152 files changed, 13470 insertions, 4095 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0006-drivers-i2c-w83795-Add-full-support-for-fan-control-.patch b/resources/libreboot/patch/kgpe-d16/0001-drivers-i2c-w83795-Add-full-support-for-fan-control-.patch
index f2f37ec..0dc1606 100644
--- a/resources/libreboot/patch/kgpe-d16/0006-drivers-i2c-w83795-Add-full-support-for-fan-control-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0001-drivers-i2c-w83795-Add-full-support-for-fan-control-.patch
@@ -1,22 +1,24 @@
-From 12a58e8598d572ee4997f0a6670796b5e82d318b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From f7b8be27ea159845a982c310799a5896865016cd Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 17:53:20 -0500
-Subject: [PATCH 006/146] drivers/i2c/w83795: Add full support for fan
- control, fan monitoring, and voltage monitoring
+Subject: [PATCH 001/139] drivers/i2c/w83795: Add full support for fan control,
+ fan monitoring, and voltage monitoring
 
+Change-Id: I3e246af0e398d65ee43ea708060885c67fd7d202
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/drivers/i2c/w83795/chip.h   |  146 +++++++++++++++++++
- src/drivers/i2c/w83795/w83795.c |  301 +++++++++++++++++++++++++++------------
- src/drivers/i2c/w83795/w83795.h |   50 +++++--
- 3 files changed, 392 insertions(+), 105 deletions(-)
+ src/drivers/i2c/w83795/chip.h   | 142 +++++++++++++++++
+ src/drivers/i2c/w83795/w83795.c | 334 ++++++++++++++++++++++++++--------------
+ src/drivers/i2c/w83795/w83795.h |  52 +++++--
+ 3 files changed, 399 insertions(+), 129 deletions(-)
  create mode 100644 src/drivers/i2c/w83795/chip.h
 
 diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h
 new file mode 100644
-index 0000000..413ea87
+index 0000000..effe119
 --- /dev/null
 +++ b/src/drivers/i2c/w83795/chip.h
-@@ -0,0 +1,146 @@
+@@ -0,0 +1,142 @@
 +/*
 + * This file is part of the coreboot project.
 + *
@@ -158,13 +160,9 @@ index 0000000..413ea87
 +	uint8_t fan6_duty;			/* % of full speed (0-100) */
 +	uint8_t fan7_duty;			/* % of full speed (0-100) */
 +	uint8_t fan8_duty;			/* % of full speed (0-100) */
-+
-+	uint8_t smbus_aux;			/* 0 == device located on first SMBUS,
-+						 * 1 == device located on auxiliary SMBUS
-+						 */
 +};
 diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c
-index 2bbe0be..0e40710 100644
+index 2bbe0be..cf0cf2f 100644
 --- a/src/drivers/i2c/w83795/w83795.c
 +++ b/src/drivers/i2c/w83795/w83795.c
 @@ -2,6 +2,7 @@
@@ -175,31 +173,29 @@ index 2bbe0be..0e40710 100644
   *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License as published by
-@@ -21,12 +22,19 @@
+@@ -21,106 +22,68 @@
  #include <arch/cpu.h>
  #include <console/console.h>
  #include <device/device.h>
 -#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/
-+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
-+#  include "southbridge/amd/sb700/smbus.h" /*SMBUS_IO_BASE*/
-+#else
-+#  include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/
-+#endif
  #include "w83795.h"
++#include <device/smbus.h>
 +#include "chip.h"
-+
-+static uint32_t smbus_io_base;
  
- static int w83795_set_bank(u8 bank)
+-static int w83795_set_bank(u8 bank)
++static int w83795_set_bank(struct device *dev, uint8_t bank)
  {
 -	return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank);
-+	return do_smbus_write_byte(smbus_io_base, W83795_DEV, W83795_REG_BANKSEL, bank);
++	return smbus_write_byte(dev, W83795_REG_BANKSEL, bank);
  }
  
- static u8 w83795_read(u16 reg)
-@@ -35,11 +43,11 @@ static u8 w83795_read(u16 reg)
+-static u8 w83795_read(u16 reg)
++static uint8_t w83795_read(struct device *dev, uint16_t reg)
+ {
+ 	int ret;
  
- 	ret = w83795_set_bank(reg >> 8);
+-	ret = w83795_set_bank(reg >> 8);
++	ret = w83795_set_bank(dev, reg >> 8);
  	if (ret < 0) {
 -		printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8);
 +		printk(BIOS_DEBUG, "read failed to set bank %x\n", reg >> 8);
@@ -207,13 +203,17 @@ index 2bbe0be..0e40710 100644
  	}
  
 -	ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff);
-+	ret = do_smbus_read_byte(smbus_io_base, W83795_DEV, reg & 0xff);
++	ret = smbus_read_byte(dev, reg & 0xff);
  	return ret;
  }
  
-@@ -49,18 +57,18 @@ static u8 w83795_write(u16 reg, u8 value)
+-static u8 w83795_write(u16 reg, u8 value)
++static uint8_t w83795_write(struct device *dev, uint16_t reg, uint8_t value)
+ {
+ 	int err;
  
- 	err = w83795_set_bank(reg >> 8);
+-	err = w83795_set_bank(reg >> 8);
++	err = w83795_set_bank(dev, reg >> 8);
  	if (err < 0) {
 -		printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8);
 +		printk(BIOS_DEBUG, "write failed to set bank %x\n", reg >> 8);
@@ -221,7 +221,7 @@ index 2bbe0be..0e40710 100644
  	}
  
 -	err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value);
-+	err = do_smbus_write_byte(smbus_io_base, W83795_DEV, reg & 0xff, value);
++	err = smbus_write_byte(dev, reg & 0xff, value);
  	return err;
  }
  
@@ -230,14 +230,15 @@ index 2bbe0be..0e40710 100644
 + * Configure Digital Temperature Sensor
   */
 -static void w83795_dts_enable(u8 dts_src)
-+static void w83795_dts_configure(u8 dts_src)
++static void w83795_dts_configure(struct device *dev, uint8_t dts_src)
  {
  	u8 val;
  
-@@ -68,45 +76,6 @@ static void w83795_dts_enable(u8 dts_src)
- 	val = w83795_read(W83795_REG_DTSC);
+ 	/* DIS */
+-	val = w83795_read(W83795_REG_DTSC);
++	val = w83795_read(dev, W83795_REG_DTSC);
  	val |= (dts_src & 0x01);
- 	w83795_write(W83795_REG_DTSC, val);
+-	w83795_write(W83795_REG_DTSC, val);
 -
 -	/* DTSE */
 -	val = w83795_read(W83795_REG_DTSE);
@@ -262,8 +263,9 @@ index 2bbe0be..0e40710 100644
 -	val = w83795_read(W83795_REG_TEMP_CTRL1);
 -	val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */
 -	w83795_write(W83795_REG_TEMP_CTRL1, val);
--}
--
++	w83795_write(dev, W83795_REG_DTSC, val);
+ }
+ 
 -static void w83795_set_tfmr(w83795_fan_mode_t mode)
 -{
 -	u8 val;
@@ -277,10 +279,29 @@ index 2bbe0be..0e40710 100644
 -
 -	for (i = 0; i < 6; i++)
 -		w83795_write(W83795_REG_TFMR(i), val);
- }
- 
- static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
-@@ -131,40 +100,12 @@ static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
+-}
+-
+-static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
++static u32 w83795_set_fan_mode(struct device *dev, w83795_fan_mode_t mode)
+ {
+ 	if (mode == SPEED_CRUISE_MODE) {
+-		w83795_write(W83795_REG_FCMS1, 0xFF);
++		w83795_write(dev, W83795_REG_FCMS1, 0xFF);
+ 		printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n");
+ 	}  else {
+-		w83795_write(W83795_REG_FCMS1, 0x00);
++		w83795_write(dev, W83795_REG_FCMS1, 0x00);
+ 		if (mode == THERMAL_CRUISE_MODE) {
+-			w83795_write(W83795_REG_FCMS2, 0x00);
++			w83795_write(dev, W83795_REG_FCMS2, 0x00);
+ 			printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n");
+ 		} else if (mode == SMART_FAN_MODE) {
+-			w83795_write(W83795_REG_FCMS2, 0x3F);
++			w83795_write(dev, W83795_REG_FCMS2, 0x3F);
+ 			printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n");
+ 		} else {
+ 			printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n");
+@@ -131,40 +94,12 @@ static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
  	return 0;
  }
  
@@ -294,7 +315,8 @@ index 2bbe0be..0e40710 100644
 -	w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */
 -}
 -
- static void w83795_set_fan(w83795_fan_mode_t mode)
+-static void w83795_set_fan(w83795_fan_mode_t mode)
++static void w83795_set_fan(struct device *dev, w83795_fan_mode_t mode)
  {
 -	u8 i;
 -
@@ -305,7 +327,8 @@ index 2bbe0be..0e40710 100644
 -	w83795_set_tfmr(mode);
 -
  	/* set fan output controlled mode (FCMS)*/
- 	w83795_set_fan_mode(mode);
+-	w83795_set_fan_mode(mode);
++	w83795_set_fan_mode(dev, mode);
  
 -	/* Set Critical Temperature to Full Speed all fan (CTFS) */
 -	for (i = 0; i < 6; i++) {
@@ -322,7 +345,7 @@ index 2bbe0be..0e40710 100644
  		/* Set the Relative Register-at SMART FAN IV Control Mode Table */
  		//SFIV TODO
  	}
-@@ -173,12 +114,45 @@ static void w83795_set_fan(w83795_fan_mode_t mode)
+@@ -173,16 +108,44 @@ static void w83795_set_fan(w83795_fan_mode_t mode)
  	//TODO
  }
  
@@ -342,7 +365,8 @@ index 2bbe0be..0e40710 100644
 +	/* Datasheet v1.41 page 44 (VSEN1 - VSEN13, VTT) */
 +	return ((millivolts / 2) >> 2);
 +}
-+
+ 
+-	if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) {
 +static uint8_t millivolts_to_limit_value_type2(int millivolts)
 +{
 +	/* Datasheet v1.41 page 44 (3VSB, 3VDD, VBAT) */
@@ -362,196 +386,212 @@ index 2bbe0be..0e40710 100644
 +	uint8_t val;
 +	uint16_t limit_value;
 +
-+	if (config->smbus_aux)
-+		smbus_io_base = SMBUS_AUX_IO_BASE;
-+	else
-+		smbus_io_base = SMBUS_IO_BASE;
- 
--	if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) {
-+	if (do_smbus_read_byte(smbus_io_base, W83795_DEV, 0x00) < 0) {
++	if (smbus_read_byte(dev, 0x00) < 0) {
  		printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n");
  		return;
  	}
-@@ -192,18 +166,156 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src)
- 	val |= W83795_REG_CONFIG_INIT;
- 	w83795_write(W83795_REG_CONFIG, val);
+-	val = w83795_read(W83795_REG_CONFIG);
++	val = w83795_read(dev, W83795_REG_CONFIG);
+ 	if ((val & W83795_REG_CONFIG_CONFIG48) == 0)
+ 		printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n");
+ 	else if ((val & W83795_REG_CONFIG_CONFIG48) == 1)
+@@ -190,35 +153,178 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src)
  
--	/* Fan monitoring setting */
--	val = 0xFF; /* FAN1-FAN8 */
--	w83795_write(W83795_REG_FANIN_CTRL1, val);
--	val = 0x3F; /* FAN9-FAN14 */
--	w83795_write(W83795_REG_FANIN_CTRL2, val);
+ 	/* Reset */
+ 	val |= W83795_REG_CONFIG_INIT;
+-	w83795_write(W83795_REG_CONFIG, val);
++	w83795_write(dev, W83795_REG_CONFIG, val);
++
 +	/* Fan monitor settings */
-+	w83795_write(W83795_REG_FANIN_CTRL1, config->fanin_ctl1);
-+	w83795_write(W83795_REG_FANIN_CTRL2, config->fanin_ctl2);
++	w83795_write(dev, W83795_REG_FANIN_CTRL1, config->fanin_ctl1);
++	w83795_write(dev, W83795_REG_FANIN_CTRL2, config->fanin_ctl2);
 +
 +	/* Temperature thresholds */
-+	w83795_write(W83795_REG_TEMP_CRIT(0), config->tr1_critical_temperature);
-+	w83795_write(W83795_REG_TEMP_CRIT_HYSTER(0), config->tr1_critical_hysteresis);
-+	w83795_write(W83795_REG_TEMP_WARN(0), config->tr1_warning_temperature);
-+	w83795_write(W83795_REG_TEMP_WARN_HYSTER(0), config->tr1_warning_hysteresis);
-+	w83795_write(W83795_REG_TEMP_CRIT(1), config->tr2_critical_temperature);
-+	w83795_write(W83795_REG_TEMP_CRIT_HYSTER(1), config->tr2_critical_hysteresis);
-+	w83795_write(W83795_REG_TEMP_WARN(1), config->tr2_warning_temperature);
-+	w83795_write(W83795_REG_TEMP_WARN_HYSTER(1), config->tr2_warning_hysteresis);
-+	w83795_write(W83795_REG_TEMP_CRIT(2), config->tr3_critical_temperature);
-+	w83795_write(W83795_REG_TEMP_CRIT_HYSTER(2), config->tr3_critical_hysteresis);
-+	w83795_write(W83795_REG_TEMP_WARN(2), config->tr3_warning_temperature);
-+	w83795_write(W83795_REG_TEMP_WARN_HYSTER(2), config->tr3_warning_hysteresis);
-+	w83795_write(W83795_REG_TEMP_CRIT(3), config->tr4_critical_temperature);
-+	w83795_write(W83795_REG_TEMP_CRIT_HYSTER(3), config->tr4_critical_hysteresis);
-+	w83795_write(W83795_REG_TEMP_WARN(3), config->tr4_warning_temperature);
-+	w83795_write(W83795_REG_TEMP_WARN_HYSTER(3), config->tr4_warning_hysteresis);
-+	w83795_write(W83795_REG_TEMP_CRIT(4), config->tr5_critical_temperature);
-+	w83795_write(W83795_REG_TEMP_CRIT_HYSTER(4), config->tr5_critical_hysteresis);
-+	w83795_write(W83795_REG_TEMP_WARN(4), config->tr5_warning_temperature);
-+	w83795_write(W83795_REG_TEMP_WARN_HYSTER(4), config->tr5_warning_hysteresis);
-+	w83795_write(W83795_REG_TEMP_CRIT(5), config->tr6_critical_temperature);
-+	w83795_write(W83795_REG_TEMP_CRIT_HYSTER(5), config->tr6_critical_hysteresis);
-+	w83795_write(W83795_REG_TEMP_WARN(5), config->tr6_warning_temperature);
-+	w83795_write(W83795_REG_TEMP_WARN_HYSTER(5), config->tr6_warning_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_CRIT(0), config->tr1_critical_temperature);
++	w83795_write(dev, W83795_REG_TEMP_CRIT_HYSTER(0), config->tr1_critical_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_WARN(0), config->tr1_warning_temperature);
++	w83795_write(dev, W83795_REG_TEMP_WARN_HYSTER(0), config->tr1_warning_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_CRIT(1), config->tr2_critical_temperature);
++	w83795_write(dev, W83795_REG_TEMP_CRIT_HYSTER(1), config->tr2_critical_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_WARN(1), config->tr2_warning_temperature);
++	w83795_write(dev, W83795_REG_TEMP_WARN_HYSTER(1), config->tr2_warning_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_CRIT(2), config->tr3_critical_temperature);
++	w83795_write(dev, W83795_REG_TEMP_CRIT_HYSTER(2), config->tr3_critical_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_WARN(2), config->tr3_warning_temperature);
++	w83795_write(dev, W83795_REG_TEMP_WARN_HYSTER(2), config->tr3_warning_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_CRIT(3), config->tr4_critical_temperature);
++	w83795_write(dev, W83795_REG_TEMP_CRIT_HYSTER(3), config->tr4_critical_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_WARN(3), config->tr4_warning_temperature);
++	w83795_write(dev, W83795_REG_TEMP_WARN_HYSTER(3), config->tr4_warning_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_CRIT(4), config->tr5_critical_temperature);
++	w83795_write(dev, W83795_REG_TEMP_CRIT_HYSTER(4), config->tr5_critical_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_WARN(4), config->tr5_warning_temperature);
++	w83795_write(dev, W83795_REG_TEMP_WARN_HYSTER(4), config->tr5_warning_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_CRIT(5), config->tr6_critical_temperature);
++	w83795_write(dev, W83795_REG_TEMP_CRIT_HYSTER(5), config->tr6_critical_hysteresis);
++	w83795_write(dev, W83795_REG_TEMP_WARN(5), config->tr6_warning_temperature);
++	w83795_write(dev, W83795_REG_TEMP_WARN_HYSTER(5), config->tr6_warning_hysteresis);
 +
 +	/* DTS enable */
-+	w83795_write(W83795_REG_DTSE, config->temp_dtse);
++	w83795_write(dev, W83795_REG_DTSE, config->temp_dtse);
 +
 +	/* DTS temperature thresholds */
-+	w83795_write(W83795_REG_DTS_CRIT, config->dts_critical_temperature);
-+	w83795_write(W83795_REG_DTS_CRIT_HYSTER, config->dts_critical_hysteresis);
-+	w83795_write(W83795_REG_DTS_WARN, config->dts_warning_temperature);
-+	w83795_write(W83795_REG_DTS_WARN_HYSTER, config->dts_warning_hysteresis);
++	w83795_write(dev, W83795_REG_DTS_CRIT, config->dts_critical_temperature);
++	w83795_write(dev, W83795_REG_DTS_CRIT_HYSTER, config->dts_critical_hysteresis);
++	w83795_write(dev, W83795_REG_DTS_WARN, config->dts_warning_temperature);
++	w83795_write(dev, W83795_REG_DTS_WARN_HYSTER, config->dts_warning_hysteresis);
 +
 +	/* Configure DTS registers in bank3 before enabling DTS */
-+	w83795_dts_configure(dts_src);
++	w83795_dts_configure(dev, dts_src);
 +
 +	/* Temperature monitor settings */
-+	w83795_write(W83795_REG_TEMP_CTRL1, config->temp_ctl1);
-+	w83795_write(W83795_REG_TEMP_CTRL2, config->temp_ctl2);
++	w83795_write(dev, W83795_REG_TEMP_CTRL1, config->temp_ctl1);
++	w83795_write(dev, W83795_REG_TEMP_CTRL2, config->temp_ctl2);
 +
 +	/* Temperature to fan mappings */
-+	w83795_write(W83795_REG_TFMR(0), config->temp1_fan_select);
-+	w83795_write(W83795_REG_TFMR(1), config->temp2_fan_select);
-+	w83795_write(W83795_REG_TFMR(2), config->temp3_fan_select);
-+	w83795_write(W83795_REG_TFMR(3), config->temp4_fan_select);
-+	w83795_write(W83795_REG_TFMR(4), config->temp5_fan_select);
-+	w83795_write(W83795_REG_TFMR(5), config->temp6_fan_select);
++	w83795_write(dev, W83795_REG_TFMR(0), config->temp1_fan_select);
++	w83795_write(dev, W83795_REG_TFMR(1), config->temp2_fan_select);
++	w83795_write(dev, W83795_REG_TFMR(2), config->temp3_fan_select);
++	w83795_write(dev, W83795_REG_TFMR(3), config->temp4_fan_select);
++	w83795_write(dev, W83795_REG_TFMR(4), config->temp5_fan_select);
++	w83795_write(dev, W83795_REG_TFMR(5), config->temp6_fan_select);
 +
 +	/* Temperature data source to temperature mappings */
-+	w83795_write(W83795_REG_T12TSS, ((config->temp2_source_select & 0xff) << 8) | (config->temp1_source_select & 0xff));
-+	w83795_write(W83795_REG_T34TSS, ((config->temp4_source_select & 0xff) << 8) | (config->temp3_source_select & 0xff));
-+	w83795_write(W83795_REG_T56TSS, ((config->temp6_source_select & 0xff) << 8) | (config->temp5_source_select & 0xff));
++	w83795_write(dev, W83795_REG_T12TSS, ((config->temp2_source_select & 0xff) << 8) | (config->temp1_source_select & 0xff));
++	w83795_write(dev, W83795_REG_T34TSS, ((config->temp4_source_select & 0xff) << 8) | (config->temp3_source_select & 0xff));
++	w83795_write(dev, W83795_REG_T56TSS, ((config->temp6_source_select & 0xff) << 8) | (config->temp5_source_select & 0xff));
  
+-	/* Fan monitoring setting */
+-	val = 0xFF; /* FAN1-FAN8 */
+-	w83795_write(W83795_REG_FANIN_CTRL1, val);
+-	val = 0x3F; /* FAN9-FAN14 */
+-	w83795_write(W83795_REG_FANIN_CTRL2, val);
+-
 -	/* enable monitoring operations */
 -	val = w83795_read(W83795_REG_CONFIG);
 -	val |= W83795_REG_CONFIG_START;
 -	w83795_write(W83795_REG_CONFIG, val);
+-
+-	w83795_dts_enable(dts_src);
+-	w83795_set_fan(mode);
 +	/* Set Critical Temperature to Full Speed all fan (CTFS) */
-+	w83795_write(W83795_REG_CTFS(0), config->temp1_critical_temperature);
-+	w83795_write(W83795_REG_CTFS(1), config->temp2_critical_temperature);
-+	w83795_write(W83795_REG_CTFS(2), config->temp3_critical_temperature);
-+	w83795_write(W83795_REG_CTFS(3), config->temp4_critical_temperature);
-+	w83795_write(W83795_REG_CTFS(4), config->temp5_critical_temperature);
-+	w83795_write(W83795_REG_CTFS(5), config->temp6_critical_temperature);
++	w83795_write(dev, W83795_REG_CTFS(0), config->temp1_critical_temperature);
++	w83795_write(dev, W83795_REG_CTFS(1), config->temp2_critical_temperature);
++	w83795_write(dev, W83795_REG_CTFS(2), config->temp3_critical_temperature);
++	w83795_write(dev, W83795_REG_CTFS(3), config->temp4_critical_temperature);
++	w83795_write(dev, W83795_REG_CTFS(4), config->temp5_critical_temperature);
++	w83795_write(dev, W83795_REG_CTFS(5), config->temp6_critical_temperature);
 +
 +	/* Set fan control target temperatures */
-+	w83795_write(W83795_REG_TTTI(0), config->temp1_target_temperature);
-+	w83795_write(W83795_REG_TTTI(1), config->temp2_target_temperature);
-+	w83795_write(W83795_REG_TTTI(2), config->temp3_target_temperature);
-+	w83795_write(W83795_REG_TTTI(3), config->temp4_target_temperature);
-+	w83795_write(W83795_REG_TTTI(4), config->temp5_target_temperature);
-+	w83795_write(W83795_REG_TTTI(5), config->temp6_target_temperature);
++	w83795_write(dev, W83795_REG_TTTI(0), config->temp1_target_temperature);
++	w83795_write(dev, W83795_REG_TTTI(1), config->temp2_target_temperature);
++	w83795_write(dev, W83795_REG_TTTI(2), config->temp3_target_temperature);
++	w83795_write(dev, W83795_REG_TTTI(3), config->temp4_target_temperature);
++	w83795_write(dev, W83795_REG_TTTI(4), config->temp5_target_temperature);
++	w83795_write(dev, W83795_REG_TTTI(5), config->temp6_target_temperature);
 +
 +	/* Set fan stall prevention parameters */
-+	w83795_write(W83795_REG_FAN_NONSTOP(0), config->fan1_nonstop);
-+	w83795_write(W83795_REG_FAN_NONSTOP(1), config->fan2_nonstop);
-+	w83795_write(W83795_REG_FAN_NONSTOP(2), config->fan3_nonstop);
-+	w83795_write(W83795_REG_FAN_NONSTOP(3), config->fan4_nonstop);
-+	w83795_write(W83795_REG_FAN_NONSTOP(4), config->fan5_nonstop);
-+	w83795_write(W83795_REG_FAN_NONSTOP(5), config->fan6_nonstop);
-+	w83795_write(W83795_REG_FAN_NONSTOP(6), config->fan7_nonstop);
-+	w83795_write(W83795_REG_FAN_NONSTOP(7), config->fan8_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(0), config->fan1_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(1), config->fan2_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(2), config->fan3_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(3), config->fan4_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(4), config->fan5_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(5), config->fan6_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(6), config->fan7_nonstop);
++	w83795_write(dev, W83795_REG_FAN_NONSTOP(7), config->fan8_nonstop);
 +
 +	/* Set fan default speed */
-+	w83795_write(W83795_REG_DFSP, fan_pct_to_cfg_val(config->default_speed));
++	w83795_write(dev, W83795_REG_DFSP, fan_pct_to_cfg_val(config->default_speed));
 +
 +	/* Set initial fan speeds */
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(0), fan_pct_to_cfg_val(config->fan1_duty));
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(1), fan_pct_to_cfg_val(config->fan2_duty));
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(2), fan_pct_to_cfg_val(config->fan3_duty));
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(3), fan_pct_to_cfg_val(config->fan4_duty));
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(4), fan_pct_to_cfg_val(config->fan5_duty));
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(5), fan_pct_to_cfg_val(config->fan6_duty));
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(6), fan_pct_to_cfg_val(config->fan7_duty));
-+	w83795_write(W83795_REG_FAN_MANUAL_SPEED(7), fan_pct_to_cfg_val(config->fan8_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(0), fan_pct_to_cfg_val(config->fan1_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(1), fan_pct_to_cfg_val(config->fan2_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(2), fan_pct_to_cfg_val(config->fan3_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(3), fan_pct_to_cfg_val(config->fan4_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(4), fan_pct_to_cfg_val(config->fan5_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(5), fan_pct_to_cfg_val(config->fan6_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(6), fan_pct_to_cfg_val(config->fan7_duty));
++	w83795_write(dev, W83795_REG_FAN_MANUAL_SPEED(7), fan_pct_to_cfg_val(config->fan8_duty));
 +
 +	/* Voltage monitor settings */
-+	w83795_write(W83795_REG_VOLT_CTRL1, config->volt_ctl1);
-+	w83795_write(W83795_REG_VOLT_CTRL2, config->volt_ctl2);
++	w83795_write(dev, W83795_REG_VOLT_CTRL1, config->volt_ctl1);
++	w83795_write(dev, W83795_REG_VOLT_CTRL2, config->volt_ctl2);
 +
 +	/* Voltage high/low limits */
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(0), millivolts_to_limit_value_type1(config->vcore1_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(0), millivolts_to_limit_value_type1(config->vcore1_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(1), millivolts_to_limit_value_type1(config->vcore2_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(1), millivolts_to_limit_value_type1(config->vcore2_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(2), millivolts_to_limit_value_type1(config->vsen3_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(2), millivolts_to_limit_value_type1(config->vsen3_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(3), millivolts_to_limit_value_type1(config->vsen4_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(3), millivolts_to_limit_value_type1(config->vsen4_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(4), millivolts_to_limit_value_type1(config->vsen5_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(4), millivolts_to_limit_value_type1(config->vsen5_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(5), millivolts_to_limit_value_type1(config->vsen6_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(5), millivolts_to_limit_value_type1(config->vsen6_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(6), millivolts_to_limit_value_type1(config->vsen7_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(6), millivolts_to_limit_value_type1(config->vsen7_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(7), millivolts_to_limit_value_type1(config->vsen8_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(7), millivolts_to_limit_value_type1(config->vsen8_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(8), millivolts_to_limit_value_type1(config->vsen9_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(8), millivolts_to_limit_value_type1(config->vsen9_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(9), millivolts_to_limit_value_type1(config->vsen10_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(9), millivolts_to_limit_value_type1(config->vsen10_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(10), millivolts_to_limit_value_type1(config->vsen11_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(10), millivolts_to_limit_value_type1(config->vsen11_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(11), millivolts_to_limit_value_type1(config->vtt_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(11), millivolts_to_limit_value_type1(config->vtt_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(12), millivolts_to_limit_value_type2(config->vdd_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(12), millivolts_to_limit_value_type2(config->vdd_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(13), millivolts_to_limit_value_type2(config->vsb_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(13), millivolts_to_limit_value_type2(config->vsb_low_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH(14), millivolts_to_limit_value_type2(config->vbat_high_limit_mv));
-+	w83795_write(W83795_REG_VOLT_LIM_LOW(14), millivolts_to_limit_value_type2(config->vbat_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(0), millivolts_to_limit_value_type1(config->vcore1_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(0), millivolts_to_limit_value_type1(config->vcore1_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(1), millivolts_to_limit_value_type1(config->vcore2_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(1), millivolts_to_limit_value_type1(config->vcore2_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(2), millivolts_to_limit_value_type1(config->vsen3_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(2), millivolts_to_limit_value_type1(config->vsen3_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(3), millivolts_to_limit_value_type1(config->vsen4_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(3), millivolts_to_limit_value_type1(config->vsen4_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(4), millivolts_to_limit_value_type1(config->vsen5_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(4), millivolts_to_limit_value_type1(config->vsen5_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(5), millivolts_to_limit_value_type1(config->vsen6_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(5), millivolts_to_limit_value_type1(config->vsen6_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(6), millivolts_to_limit_value_type1(config->vsen7_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(6), millivolts_to_limit_value_type1(config->vsen7_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(7), millivolts_to_limit_value_type1(config->vsen8_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(7), millivolts_to_limit_value_type1(config->vsen8_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(8), millivolts_to_limit_value_type1(config->vsen9_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(8), millivolts_to_limit_value_type1(config->vsen9_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(9), millivolts_to_limit_value_type1(config->vsen10_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(9), millivolts_to_limit_value_type1(config->vsen10_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(10), millivolts_to_limit_value_type1(config->vsen11_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(10), millivolts_to_limit_value_type1(config->vsen11_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(11), millivolts_to_limit_value_type1(config->vtt_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(11), millivolts_to_limit_value_type1(config->vtt_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(12), millivolts_to_limit_value_type2(config->vdd_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(12), millivolts_to_limit_value_type2(config->vdd_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(13), millivolts_to_limit_value_type2(config->vsb_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(13), millivolts_to_limit_value_type2(config->vsb_low_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH(14), millivolts_to_limit_value_type2(config->vbat_high_limit_mv));
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW(14), millivolts_to_limit_value_type2(config->vbat_low_limit_mv));
 +
 +	/* VSEN12 limits */
 +	limit_value = millivolts_to_limit_value_type3(config->vsen12_high_limit_mv);
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH_2_M(4), limit_value >> 2);
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH_2_L(4), limit_value & 0x3);
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_M(4), limit_value >> 2);
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_L(4), limit_value & 0x3);
 +	limit_value = millivolts_to_limit_value_type3(config->vsen12_low_limit_mv);
-+	w83795_write(W83795_REG_VOLT_LIM_LOW_2_M(4), limit_value >> 2);
-+	w83795_write(W83795_REG_VOLT_LIM_LOW_2_L(4), limit_value & 0x3);
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_M(4), limit_value >> 2);
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_L(4), limit_value & 0x3);
 +
 +	/* VSEN13 limits */
 +	limit_value = millivolts_to_limit_value_type3(config->vsen13_high_limit_mv);
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH_2_M(5), limit_value >> 2);
-+	w83795_write(W83795_REG_VOLT_LIM_HIGH_2_L(5), limit_value & 0x3);
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_M(5), limit_value >> 2);
++	w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_L(5), limit_value & 0x3);
 +	limit_value = millivolts_to_limit_value_type3(config->vsen13_low_limit_mv);
-+	w83795_write(W83795_REG_VOLT_LIM_LOW_2_M(5), limit_value >> 2);
-+	w83795_write(W83795_REG_VOLT_LIM_LOW_2_L(5), limit_value & 0x3);
- 
--	w83795_dts_enable(dts_src);
- 	w83795_set_fan(mode);
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_M(5), limit_value >> 2);
++	w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_L(5), limit_value & 0x3);
++
++	w83795_set_fan(dev, mode);
  
  	printk(BIOS_INFO, "Fan   CTFS(celsius)  TTTI(celsius)\n");
-@@ -219,6 +331,11 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src)
- 		val = w83795_read(W83795_REG_DTS(i));
+ 	for (i = 0; i < 6; i++) {
+-		val = w83795_read(W83795_REG_CTFS(i));
++		val = w83795_read(dev, W83795_REG_CTFS(i));
+ 		printk(BIOS_INFO, " %x     %d", i, val);
+-		val = w83795_read(W83795_REG_TTTI(i));
++		val = w83795_read(dev, W83795_REG_TTTI(i));
+ 		printk(BIOS_INFO, "             %d\n", val);
+ 	}
+ 
+ 	/* Temperature ReadOut */
+ 	for (i = 0; i < 9; i++) {
+-		val = w83795_read(W83795_REG_DTS(i));
++		val = w83795_read(dev, W83795_REG_DTS(i));
  		printk(BIOS_DEBUG, "DTS%x ReadOut=%x\n", i, val);
  	}
 +
 +	/* start monitoring operation */
-+	val = w83795_read(W83795_REG_CONFIG);
++	val = w83795_read(dev, W83795_REG_CONFIG);
 +	val |= W83795_REG_CONFIG_START;
-+	w83795_write(W83795_REG_CONFIG, val);
++	w83795_write(dev, W83795_REG_CONFIG, val);
  }
  
  static void w83795_hwm_init(struct device *dev)
-@@ -232,9 +349,9 @@ static void w83795_hwm_init(struct device *dev)
+@@ -232,9 +338,9 @@ static void w83795_hwm_init(struct device *dev)
  		die("CPU: missing cpu device structure");
  
  	if (cpu->vendor == X86_VENDOR_AMD)
@@ -564,7 +604,7 @@ index 2bbe0be..0e40710 100644
  		printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n");
  }
 diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h
-index cac4d5f..59fa273 100644
+index cac4d5f..0727dc5 100644
 --- a/src/drivers/i2c/w83795/w83795.h
 +++ b/src/drivers/i2c/w83795/w83795.h
 @@ -2,6 +2,7 @@
@@ -575,7 +615,16 @@ index cac4d5f..59fa273 100644
   *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License as published by
-@@ -29,6 +30,8 @@
+@@ -20,8 +21,6 @@
+ #ifndef _W83795_H_
+ #define _W83795_H_
+ 
+-#define W83795_DEV			0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */
+-
+ #define W83795_REG_I2C_ADDR		0xFC
+ #define W83795_REG_BANKSEL		0x00
+ #define W83795_REG_CONFIG		0x01
+@@ -29,6 +28,8 @@
  #define W83795_REG_CONFIG_CONFIG48	0x04
  #define W83795_REG_CONFIG_INIT		0x80
  
@@ -584,7 +633,7 @@ index cac4d5f..59fa273 100644
  #define W83795_REG_TEMP_CTRL1		0x04 /* Temperature Monitoring Control Register */
  #define W83795_REG_TEMP_CTRL2		0x05 /* Temperature Monitoring Control Register */
  #define W83795_REG_FANIN_CTRL1		0x06
-@@ -37,37 +40,58 @@
+@@ -37,37 +38,58 @@
  #define DTS_SRC_INTEL_PECI		(0 << 0)
  #define DTS_SRC_AMD_SBTSI		(1 << 0)
  
@@ -657,5 +706,5 @@ index cac4d5f..59fa273 100644
  
  #endif
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0001-util-cbmem-Fix-failure-with-certain-cbmem-base-align.patch b/resources/libreboot/patch/kgpe-d16/0001-util-cbmem-Fix-failure-with-certain-cbmem-base-align.patch
deleted file mode 100644
index 84c51ba..0000000
--- a/resources/libreboot/patch/kgpe-d16/0001-util-cbmem-Fix-failure-with-certain-cbmem-base-align.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From 4e0a69562a189e9abe06979a993f50e3f0b2069b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Sat, 5 Sep 2015 18:07:17 -0500
-Subject: [PATCH 001/146] util/cbmem: Fix failure with certain cbmem base
- alignments
-
----
- util/cbmem/cbmem.c |   61 ++++++++++++++++++++++++++++++++--------------------
- 1 file changed, 38 insertions(+), 23 deletions(-)
-
-diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
-index 74cb52d..69ffbaf 100644
---- a/util/cbmem/cbmem.c
-+++ b/util/cbmem/cbmem.c
-@@ -2,6 +2,7 @@
-  * This file is part of the coreboot project.
-  *
-  * Copyright 2012 Google Inc.
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-@@ -103,8 +104,7 @@ static void unmap_memory(void)
- 	if (size_to_mib(mapped_size) == 0) {
- 		debug("Unmapping %zuMB of virtual memory at %p.\n",
- 		      size_to_mib(mapped_size), mapped_virtual);
--	}
--	else {
-+	} else {
- 		debug("Unmapping %zuMB of virtual memory at %p.\n",
- 		      size_to_mib(mapped_size), mapped_virtual);
- 	}
-@@ -113,7 +113,7 @@ static void unmap_memory(void)
- 	mapped_size = 0;
- }
- 
--static void *map_memory_size(u64 physical, size_t size)
-+static void *map_memory_size(u64 physical, size_t size, uint8_t abort_on_failure)
- {
- 	void *v;
- 	off_t p;
-@@ -131,8 +131,7 @@ static void *map_memory_size(u64 physical, size_t size)
- 	if (size_to_mib(size) == 0) {
- 		debug("Mapping %zuB of physical memory at 0x%jx (requested 0x%jx).\n",
- 		      size, (intmax_t)p, (intmax_t)physical);
--	}
--	else {
-+	} else {
- 		debug("Mapping %zuMB of physical memory at 0x%jx (requested 0x%jx).\n",
- 		      size_to_mib(size), (intmax_t)p, (intmax_t)physical);
- 	}
-@@ -153,9 +152,13 @@ static void *map_memory_size(u64 physical, size_t size)
- 	}
- 
- 	if (v == MAP_FAILED) {
--		fprintf(stderr, "Failed to mmap /dev/mem: %s\n",
--			strerror(errno));
--		exit(1);
-+		if (abort_on_failure) {
-+			fprintf(stderr, "Failed to mmap /dev/mem: %s\n",
-+				strerror(errno));
-+			exit(1);
-+		} else {
-+			return 0;
-+		}
- 	}
- 
- 	/* Remember what we actually mapped ... */
-@@ -173,7 +176,7 @@ static void *map_memory_size(u64 physical, size_t size)
- 
- static void *map_memory(u64 physical)
- {
--	return map_memory_size(physical, MAP_BYTES);
-+	return map_memory_size(physical, MAP_BYTES, 1);
- }
- 
- /*
-@@ -210,14 +213,16 @@ static struct lb_cbmem_ref parse_cbmem_ref(struct lb_cbmem_ref *cbmem_ref)
- 	return ret;
- }
- 
--static int parse_cbtable(u64 address, size_t table_size)
-+static int parse_cbtable(u64 address, size_t table_size, uint8_t abort_on_failure)
- {
--	int i, found = 0;
-+	int i, found, ret = 0;
- 	void *buf;
- 
- 	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n",
- 		address, table_size);
--	buf = map_memory_size(address, table_size);
-+	buf = map_memory_size(address, table_size, abort_on_failure);
-+	if (!buf)
-+		return -2;
- 
- 	/* look at every 16 bytes within 4K of the base */
- 
-@@ -283,7 +288,17 @@ static int parse_cbtable(u64 address, size_t table_size)
- 					*(struct lb_forward *) lbr_p;
- 				debug("    Found forwarding entry.\n");
- 				unmap_memory();
--				return parse_cbtable(lbf_p.forward, table_size);
-+				ret = parse_cbtable(lbf_p.forward, table_size, 0);
-+				if (ret == -2) {
-+					/* try again with a smaller memory mapping request */
-+					ret = parse_cbtable(lbf_p.forward, table_size / 2, 1);
-+					if (ret == -2)
-+						exit(1);
-+					else
-+						return ret;
-+				} else {
-+					return ret;
-+				}
- 			}
- 			default:
- 				break;
-@@ -544,7 +559,7 @@ static void dump_timestamps(int mach_readable)
- 	}
- 
- 	size = sizeof(*tst_p);
--	tst_p = map_memory_size((unsigned long)timestamps.cbmem_addr, size);
-+	tst_p = map_memory_size((unsigned long)timestamps.cbmem_addr, size, 1);
- 
- 	timestamp_set_tick_freq(tst_p->tick_freq_mhz);
- 
-@@ -553,7 +568,7 @@ static void dump_timestamps(int mach_readable)
- 	size += tst_p->num_entries * sizeof(tst_p->entries[0]);
- 
- 	unmap_memory();
--	tst_p = map_memory_size((unsigned long)timestamps.cbmem_addr, size);
-+	tst_p = map_memory_size((unsigned long)timestamps.cbmem_addr, size, 1);
- 
- 	/* Report the base time within the table. */
- 	prev_stamp = 0;
-@@ -604,7 +619,7 @@ static void dump_console(void)
- 	}
- 
- 	console_p = map_memory_size((unsigned long)console.cbmem_addr,
--					2 * sizeof(uint32_t));
-+					2 * sizeof(uint32_t), 1);
- 	/* The in-memory format of the console area is:
- 	 *  u32  size
- 	 *  u32  cursor
-@@ -626,7 +641,7 @@ static void dump_console(void)
- 	}
- 
- 	console_p = map_memory_size((unsigned long)console.cbmem_addr,
--	                            size + sizeof(size) + sizeof(cursor));
-+	                            size + sizeof(size) + sizeof(cursor), 1);
- 	memcpy(console_c, console_p + 8, size);
- 	console_c[size] = 0;
- 	console_c[cursor] = 0;
-@@ -647,7 +662,7 @@ static void hexdump(unsigned long memory, int length)
- 	uint8_t *m;
- 	int all_zero = 0;
- 
--	m = map_memory_size((intptr_t)memory, length);
-+	m = map_memory_size((intptr_t)memory, length, 1);
- 
- 	if (length > MAP_BYTES) {
- 		printf("Truncating hex dump from %d to %d bytes\n\n",
-@@ -803,7 +818,7 @@ static void dump_cbmem_toc(void)
- 
- 	start = unpack_lb64(cbmem.start);
- 
--	cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size));
-+	cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size), 1);
- 	entries = (struct cbmem_entry *)cbmem_area;
- 
- 	if (entries[0].magic == CBMEM_MAGIC) {
-@@ -814,12 +829,12 @@ static void dump_cbmem_toc(void)
- 		rootptr -= sizeof(struct cbmem_root_pointer);
- 		unmap_memory();
- 		struct cbmem_root_pointer *r =
--			map_memory_size(rootptr, sizeof(*r));
-+			map_memory_size(rootptr, sizeof(*r), 1);
- 		if (r->magic == CBMEM_POINTER_MAGIC) {
- 			struct cbmem_root *root;
- 			uint64_t rootaddr = rootptr + r->root_offset;
- 			unmap_memory();
--			root = map_memory_size(rootaddr, ROOT_MIN_SIZE);
-+			root = map_memory_size(rootaddr, ROOT_MIN_SIZE, 1);
- 			dump_dynamic_cbmem_toc(root);
- 		} else
- 			fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n");
-@@ -1205,14 +1220,14 @@ int main(int argc, char** argv)
- 		dtbuffer++;
- 	}
- 
--	parse_cbtable(baseaddr, cb_table_size);
-+	parse_cbtable(baseaddr, cb_table_size, 1);
- #else
- 	int j;
- 	static const int possible_base_addresses[] = { 0, 0xf0000 };
- 
- 	/* Find and parse coreboot table */
- 	for (j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) {
--		if (parse_cbtable(possible_base_addresses[j], MAP_BYTES))
-+		if (parse_cbtable(possible_base_addresses[j], MAP_BYTES, 1))
- 			break;
- 	}
- #endif
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0002-cpu-amd-microcode-Update-microcode-parser-to-handle-.patch b/resources/libreboot/patch/kgpe-d16/0002-cpu-amd-microcode-Update-microcode-parser-to-handle-.patch
deleted file mode 100644
index 960cfa8..0000000
--- a/resources/libreboot/patch/kgpe-d16/0002-cpu-amd-microcode-Update-microcode-parser-to-handle-.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From f65e4abec63a8ec3bfb5a784cecb7405c463c038 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Tue, 11 Aug 2015 19:14:34 -0500
-Subject: [PATCH 002/146] cpu/amd/microcode: Update microcode parser to handle
- expanded blob files
-
----
- src/cpu/amd/microcode/microcode.c |    5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
-index 45e4bf0..ce5b08f 100644
---- a/src/cpu/amd/microcode/microcode.c
-+++ b/src/cpu/amd/microcode/microcode.c
-@@ -2,6 +2,7 @@
-  * This file is part of the coreboot project.
-  *
-  * Copyright (C) 2007 Advanced Micro Devices, Inc.
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-@@ -83,13 +84,13 @@ static void amd_update_microcode(const void *ucode,  size_t ucode_len,
- 	const uint8_t *c = ucode;
- 	const uint8_t *ucode_end = (uint8_t*)ucode + ucode_len;
- 
--	while (c <= (ucode_end - 2048)) {
-+	while (c <= (ucode_end - 4096)) {
- 		m = (struct microcode *)c;
- 		if (m->processor_rev_id == equivalent_processor_rev_id) {
- 			apply_microcode_patch(m);
- 			break;
- 		}
--		c += 2048;
-+		c += 4096;
- 	}
- }
- 
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0002-southbridge-amd-sb700-Allow-use-of-auxiliary-SMBUS-c.patch b/resources/libreboot/patch/kgpe-d16/0002-southbridge-amd-sb700-Allow-use-of-auxiliary-SMBUS-c.patch
new file mode 100644
index 0000000..651c973
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0002-southbridge-amd-sb700-Allow-use-of-auxiliary-SMBUS-c.patch
@@ -0,0 +1,187 @@
+From 6ae8695f880a4a15672eda801226b4b1c83aa1a8 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sat, 17 Oct 2015 04:36:47 -0500
+Subject: [PATCH 002/139] southbridge/amd/sb700: Allow use of auxiliary SMBUS
+ controller
+
+Change-Id: I29ece10eeefc2c75a3829c169f1e1aede7194ec2
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/device/Kconfig                |  4 ++++
+ src/include/device/smbus.h        |  5 +++++
+ src/southbridge/amd/sb700/Kconfig |  1 +
+ src/southbridge/amd/sb700/sm.c    | 36 +++++++++++++++++++++++++++++++-----
+ src/southbridge/amd/sb700/smbus.c | 15 +++++++++++++++
+ 5 files changed, 56 insertions(+), 5 deletions(-)
+
+diff --git a/src/device/Kconfig b/src/device/Kconfig
+index 613461b..3dd2b61 100644
+--- a/src/device/Kconfig
++++ b/src/device/Kconfig
+@@ -192,6 +192,10 @@ config MULTIPLE_VGA_ADAPTERS
+ 	bool
+ 	default n
+ 
++config SMBUS_HAS_AUX
++	bool
++	default n
++
+ config SPD_CACHE
+ 	bool
+ 	default n
+diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h
+index 073d7e2..53e90fb 100644
+--- a/src/include/device/smbus.h
++++ b/src/include/device/smbus.h
+@@ -47,4 +47,9 @@ int smbus_process_call(device_t dev, u8 cmd, u16 data);
+ int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer);
+ int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer);
+ 
++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX)
++void smbus_switch_to_aux(uint8_t enable_aux);
++uint8_t smbus_switched_to_aux(void);
++#endif
++
+ #endif /* DEVICE_SMBUS_H */
+diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
+index 42ca2bb..a5dfe07 100644
+--- a/src/southbridge/amd/sb700/Kconfig
++++ b/src/southbridge/amd/sb700/Kconfig
+@@ -27,6 +27,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
+ 	select IOAPIC
+ 	select HAVE_USBDEBUG_OPTIONS
+ 	select HAVE_HARD_RESET
++	select SMBUS_HAS_AUX
+ 
+ # Set for southbridge SP5100 which also uses SB700 driver
+ config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
+index f544c88..c216e1f 100644
+--- a/src/southbridge/amd/sb700/sm.c
++++ b/src/southbridge/amd/sb700/sm.c
+@@ -40,6 +40,8 @@
+ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+ #endif
+ 
++uint8_t smbus_use_aux = 0;
++
+ /*
+ * SB700 enables all USB controllers by default in SMBUS Control.
+ * SB700 enables SATA by default in SMBUS Control.
+@@ -312,7 +314,10 @@ static int lsmbus_recv_byte(device_t dev)
+ 	device = dev->path.i2c.device;
+ 	pbus = get_pbus_smbus(dev);
+ 
+-	res = find_resource(pbus->dev, 0x90);
++	if (!smbus_use_aux)
++		res = find_resource(pbus->dev, 0x90);
++	else
++		res = find_resource(pbus->dev, 0x58);
+ 
+ 	return do_smbus_recv_byte(res->base, device);
+ }
+@@ -326,7 +331,10 @@ static int lsmbus_send_byte(device_t dev, u8 val)
+ 	device = dev->path.i2c.device;
+ 	pbus = get_pbus_smbus(dev);
+ 
+-	res = find_resource(pbus->dev, 0x90);
++	if (!smbus_use_aux)
++		res = find_resource(pbus->dev, 0x90);
++	else
++		res = find_resource(pbus->dev, 0x58);
+ 
+ 	return do_smbus_send_byte(res->base, device, val);
+ }
+@@ -340,7 +348,10 @@ static int lsmbus_read_byte(device_t dev, u8 address)
+ 	device = dev->path.i2c.device;
+ 	pbus = get_pbus_smbus(dev);
+ 
+-	res = find_resource(pbus->dev, 0x90);
++	if (!smbus_use_aux)
++		res = find_resource(pbus->dev, 0x90);
++	else
++		res = find_resource(pbus->dev, 0x58);
+ 
+ 	return do_smbus_read_byte(res->base, device, address);
+ }
+@@ -354,7 +365,10 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+ 	device = dev->path.i2c.device;
+ 	pbus = get_pbus_smbus(dev);
+ 
+-	res = find_resource(pbus->dev, 0x90);
++	if (!smbus_use_aux)
++		res = find_resource(pbus->dev, 0x90);
++	else
++		res = find_resource(pbus->dev, 0x58);
+ 
+ 	return do_smbus_write_byte(res->base, device, address, val);
+ }
+@@ -393,7 +407,7 @@ static void sb700_sm_read_resources(device_t dev)
+ 
+ 	/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
+ 
+-	/* smbus */
++	/* primary smbus */
+ 	res = new_resource(dev, 0x90);
+ 	res->base  = 0xB00;
+ 	res->size = 0x10;
+@@ -402,6 +416,15 @@ static void sb700_sm_read_resources(device_t dev)
+ 	res->gran = 8;
+ 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
+ 
++	/* auxiliary smbus */
++	res = new_resource(dev, 0x58);
++	res->base  = 0xB20;
++	res->size = 0x10;
++	res->limit = 0xFFFFUL;	/* res->base + res->size -1; */
++	res->align = 8;
++	res->gran = 8;
++	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
++
+ 	compact_resources(dev);
+ }
+ 
+@@ -441,6 +464,9 @@ static void sb700_sm_set_resources(struct device *dev)
+ 
+ 	res = find_resource(dev, 0x90);
+ 	pci_write_config32(dev, 0x90, res->base | 1);
++
++	res = find_resource(dev, 0x58);
++	pci_write_config32(dev, 0x58, res->base | 1);
+ }
+ 
+ static struct pci_operations lops_pci = {
+diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c
+index 94f5e24..a89e830 100644
+--- a/src/southbridge/amd/sb700/smbus.c
++++ b/src/southbridge/amd/sb700/smbus.c
+@@ -22,6 +22,11 @@
+ 
+ #include "smbus.h"
+ 
++extern uint8_t smbus_use_aux;
++
++void smbus_switch_to_aux(uint8_t enable_aux);
++uint8_t smbus_switched_to_aux(void);
++
+ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+ {
+ 	u32 tmp;
+@@ -216,4 +221,14 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
+ 	return 0;
+ }
+ 
++void smbus_switch_to_aux(uint8_t enable_aux)
++{
++	smbus_use_aux = enable_aux;
++}
++
++uint8_t smbus_switched_to_aux(void)
++{
++	return smbus_use_aux;
++}
++
+ #endif
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0003-arch-x86-boot-smbios-Add-SPD-IDs-for-Kingston-and-Co.patch b/resources/libreboot/patch/kgpe-d16/0003-arch-x86-boot-smbios-Add-SPD-IDs-for-Kingston-and-Co.patch
deleted file mode 100644
index 561dfaf..0000000
--- a/resources/libreboot/patch/kgpe-d16/0003-arch-x86-boot-smbios-Add-SPD-IDs-for-Kingston-and-Co.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From f612a5cc0afba6e1af60652283dd47f3f34dcca7 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Thu, 25 Jun 2015 18:37:58 -0500
-Subject: [PATCH 003/146] arch/x86/boot/smbios: Add SPD IDs for Kingston and
- Corsair
-
----
- src/arch/x86/smbios.c |    8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
-index a1f05da..74288f9 100644
---- a/src/arch/x86/smbios.c
-+++ b/src/arch/x86/smbios.c
-@@ -124,10 +124,18 @@ static int smbios_processor_name(char *start)
- void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t)
- {
- 	switch (mod_id) {
-+		case 0x9801:
-+			t->manufacturer = smbios_add_string(t->eos,
-+							    "Kingston");
-+			break;
- 		case 0x987f:
- 			t->manufacturer = smbios_add_string(t->eos,
- 							    "Hynix");
- 			break;
-+		case 0x9e02:
-+			t->manufacturer = smbios_add_string(t->eos,
-+							    "Corsair");
-+			break;
- 		case 0xad80:
- 			t->manufacturer = smbios_add_string(t->eos,
- 							    "Hynix/Hyundai");
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch b/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch
new file mode 100644
index 0000000..b984f28
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch
@@ -0,0 +1,62 @@
+From 3e2be2d88101331eedb59c1459630b553c7cb660 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sat, 17 Oct 2015 04:37:10 -0500
+Subject: [PATCH 003/139] drivers/i2c/w83795: Add option to use auxiliary SMBUS
+ controller
+
+Change-Id: I5a9b5eba992853b84b0cb6c3a1764edf42ac49b2
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/drivers/i2c/w83795/chip.h   |  4 ++++
+ src/drivers/i2c/w83795/w83795.c | 14 ++++++++++++++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h
+index effe119..413ea87 100644
+--- a/src/drivers/i2c/w83795/chip.h
++++ b/src/drivers/i2c/w83795/chip.h
+@@ -139,4 +139,8 @@ struct drivers_i2c_w83795_config {
+ 	uint8_t fan6_duty;			/* % of full speed (0-100) */
+ 	uint8_t fan7_duty;			/* % of full speed (0-100) */
+ 	uint8_t fan8_duty;			/* % of full speed (0-100) */
++
++	uint8_t smbus_aux;			/* 0 == device located on first SMBUS,
++						 * 1 == device located on auxiliary SMBUS
++						 */
+ };
+diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c
+index cf0cf2f..453e0af 100644
+--- a/src/drivers/i2c/w83795/w83795.c
++++ b/src/drivers/i2c/w83795/w83795.c
+@@ -141,7 +141,16 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src)
+ 	uint8_t val;
+ 	uint16_t limit_value;
+ 
++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX)
++	uint8_t smbus_aux_prev = smbus_switched_to_aux();
++	smbus_switch_to_aux(config->smbus_aux);
++#endif
++
+ 	if (smbus_read_byte(dev, 0x00) < 0) {
++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX)
++		/* Restore SMBUS channel setting */
++		smbus_switch_to_aux(smbus_aux_prev);
++#endif
+ 		printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n");
+ 		return;
+ 	}
+@@ -325,6 +334,11 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src)
+ 	val = w83795_read(dev, W83795_REG_CONFIG);
+ 	val |= W83795_REG_CONFIG_START;
+ 	w83795_write(dev, W83795_REG_CONFIG, val);
++
++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX)
++	/* Restore SMBUS channel setting */
++	smbus_switch_to_aux(smbus_aux_prev);
++#endif
+ }
+ 
+ static void w83795_hwm_init(struct device *dev)
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0004-arch-x86-smbios-Add-Crucial-DIMM-manufacturer-ID.patch b/resources/libreboot/patch/kgpe-d16/0004-arch-x86-smbios-Add-Crucial-DIMM-manufacturer-ID.patch
deleted file mode 100644
index 4dd4068..0000000
--- a/resources/libreboot/patch/kgpe-d16/0004-arch-x86-smbios-Add-Crucial-DIMM-manufacturer-ID.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 4daf71b080abe86e2fe61af3adbc57a710b7ea02 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Tue, 28 Jul 2015 09:22:59 -0500
-Subject: [PATCH 004/146] arch/x86/smbios: Add Crucial DIMM manufacturer ID
-
----
- src/arch/x86/smbios.c |    4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
-index 74288f9..6d645a3 100644
---- a/src/arch/x86/smbios.c
-+++ b/src/arch/x86/smbios.c
-@@ -124,6 +124,10 @@ static int smbios_processor_name(char *start)
- void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t)
- {
- 	switch (mod_id) {
-+		case 0x2c80:
-+			t->manufacturer = smbios_add_string(t->eos,
-+							    "Crucial");
-+			break;
- 		case 0x9801:
- 			t->manufacturer = smbios_add_string(t->eos,
- 							    "Kingston");
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0007-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch b/resources/libreboot/patch/kgpe-d16/0004-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch
index 4f1751d..3d9c5c8 100644
--- a/resources/libreboot/patch/kgpe-d16/0007-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0004-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch
@@ -1,9 +1,11 @@
-From 27f2cdc381f7bac82f868acef86bcc95467fe24c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 7075bbddd264958b80ea4831b602b6fbfaf60b0d Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 17:38:09 -0500
-Subject: [PATCH 007/146] drivers/aspeed: Add native text mode VGA support for
+Subject: [PATCH 004/139] drivers/aspeed: Add native text mode VGA support for
  the AST2050
 
+Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
  src/drivers/aspeed/Kconfig                  |    2 +
  src/drivers/aspeed/Makefile.inc             |    1 +
@@ -83,7 +85,7 @@ index 0000000..3ba9dde
 \ No newline at end of file
 diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c
 new file mode 100644
-index 0000000..cc090bb
+index 0000000..809e9de
 --- /dev/null
 +++ b/src/drivers/aspeed/ast2050/ast2050.c
 @@ -0,0 +1,83 @@
@@ -152,7 +154,7 @@ index 0000000..cc090bb
 +	vga_io_init();
 +	vga_textmode_init();
 +	printk(BIOS_INFO, "ASpeed VGA text mode initialized\n");
-+	
++
 +	/* if we don't have console, at least print something... */
 +	vga_line_write(0, "ASpeed VGA text mode initialized");
 +}
@@ -3669,5 +3671,5 @@ index dcb8a42..fcaf4aa 100644
  #define PCI_DEVICE_ID_SYMPHONY_101	0x0001
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0008-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch b/resources/libreboot/patch/kgpe-d16/0005-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch
index 6792c6d..a895479 100644
--- a/resources/libreboot/patch/kgpe-d16/0008-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch
+++ b/resources/libreboot/patch/kgpe-d16/0005-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch
@@ -1,27 +1,28 @@
-From bdcf5ce540eb621d31655a172eb43ddf86d4cea0 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From e897086a84f3b7c1af321e2a8a303cc49367b390 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 17:46:15 -0500
-Subject: [PATCH 008/146] southbridge/amd/sb700: Fix boot hang on ASUS
- KGPE-D16
+Subject: [PATCH 005/139] southbridge/amd/sb700: Fix boot hang on ASUS KGPE-D16
 
+Change-Id: I1d7d6715663a13ab94fd6d71808e35f0f7384d00
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/Kconfig       |    4 +
- src/southbridge/amd/sb700/acpi/ide.asl  |  234 +++++++++++++++++++++++++++++++
- src/southbridge/amd/sb700/acpi/sata.asl |  133 ++++++++++++++++++
- src/southbridge/amd/sb700/bootblock.c   |   46 +++++-
- src/southbridge/amd/sb700/early_setup.c |   18 +++
- src/southbridge/amd/sb700/lpc.c         |    3 +
- src/southbridge/amd/sb700/sm.c          |   21 +--
- src/southbridge/amd/sb700/smbus.h       |    5 +-
+ src/southbridge/amd/sb700/Kconfig       |   4 +
+ src/southbridge/amd/sb700/acpi/ide.asl  | 234 ++++++++++++++++++++++++++++++++
+ src/southbridge/amd/sb700/acpi/sata.asl | 133 ++++++++++++++++++
+ src/southbridge/amd/sb700/bootblock.c   |  46 ++++++-
+ src/southbridge/amd/sb700/early_setup.c |  18 +++
+ src/southbridge/amd/sb700/lpc.c         |   3 +
+ src/southbridge/amd/sb700/sm.c          |  21 +--
+ src/southbridge/amd/sb700/smbus.h       |   5 +-
  8 files changed, 447 insertions(+), 17 deletions(-)
  create mode 100644 src/southbridge/amd/sb700/acpi/ide.asl
  create mode 100644 src/southbridge/amd/sb700/acpi/sata.asl
 
 diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
-index 42ca2bb..064f32e 100644
+index a5dfe07..f56f84a 100644
 --- a/src/southbridge/amd/sb700/Kconfig
 +++ b/src/southbridge/amd/sb700/Kconfig
-@@ -41,6 +41,10 @@ config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
+@@ -42,6 +42,10 @@ config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
  	bool
  	default n
  
@@ -34,14 +35,14 @@ index 42ca2bb..064f32e 100644
  	default 0xfef00000
 diff --git a/src/southbridge/amd/sb700/acpi/ide.asl b/src/southbridge/amd/sb700/acpi/ide.asl
 new file mode 100644
-index 0000000..fa89d18
+index 0000000..9b5e3ea
 --- /dev/null
 +++ b/src/southbridge/amd/sb700/acpi/ide.asl
 @@ -0,0 +1,234 @@
 +/*
 + * This file is part of the coreboot project.
 + *
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering 
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
 + * Copyright (C) 2010 Advanced Micro Devices, Inc.
 + *
 + * This program is free software; you can redistribute it and/or modify
@@ -554,7 +555,7 @@ index a39ec18..0cc1e8b 100644
  	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
  	dword = pci_read_config32(sm_dev, 0x64);
 diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
-index f544c88..3e6ddf1 100644
+index c216e1f..a4b78d0 100644
 --- a/src/southbridge/amd/sb700/sm.c
 +++ b/src/southbridge/amd/sb700/sm.c
 @@ -2,6 +2,7 @@
@@ -565,7 +566,7 @@ index f544c88..3e6ddf1 100644
   *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License as published by
-@@ -57,11 +58,8 @@ static void sm_init(device_t dev)
+@@ -59,11 +60,8 @@ static void sm_init(device_t dev)
  	printk(BIOS_INFO, "sm_init().\n");
  
  	rev = get_sb700_revision(dev);
@@ -579,7 +580,7 @@ index f544c88..3e6ddf1 100644
  
  	/* 2.10 Interrupt Routing/Filtering */
  	dword = pci_read_config8(dev, 0x62);
-@@ -127,9 +125,10 @@ static void sm_init(device_t dev)
+@@ -129,9 +127,10 @@ static void sm_init(device_t dev)
  	get_option(&on, "power_on_after_fail");
  	byte = pm_ioread(0x74);
  	byte &= ~0x03;
@@ -593,7 +594,7 @@ index f544c88..3e6ddf1 100644
  	byte |= 1 << 2;
  	pm_iowrite(0x74, byte);
  	printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
-@@ -293,6 +292,10 @@ static void sm_init(device_t dev)
+@@ -295,6 +294,10 @@ static void sm_init(device_t dev)
  	byte &= ~(1 << 1);
  	pm_iowrite(0x59, byte);
  
@@ -604,7 +605,7 @@ index f544c88..3e6ddf1 100644
  	printk(BIOS_INFO, "sm_init() end\n");
  
  	/* Enable NbSb virtual channel */
-@@ -371,7 +374,7 @@ static void sb700_sm_read_resources(device_t dev)
+@@ -385,7 +388,7 @@ static void sb700_sm_read_resources(device_t dev)
  	struct resource *res;
  
  	/* Get the normal pci resources of this device */
@@ -637,5 +638,5 @@ index d223fe7..34b4098 100644
  #define SMBHSTSTAT 0x0
  #define SMBSLVSTAT 0x1
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0005-southbridge-amd-sr5650-Remove-unnecessary-register-c.patch b/resources/libreboot/patch/kgpe-d16/0005-southbridge-amd-sr5650-Remove-unnecessary-register-c.patch
deleted file mode 100644
index b7a888e..0000000
--- a/resources/libreboot/patch/kgpe-d16/0005-southbridge-amd-sr5650-Remove-unnecessary-register-c.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 0d0290e3866dd24c77de9114937b692bba0e9db9 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Sun, 2 Aug 2015 21:29:20 -0500
-Subject: [PATCH 005/146] southbridge/amd/sr5650: Remove unnecessary register
- configuration
-
----
- src/southbridge/amd/sr5650/early_setup.c |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
-index d91f3bd..ec555f8 100644
---- a/src/southbridge/amd/sr5650/early_setup.c
-+++ b/src/southbridge/amd/sr5650/early_setup.c
-@@ -1,6 +1,7 @@
- /*
-  * This file is part of the coreboot project.
-  *
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-  * Copyright (C) 2010 Advanced Micro Devices, Inc.
-  *
-  * This program is free software; you can redistribute it and/or modify
-@@ -437,7 +438,6 @@ static void sr5650_por_htiu_index_init(device_t nb_dev)
- 	set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2,  0x1<<2);
- 	set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4,  0x1<<4);
- 
--	set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 0 << 21);
- 	axindxc_reg(0x10, 1 << 9, 1 << 9);
- 	set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9);
- 	set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26);
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0009-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch b/resources/libreboot/patch/kgpe-d16/0006-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch
index 3cffccc..a0273e2 100644
--- a/resources/libreboot/patch/kgpe-d16/0009-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch
+++ b/resources/libreboot/patch/kgpe-d16/0006-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch
@@ -1,15 +1,17 @@
-From dd732a07e6aec5386eea9a00845f62c5b8b6ae68 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 03ff36542c8f8260b2ff7db5f41a16e9299a1bd0 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 17:46:38 -0500
-Subject: [PATCH 009/146] southbridge/amd/sr5650: Fix boot failure on ASUS
+Subject: [PATCH 006/139] southbridge/amd/sr5650: Fix boot failure on ASUS
  KGPE-D16
 
+Change-Id: Ia13ba58118a826e830a4dc6e2378b76110fcabad
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sr5650/acpi/sr5650.asl |  388 ++++++++++++++++++++++++++++
- src/southbridge/amd/sr5650/early_setup.c   |    7 +-
- src/southbridge/amd/sr5650/ht.c            |    3 +-
- src/southbridge/amd/sr5650/pcie.c          |   37 ++-
- src/southbridge/amd/sr5650/sr5650.c        |   51 ++--
+ src/southbridge/amd/sr5650/acpi/sr5650.asl | 388 +++++++++++++++++++++++++++++
+ src/southbridge/amd/sr5650/early_setup.c   |   7 +-
+ src/southbridge/amd/sr5650/ht.c            |   3 +-
+ src/southbridge/amd/sr5650/pcie.c          |  37 ++-
+ src/southbridge/amd/sr5650/sr5650.c        |  51 ++--
  5 files changed, 456 insertions(+), 30 deletions(-)
  create mode 100644 src/southbridge/amd/sr5650/acpi/sr5650.asl
 
@@ -615,5 +617,5 @@ index 441be66..75383de 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0010-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch b/resources/libreboot/patch/kgpe-d16/0007-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch
index dadfa5a..017295e 100644
--- a/resources/libreboot/patch/kgpe-d16/0010-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch
+++ b/resources/libreboot/patch/kgpe-d16/0007-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch
@@ -1,27 +1,31 @@
-From a7e9e5b7d4f3699e043574b2ad5d13ff65125fce Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 1c4603c0b0003dc41519ed8e03782ff6e1f9222f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 17:50:29 -0500
-Subject: [PATCH 010/146] cpu/amd: Add initial support for AMD Socket G34
+Subject: [PATCH 007/139] cpu/amd: Add initial support for AMD Socket G34
  processors
 
+Change-Id: Iccd034f32c26513edd52ca3a11a30f61c362682d
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/Kconfig                        |    1 +
- src/cpu/amd/Makefile.inc                   |    1 +
- src/cpu/amd/car/post_cache_as_ram.c        |   19 ++++-
- src/cpu/amd/model_10xxx/init_cpus.c        |   34 ++++++++-
- src/cpu/amd/model_10xxx/model_10xxx_init.c |    2 +
- src/cpu/amd/model_10xxx/processor_name.c   |   23 ++++++
- src/cpu/amd/model_10xxx/ram_calc.c         |    2 +
- src/cpu/amd/quadcore/quadcore_id.c         |   77 +++++++++++++++-----
- src/cpu/amd/socket_G34/Kconfig             |   29 ++++++++
- src/cpu/amd/socket_G34/Makefile.inc        |   14 ++++
- src/cpu/amd/socket_G34/socket_G34.c        |   25 +++++++
- src/northbridge/amd/amdfam10/northbridge.c |  102 ++++++++++++++++++++++-----
- src/northbridge/amd/amdht/ht_wrapper.c     |  105 +++++++++++++++++++++++++++-
- 13 files changed, 390 insertions(+), 44 deletions(-)
+ src/cpu/amd/Kconfig                        |   1 +
+ src/cpu/amd/Makefile.inc                   |   1 +
+ src/cpu/amd/car/post_cache_as_ram.c        |  19 ++++-
+ src/cpu/amd/model_10xxx/init_cpus.c        |  34 ++++++++-
+ src/cpu/amd/model_10xxx/model_10xxx_init.c |   2 +
+ src/cpu/amd/model_10xxx/processor_name.c   |  23 +++++++
+ src/cpu/amd/model_10xxx/ram_calc.c         |   2 +
+ src/cpu/amd/quadcore/quadcore_id.c         |  77 ++++++++++++++++-----
+ src/cpu/amd/socket_G34/Kconfig             |  29 ++++++++
+ src/cpu/amd/socket_G34/Makefile.inc        |  14 ++++
+ src/cpu/amd/socket_G34/socket_G34.c        |  25 +++++++
+ src/northbridge/amd/amdfam10/northbridge.c | 102 ++++++++++++++++++++++-----
+ src/northbridge/amd/amdht/ht_wrapper.c     | 107 ++++++++++++++++++++++++++++-
+ src/northbridge/amd/amdht/ht_wrapper.h     |  25 +++++++
+ 14 files changed, 417 insertions(+), 44 deletions(-)
  create mode 100644 src/cpu/amd/socket_G34/Kconfig
  create mode 100644 src/cpu/amd/socket_G34/Makefile.inc
  create mode 100644 src/cpu/amd/socket_G34/socket_G34.c
+ create mode 100644 src/northbridge/amd/amdht/ht_wrapper.h
 
 diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
 index 8286b2a..3a02043 100644
@@ -247,7 +251,7 @@ index c8637c9..46ccdbd 100644
  }
 +#endif
 diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
-index cf45196..778e96f 100644
+index cf45196..c5921de 100644
 --- a/src/cpu/amd/quadcore/quadcore_id.c
 +++ b/src/cpu/amd/quadcore/quadcore_id.c
 @@ -1,6 +1,7 @@
@@ -333,7 +337,7 @@ index cf45196..778e96f 100644
 +		}
  	}
 +
-+	if (rev_gte_d) {
++	if (rev_gte_d && dual_node) {
 +		/* Coreboot expects each separate processor die to be on a different nodeid.
 +		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
 +		 */
@@ -436,7 +440,7 @@ index 0000000..90f7b8c
 +	CHIP_NAME("socket G34")
 +};
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index 6d91cbd..7bd8675 100644
+index 6d91cbd..74cecc8 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
 @@ -187,6 +187,43 @@ static void ht_route_link(struct bus *link, scan_state mode)
@@ -449,18 +453,18 @@ index 6d91cbd..7bd8675 100644
 +	uint8_t rev_gte_d = 0;
 +	uint8_t dual_node = 0;
 +	uint32_t f3xe8;
-+	
++
 +	if (cpuid_eax(0x80000001) >= 0x8)
 +		/* Revision D or later */
 +		rev_gte_d = 1;
-+	
++
 +	if (rev_gte_d) {
 +		f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
-+	
++
 +		/* Check for dual node capability */
 +		if (f3xe8 & 0x20000000)
 +			dual_node = 1;
-+	
++
 +		if (dual_node) {
 +			/* Each G34 processor contains a defective HT link.
 +			* See the BKDG Rev 3.62 section 2.7.1.5 for details.
@@ -590,11 +594,11 @@ index 6d91cbd..7bd8675 100644
  			add_more_links(cdb_dev, 4);
  
 +		f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
-+	
++
 +		if (cpuid_eax(0x80000001) >= 0x8)
 +			/* Revision D or later */
 +			rev_gte_d = 1;
-+	
++
 +		if (rev_gte_d)
 +			/* Check for dual node capability */
 +			if (f3xe8 & 0x20000000)
@@ -655,10 +659,19 @@ index 6d91cbd..7bd8675 100644
  	}
  }
 diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
-index 36fe60b..bafda10 100644
+index 36fe60b..389b1b1 100644
 --- a/src/northbridge/amd/amdht/ht_wrapper.c
 +++ b/src/northbridge/amd/amdht/ht_wrapper.c
-@@ -113,6 +113,20 @@ void getAmdTopolist(u8 ***p)
+@@ -22,6 +22,8 @@
+ #include <console/console.h>
+ #include <northbridge/amd/amdfam10/amdfam10.h>
+ 
++#include "ht_wrapper.h"
++
+ /*----------------------------------------------------------------------------
+  *			TYPEDEFS, DEFINITIONS AND MACROS
+  *
+@@ -113,6 +115,20 @@ void getAmdTopolist(u8 ***p)
  	*p = (u8 **)amd_topo_list;
  }
  
@@ -679,7 +692,7 @@ index 36fe60b..bafda10 100644
  
  /**
   * void amd_ht_init(struct sys_info *sysinfo)
-@@ -128,7 +142,7 @@ static void amd_ht_init(struct sys_info *sysinfo)
+@@ -128,7 +144,7 @@ static void amd_ht_init(struct sys_info *sysinfo)
  		0,	// u8 AutoBusStart;
  		32,	// u8 AutoBusMax;
  		6,	// u8 AutoBusIncrement;
@@ -688,7 +701,7 @@ index 36fe60b..bafda10 100644
  		NULL,	// BOOL (*AMD_CB_OverrideBusNumbers)();
  		AMD_CB_ManualBUIDSwapList,	// BOOL (*AMD_CB_ManualBUIDSwapList)();
  		NULL,	// void (*AMD_CB_DeviceCapOverride)();
-@@ -146,6 +160,93 @@ static void amd_ht_init(struct sys_info *sysinfo)
+@@ -146,6 +162,93 @@ static void amd_ht_init(struct sys_info *sysinfo)
  	printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
  	amdHtInitialize(&ht_wrapper);
  	printk(BIOS_DEBUG, "Exit amd_ht_init()\n");
@@ -701,7 +714,7 @@ index 36fe60b..bafda10 100644
 + *  AMD HT fixup
 + *
 + */
-+static void amd_ht_fixup(struct sys_info *sysinfo) {
++void amd_ht_fixup(struct sys_info *sysinfo) {
 +	printk(BIOS_DEBUG, "amd_ht_fixup()\n");
 +	if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) {
 +		uint8_t rev_gte_d = 0;
@@ -783,6 +796,37 @@ index 36fe60b..bafda10 100644
 +		}
 +	}
  }
+diff --git a/src/northbridge/amd/amdht/ht_wrapper.h b/src/northbridge/amd/amdht/ht_wrapper.h
+new file mode 100644
+index 0000000..3e9d957
+--- /dev/null
++++ b/src/northbridge/amd/amdht/ht_wrapper.h
+@@ -0,0 +1,25 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#ifndef AMD_HT_WRAPPER_H
++#define AMD_HT_WRAPPER_H
++
++void amd_ht_fixup(struct sys_info *sysinfo);
++
++#endif
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch b/resources/libreboot/patch/kgpe-d16/0008-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch
index ec822df..75367b6 100644
--- a/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch
+++ b/resources/libreboot/patch/kgpe-d16/0008-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch
@@ -1,30 +1,52 @@
-From 791a6ea672f16f971422f10514bb0c4225930489 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 2f8bf745a7ffc2e031efa0f60f993b88baf5a714 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 17:55:58 -0500
-Subject: [PATCH 011/146] northbridge/amd/amdmct: Fix broken AMD K10 DDR3
+Subject: [PATCH 008/139] northbridge/amd/amdmct: Fix broken AMD K10 DDR3
  memory initalization
 
+Change-Id: Iab690db769e820600693ad1170085623b177b94e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct/mct_d.c          |    1 -
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c     |  177 ++++-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h     |    8 +-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h |   87 +--
- src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c  |    6 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c  |  806 ++++++++++++-----------
- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c    |    6 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c  |   14 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c  |    3 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c   |   19 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c    |    5 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c    |  803 +++++++++++-----------
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c  |   18 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c  |   13 +-
- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c   |    7 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c     |   42 +-
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c   |  267 ++++----
- src/northbridge/amd/amdmct/wrappers/mcti_d.c    |  114 +---
- 18 files changed, 1254 insertions(+), 1142 deletions(-)
+ src/northbridge/amd/amdfam10/raminit_amdmct.c   |   2 +
+ src/northbridge/amd/amdmct/mct/mct_d.c          |   1 -
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c     | 177 +++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h     |   8 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h |  87 +--
+ src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c  |   6 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c  | 806 +++++++++++++-----------
+ src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c    |   6 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c  |  14 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c  |   3 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctproc.c   |  19 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c    |   5 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c    | 800 ++++++++++++-----------
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c  |  18 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c  |  13 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c   |   7 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c     |  42 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c   | 267 ++++----
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c    | 112 +---
+ 19 files changed, 1253 insertions(+), 1140 deletions(-)
 
+diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
+index a0d47f4..a585fae 100644
+--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
++++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
+@@ -28,12 +28,14 @@ static  void print_tx(const char *strval, u32 val)
+ }
+ #endif
+ 
++#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
+ static  void print_t(const char *strval)
+ {
+ #if CONFIG_DEBUG_RAM_SETUP
+ 	printk(BIOS_DEBUG, "%s", strval);
+ #endif
+ }
++#endif
+ 
+ static  void print_tf(const char *func, const char *strval)
+ {
 diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
 index 3dec934..88910e2 100644
 --- a/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -544,7 +566,7 @@ index ae1654c..99a2628 100644
  			*AddrTmgCTL = 0x00000000;
  			if (MAAdimms == 3)
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 404727b..8572243 100644
+index 404727b..cc2f43a 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -2,6 +2,7 @@
@@ -1071,7 +1093,7 @@ index 404727b..8572243 100644
 +						pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane];
 +					} else {
 +						print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 123 Unable to find write passing region for lane ", lane, 2);
-+	
++
 +						/* Flag absence of passing window */
 +						Errors |= 1 << SB_NODQSPOS;
 +					}
@@ -1668,7 +1690,7 @@ index 6de2f4e..b21b96a 100644
  	/* program MrsAddress[12]=0 (PPD):slow exit */
  	if (dword & (1 << 23))
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index 8e5c268..587c414 100644
+index 8e5c268..91e8f77 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 @@ -2,6 +2,7 @@
@@ -1957,7 +1979,7 @@ index 8e5c268..587c414 100644
  				continue;
  			}
  
-@@ -229,171 +370,215 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
+@@ -229,171 +370,214 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
  			print_debug_dqs("\t\tTrainRcvEn53: TestAddr1 ", TestAddr1, 2);
  			print_debug_dqs("\t\tTrainRcvEn53: TestAddr1B ", TestAddr1B, 2);
  
@@ -2139,7 +2161,6 @@ index 8e5c268..587c414 100644
 +						print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", 0x55, "  |  ", result_lane_byte1, 4);
 +						print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", 0xaa, "  |  ", result_lane_byte2, 4);
 +#endif
-+						
  					}
  				}
  
@@ -2259,24 +2280,19 @@ index 8e5c268..587c414 100644
 -
 -			/* CHB_D0_B0_RCVRDLY set in mct_Average_RcvrEnDly_Pass */
 -			mct_Average_RcvrEnDly_Pass(pDCTstat, RcvrEnDly, RcvrEnDlyLimit, Channel, Receiver, Pass);
--
--			mct_SetFinalRcvrEnDly_D(pDCTstat, RcvrEnDly, Final_Value, Channel, Receiver, dev, index_reg, Addl_Index, Pass);
 +#if DQS_TRAIN_DEBUG > 0
 +			for (lane = 0; lane < 8; lane++)
 +				print_debug_dqs_pair("\t\tTrainRcvEn55: Lane ", lane, " current_total_delay ", current_total_delay[lane], 2);
 +#endif
  
--			if(pDCTstat->ErrStatus & (1 << SB_SmallRCVR)) {
--				Errors |= 1 << SB_SmallRCVR;
--			}
+-			mct_SetFinalRcvrEnDly_D(pDCTstat, RcvrEnDly, Final_Value, Channel, Receiver, dev, index_reg, Addl_Index, Pass);
 +			/* Find highest delay value and save for later use */
 +			for (lane = 0; lane < 8; lane++)
 +				if (current_total_delay[lane] > CTLRMaxDelay)
 +					CTLRMaxDelay = current_total_delay[lane];
  
--			RcvrEnDly += Pass1MemClkDly;
--			if(RcvrEnDly > CTLRMaxDelay) {
--				CTLRMaxDelay = RcvrEnDly;
+-			if(pDCTstat->ErrStatus & (1 << SB_SmallRCVR)) {
+-				Errors |= 1 << SB_SmallRCVR;
 +			/* See if any lanes failed training, and set error flags appropriately
 +			 * For all trained lanes, save delay values for later use
 +			 */
@@ -2295,12 +2311,16 @@ index 8e5c268..587c414 100644
 +				}
  			}
  
--		}	/* while Receiver */
+-			RcvrEnDly += Pass1MemClkDly;
+-			if(RcvrEnDly > CTLRMaxDelay) {
+-				CTLRMaxDelay = RcvrEnDly;
+-			}
 +			/* 2.8.9.9.2 (8)
 +			 * Flush the receiver FIFO
 +			 * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO
 +			 */
-+			
+ 
+-		}	/* while Receiver */
 +			WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1);
 +			mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0);
 +		}
@@ -2310,7 +2330,7 @@ index 8e5c268..587c414 100644
  
  	CTLRMaxDelay = MaxDelay_CH[0];
  	if (MaxDelay_CH[1] > CTLRMaxDelay)
-@@ -428,31 +613,31 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
+@@ -428,31 +612,31 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
  
  #if DQS_TRAIN_DEBUG > 0
  	{
@@ -2355,7 +2375,7 @@ index 8e5c268..587c414 100644
  				}
  				printk(BIOS_DEBUG, "\n");
  			}
-@@ -475,15 +660,6 @@ u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct)
+@@ -475,15 +659,6 @@ u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct)
  	}
  }
  
@@ -2371,7 +2391,7 @@ index 8e5c268..587c414 100644
  static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat)
  {
  	u8 ch_end, ch;
-@@ -514,17 +690,20 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat)
+@@ -514,17 +689,20 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat)
   * Function only used once so it was inlined.
   */
  
@@ -2396,7 +2416,7 @@ index 8e5c268..587c414 100644
  		pDCTstat->Status |= 1 << SB_DQSRcvLimit;
  	}
  
-@@ -543,27 +722,57 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly,
+@@ -543,27 +721,57 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly,
  		val = Get_NB32_index_wait(dev, index_reg, index);
  		if(i & 1) {
  			/* odd byte lane */
@@ -2461,7 +2481,7 @@ index 8e5c268..587c414 100644
  
  	if(pDCTstat->GangedMode)
  		Channel = 0;
-@@ -598,49 +807,32 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ
+@@ -598,49 +806,32 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ
  	val = Get_NB32(dev, 0x78 + reg_off);
  	SubTotal += 8 - (val & 0x0f);
  
@@ -2522,7 +2542,7 @@ index 8e5c268..587c414 100644
  
  	pDCTstat->CH_MaxRdLat[Channel] = SubTotal;
  	if(pDCTstat->GangedMode) {
-@@ -659,143 +851,6 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ
+@@ -659,143 +850,6 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ
  	Set_NB32(dev, reg, val);
  }
  
@@ -2666,7 +2686,7 @@ index 8e5c268..587c414 100644
  static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat)
  {
-@@ -854,7 +909,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel)
+@@ -854,7 +908,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel)
  	u32 index_reg;
  	u32 index;
  	u8 ChipSel;
@@ -2675,7 +2695,7 @@ index 8e5c268..587c414 100644
  	u32 val;
  
  	dev = pDCTstat->dev_dct;
-@@ -884,7 +939,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -884,7 +938,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
  
  	for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) {
  		if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) {
@@ -2684,7 +2704,7 @@ index 8e5c268..587c414 100644
  			p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1];
  
  			/* DQS Delay Value of Data Bytelane
-@@ -920,6 +975,10 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -920,6 +974,10 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
  	SetEccDQSRcvrEn_D(pDCTstat, Channel);
  }
  
@@ -2695,7 +2715,7 @@ index 8e5c268..587c414 100644
  void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
  			struct DCTStatStruc *pDCTstatA)
  {
-@@ -1017,7 +1076,9 @@ static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat,
+@@ -1017,7 +1075,9 @@ static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat,
  		avRecValue -= 3;
  	else
  	*/
@@ -3281,7 +3301,7 @@ index 212a348..c76476b 100644
  	}
  
 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
-index ea32893..47260f2 100644
+index ea32893..6465e13 100644
 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 @@ -49,7 +49,7 @@ static const uint16_t ddr3_limits[4] = {800, 666, 533, 400};
@@ -3313,7 +3333,7 @@ index ea32893..47260f2 100644
  	int i;
  	for (i = 0; i < 15; i = i + 2) {
  		if (pDCTstat->DIMMValid & (1 << i))
-@@ -304,13 +310,19 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
+@@ -304,6 +310,12 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
  		if (pDCTstat->DIMMValid & (1 << (i + 1)))
  			ch2_count++;
  	}
@@ -3326,14 +3346,6 @@ index ea32893..47260f2 100644
  	if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) {
  		printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count);
  		printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count);
- 	}
- 
- 	/* Set limits if needed */
--	pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), pDCTstat->PresetmaxFreq);
-+	pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), (ch1_registered || ch2_registered), pDCTstat->PresetmaxFreq);
- }
- 
- #ifdef UNUSED_CODE
 @@ -413,101 +425,6 @@ static void mctHookAfterDramInit(void)
  }
  
@@ -3447,5 +3459,5 @@ index ea32893..47260f2 100644
  		vErratum414(pDCTstatA);
  	}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0012-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch b/resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch
index 7e62ea3..877d6b0 100644
--- a/resources/libreboot/patch/kgpe-d16/0012-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch
+++ b/resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch
@@ -1,11 +1,13 @@
-From 7192af06922df114da15077d51e8882d3d10f101 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 008cfb1a5e464a79af252b34086b1eb28d8b3420 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 8 Sep 2015 16:08:45 -0500
-Subject: [PATCH 012/146] northbridge/amd/amdmct/mct_ddr3: Fix curly brace
+Subject: [PATCH 009/139] northbridge/amd/amdmct/mct_ddr3: Fix curly brace
  style violations
 
+Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c |   37 +++++++------------------
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 37 ++++++++-------------------
  1 file changed, 10 insertions(+), 27 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -89,5 +91,5 @@ index c76476b..9f42d54 100644
  		 * We will then round the negative number to 0.
  		 */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0013-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch b/resources/libreboot/patch/kgpe-d16/0010-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch
index 0d507c7..d5a8941 100644
--- a/resources/libreboot/patch/kgpe-d16/0013-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0010-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch
@@ -1,32 +1,21 @@
-From 818a658a290203625a65df4dde4901ea66fd72c8 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5e830015eefae9024835e76c81715821a55b0853 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:00:27 -0500
-Subject: [PATCH 013/146] northbridge/amd/amdfam10: Limit maximum RAM clock to
+Subject: [PATCH 010/139] northbridge/amd/amdfam10: Limit maximum RAM clock to
  BKDG recommendations
 
+Change-Id: I45eb03a4b351e458e8448245896743bd6fa57637
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/raminit_amdmct.c |   53 +++++++++++++++++++------
- 1 file changed, 40 insertions(+), 13 deletions(-)
+ src/northbridge/amd/amdfam10/raminit_amdmct.c | 46 +++++++++++++++++++++++----
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c  |  2 +-
+ 2 files changed, 41 insertions(+), 7 deletions(-)
 
 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-index a0d47f4..fa14e4f 100644
+index a585fae..3f33eba 100644
 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
 +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-@@ -28,13 +28,6 @@ static  void print_tx(const char *strval, u32 val)
- }
- #endif
- 
--static  void print_t(const char *strval)
--{
--#if CONFIG_DEBUG_RAM_SETUP
--	printk(BIOS_DEBUG, "%s", strval);
--#endif
--}
--
- static  void print_tf(const char *func, const char *strval)
- {
- #if CONFIG_DEBUG_RAM_SETUP
-@@ -42,30 +35,59 @@ static  void print_tf(const char *func, const char *strval)
+@@ -44,29 +44,58 @@ static  void print_tf(const char *func, const char *strval)
  #endif
  }
  
@@ -56,9 +45,9 @@ index a0d47f4..fa14e4f 100644
  					freq = 400;
 -					print_tf(__func__, ": More than 1 DIMM on channel; limiting to DDR2-800\n");
 +					print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n");
- 				}
- 			}
- 		}
++				}
++			}
++		}
 +	} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
 +		if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
 +			/* K10 BKDG Rev. 3.62 Table 34 */
@@ -79,8 +68,8 @@ index a0d47f4..fa14e4f 100644
 +				if (freq > 666) {
 +					freq = 666;
 +					print_tf(__func__, ": 1 registered DIMM on channel; limiting to DDR3-1333\n");
-+				}
-+			}
+ 				}
+ 			}
 +		} else {
 +			/* K10 BKDG Rev. 3.62 Table 33 */
 +			/* Limit to DDR3-1333 */
@@ -88,11 +77,10 @@ index a0d47f4..fa14e4f 100644
 +				freq = 666;
 +				print_tf(__func__, ": unbuffered DIMMs on channel; limiting to DDR3-1333\n");
 +			}
-+		}
+ 		}
  	}
  
- 	return freq;
-@@ -118,6 +140,9 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
+@@ -120,6 +149,9 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
  //C32
  #elif CONFIG_CPU_SOCKET_TYPE == 0x14
  #include "../amdmct/mct_ddr3/mctardk5.c"
@@ -102,7 +90,7 @@ index a0d47f4..fa14e4f 100644
  #endif
  
  #else  /* DDR2 */
-@@ -205,6 +230,7 @@ static void raminit_amdmct(struct sys_info *sysinfo)
+@@ -207,6 +239,7 @@ static void raminit_amdmct(struct sys_info *sysinfo)
  	printk(BIOS_DEBUG, "raminit_amdmct end:\n");
  }
  
@@ -110,11 +98,24 @@ index a0d47f4..fa14e4f 100644
  static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
  {
  	if (!sysinfo)
-@@ -243,3 +269,4 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
+@@ -245,3 +278,4 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
  	}
  #endif
  }
 +#endif
+diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+index 6465e13..47260f2 100644
+--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
++++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+@@ -322,7 +322,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
+ 	}
+ 
+ 	/* Set limits if needed */
+-	pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), pDCTstat->PresetmaxFreq);
++	pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), (ch1_registered || ch2_registered), pDCTstat->PresetmaxFreq);
+ }
+ 
+ #ifdef UNUSED_CODE
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdfam10-Fix-typo-in-comment.patch b/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdfam10-Fix-typo-in-comment.patch
new file mode 100644
index 0000000..e28528b
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdfam10-Fix-typo-in-comment.patch
@@ -0,0 +1,27 @@
+From 72842e77d6207be18f86c8fbc3fc398808f4d69e Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sat, 5 Sep 2015 18:01:31 -0500
+Subject: [PATCH 011/139] northbridge/amd/amdfam10: Fix typo in comment
+
+Change-Id: I0a9b3a66231052622c862bae32b900f52f6efba9
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdfam10/misc_control.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
+index e242e34..90a4db1 100644
+--- a/src/northbridge/amd/amdfam10/misc_control.c
++++ b/src/northbridge/amd/amdfam10/misc_control.c
+@@ -47,7 +47,7 @@
+  * The same trick can be used to augment legacy VGA resources which can
+  * be detect by generic pci reousrce allocator for VGA devices.
+  * BAD: it is more tricky than I think, the resource allocation code is
+- * implemented in a way to NOT DOING legacy VGA resource allcation on
++ * implemented in a way to NOT DOING legacy VGA resource allocation on
+  * purpose :-(.
+  */
+ static void mcf3_read_resources(device_t dev)
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0015-device-hypertransport-Add-additional-debug-output.patch b/resources/libreboot/patch/kgpe-d16/0012-device-hypertransport-Add-additional-debug-output.patch
index 1ca8d3a..61a3c56 100644
--- a/resources/libreboot/patch/kgpe-d16/0015-device-hypertransport-Add-additional-debug-output.patch
+++ b/resources/libreboot/patch/kgpe-d16/0012-device-hypertransport-Add-additional-debug-output.patch
@@ -1,10 +1,12 @@
-From c8c17707af0850b4e520a2616e217e9fae2cf0e3 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 8791b352073e2738c7adfee154ffcab65ae6cdd6 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:06:52 -0500
-Subject: [PATCH 015/146] device/hypertransport: Add additional debug output
+Subject: [PATCH 012/139] device/hypertransport: Add additional debug output
 
+Change-Id: I94b870f47581a4a2591d02eeb37627666e0f4297
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/device/hypertransport.c |    3 +++
+ src/device/hypertransport.c | 3 +++
  1 file changed, 3 insertions(+)
 
 diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
@@ -29,5 +31,5 @@ index 07a320d..c76cb21 100644
  
  #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0016-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch b/resources/libreboot/patch/kgpe-d16/0013-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch
index 53b7e19..7dc753a 100644
--- a/resources/libreboot/patch/kgpe-d16/0016-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0013-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch
@@ -1,30 +1,33 @@
-From ef853baaaec3bf5aee31f443a7930f9882e3a01c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 2515607768d1699c148a9eee0e40ccaeb8bb0650 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 30 Apr 2015 01:47:31 -0500
-Subject: [PATCH 016/146] mainboard/asus/kgpe-d16: Add initial support for the
+Subject: [PATCH 013/139] mainboard/asus/kgpe-d16: Add initial support for the
  KGPE-D16
 
 As of this commit S3 suspend does not work on any K10 boards,
 including this board.
+
+Change-Id: Idd3971422fb2473bff7c60fe8d8161d6e20808ed
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/Kconfig          |   95 ++++
- src/mainboard/asus/kgpe-d16/Kconfig.name     |    2 +
- src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl |  367 +++++++++++++
- src/mainboard/asus/kgpe-d16/acpi_tables.c    |   75 +++
- src/mainboard/asus/kgpe-d16/board_info.txt   |    5 +
- src/mainboard/asus/kgpe-d16/bootblock.c      |   52 ++
- src/mainboard/asus/kgpe-d16/cmos.default     |   16 +
- src/mainboard/asus/kgpe-d16/cmos.layout      |  134 +++++
- src/mainboard/asus/kgpe-d16/devicetree.cb    |  248 +++++++++
- src/mainboard/asus/kgpe-d16/dsdt.asl         |  730 ++++++++++++++++++++++++++
- src/mainboard/asus/kgpe-d16/get_bus_conf.c   |  128 +++++
- src/mainboard/asus/kgpe-d16/irq_tables.c     |  112 ++++
- src/mainboard/asus/kgpe-d16/mainboard.c      |   81 +++
- src/mainboard/asus/kgpe-d16/mb_sysconf.h     |   44 ++
- src/mainboard/asus/kgpe-d16/mptable.c        |  231 ++++++++
- src/mainboard/asus/kgpe-d16/resourcemap.c    |  284 ++++++++++
- src/mainboard/asus/kgpe-d16/romstage.c       |  422 +++++++++++++++
- src/mainboard/asus/kgpe-d16/spd_notes.txt    |   30 ++
+ src/mainboard/asus/kgpe-d16/Kconfig          |  95 ++++
+ src/mainboard/asus/kgpe-d16/Kconfig.name     |   2 +
+ src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 367 ++++++++++++++
+ src/mainboard/asus/kgpe-d16/acpi_tables.c    |  75 +++
+ src/mainboard/asus/kgpe-d16/board_info.txt   |   5 +
+ src/mainboard/asus/kgpe-d16/bootblock.c      |  52 ++
+ src/mainboard/asus/kgpe-d16/cmos.default     |  16 +
+ src/mainboard/asus/kgpe-d16/cmos.layout      | 134 +++++
+ src/mainboard/asus/kgpe-d16/devicetree.cb    | 248 +++++++++
+ src/mainboard/asus/kgpe-d16/dsdt.asl         | 730 +++++++++++++++++++++++++++
+ src/mainboard/asus/kgpe-d16/get_bus_conf.c   | 128 +++++
+ src/mainboard/asus/kgpe-d16/irq_tables.c     | 112 ++++
+ src/mainboard/asus/kgpe-d16/mainboard.c      |  81 +++
+ src/mainboard/asus/kgpe-d16/mb_sysconf.h     |  44 ++
+ src/mainboard/asus/kgpe-d16/mptable.c        | 231 +++++++++
+ src/mainboard/asus/kgpe-d16/resourcemap.c    | 284 +++++++++++
+ src/mainboard/asus/kgpe-d16/romstage.c       | 422 ++++++++++++++++
+ src/mainboard/asus/kgpe-d16/spd_notes.txt    |  30 ++
  18 files changed, 3056 insertions(+)
  create mode 100644 src/mainboard/asus/kgpe-d16/Kconfig
  create mode 100644 src/mainboard/asus/kgpe-d16/Kconfig.name
@@ -844,7 +847,7 @@ index 0000000..bcf9cd3
 +checksum 392 983 984
 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
 new file mode 100644
-index 0000000..d0288da
+index 0000000..a172d89
 --- /dev/null
 +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
 @@ -0,0 +1,248 @@
@@ -908,7 +911,7 @@ index 0000000..d0288da
 +	 				device pci 14.0 on end			# SM
 +					device pci 14.1 on end			# IDE 0x439c
 +					device pci 14.2 off end			# HDA 0x4383 (KGPE-D16 omits audio option)
-+					device pci 14.3 on			# LPC 0x439d
++					device pci 14.3 on			# LPC 0x439d (SMBUS primary controller)
 +						chip superio/nuvoton/nct5572d	# Super I/O
 +							device pnp 2e.0 off end	# FDC; Not available on the KGPE-D16
 +							device pnp 2e.1 off end	# LPT1; Not available on the KGPE-D16
@@ -1060,7 +1063,7 @@ index 0000000..d0288da
 +							register "vsb_low_limit_mv" = "3100"		# 3VSB low limit to 3.1V
 +							register "vbat_high_limit_mv" = "3500"		# VBAT (+3V) high limit to 3.5V
 +							register "vbat_low_limit_mv" = "2500"		# VBAT (+3V) low limit to 2.5V
-+							register "smbus_aux" = "1"			# Device located on auxiliary SMBUS
++							register "smbus_aux" = "1"			# Device located on auxiliary SMBUS controller
 +							device i2c 0x2f on end
 +						end
 +					end
@@ -3214,5 +3217,5 @@ index 0000000..623a88f
 +RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61
 +Normal is HIGH, recovery is LOW.
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0017-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch b/resources/libreboot/patch/kgpe-d16/0014-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch
index bfed158..073e2dc 100644
--- a/resources/libreboot/patch/kgpe-d16/0017-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch
+++ b/resources/libreboot/patch/kgpe-d16/0014-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch
@@ -1,13 +1,15 @@
-From 09718eb82377722bec9b445cb8f7104e908724c1 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 7137414550b7ef1d1f1d90e31c73eda392ab663d Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 11 Aug 2015 18:38:06 -0500
-Subject: [PATCH 017/146] mainboard/asus/kgpe-d16: Add nvram option to
+Subject: [PATCH 014/139] mainboard/asus/kgpe-d16: Add nvram option to
  enable/disable the IEEE1394 controller
 
+Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.default |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout  |    1 +
- src/mainboard/asus/kgpe-d16/romstage.c   |   21 +++++++++++++++++----
+ src/mainboard/asus/kgpe-d16/cmos.default |  1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout  |  1 +
+ src/mainboard/asus/kgpe-d16/romstage.c   | 21 +++++++++++++++++----
  3 files changed, 19 insertions(+), 4 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -66,5 +68,5 @@ index 9964cfe..616fdfb 100644
  	/* Enable the RTC AltCentury register */
  	outb(0x41, 0xcd6);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0014-northbridge-amd-amdfam10-Fix-typo-in-comment.patch b/resources/libreboot/patch/kgpe-d16/0014-northbridge-amd-amdfam10-Fix-typo-in-comment.patch
deleted file mode 100644
index 85b258a..0000000
--- a/resources/libreboot/patch/kgpe-d16/0014-northbridge-amd-amdfam10-Fix-typo-in-comment.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From d5701700c4c905866a58c600b7a9f1a7f534e5f6 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Sat, 5 Sep 2015 18:01:31 -0500
-Subject: [PATCH 014/146] northbridge/amd/amdfam10: Fix typo in comment
-
----
- src/northbridge/amd/amdfam10/misc_control.c |    3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
-index e242e34..85c8838 100644
---- a/src/northbridge/amd/amdfam10/misc_control.c
-+++ b/src/northbridge/amd/amdfam10/misc_control.c
-@@ -4,6 +4,7 @@
-  * Copyright (C) 2003 by Eric Biederman
-  * Copyright (C) Stefan Reinauer
-  * Copyright (C) 2007 Advanced Micro Devices, Inc.
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-@@ -47,7 +48,7 @@
-  * The same trick can be used to augment legacy VGA resources which can
-  * be detect by generic pci reousrce allocator for VGA devices.
-  * BAD: it is more tricky than I think, the resource allocation code is
-- * implemented in a way to NOT DOING legacy VGA resource allcation on
-+ * implemented in a way to NOT DOING legacy VGA resource allocation on
-  * purpose :-(.
-  */
- static void mcf3_read_resources(device_t dev)
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0018-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch b/resources/libreboot/patch/kgpe-d16/0015-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch
index 79b7c67..1bf44c0 100644
--- a/resources/libreboot/patch/kgpe-d16/0018-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch
+++ b/resources/libreboot/patch/kgpe-d16/0015-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch
@@ -1,10 +1,12 @@
-From b4e60bb51855c3edb3c41fbe7f6378a638df9a95 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 158141bedc473c21a11918605dc7e76eee0c43e5 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:46:54 -0500
-Subject: [PATCH 018/146] cpu/amd/model_10xxx: Clean up debugging statements
+Subject: [PATCH 015/139] cpu/amd/model_10xxx: Clean up debugging statements
 
+Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/fidvid.c |   43 +++++++++++++++++++-------------------
+ src/cpu/amd/model_10xxx/fidvid.c | 43 ++++++++++++++++++++--------------------
  1 file changed, 21 insertions(+), 22 deletions(-)
 
 diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
@@ -110,5 +112,5 @@ index 36bdf36..99ffcc8 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0019-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch b/resources/libreboot/patch/kgpe-d16/0016-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch
index a097102..446d1e8 100644
--- a/resources/libreboot/patch/kgpe-d16/0019-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0016-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch
@@ -1,17 +1,19 @@
-From a0ab6743661d88d7e7c699bc8e506e9b1243749c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 4e9327a08f16505bbcdeb49592ded51873a4d62f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:14:25 -0500
-Subject: [PATCH 019/146] southbridge/amd/sb700: Add Suspend to RAM (S3)
+Subject: [PATCH 016/139] southbridge/amd/sb700: Add Suspend to RAM (S3)
  support
 
+Change-Id: Ic643e31b721f11a90d8fb5f8c8f8a3b7892c0d73
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/Makefile.inc  |    1 +
- src/southbridge/amd/sb700/bootblock.c   |    4 +-
- src/southbridge/amd/sb700/early_setup.c |   39 ++++++--
- src/southbridge/amd/sb700/lpc.c         |   12 ++-
- src/southbridge/amd/sb700/sb700.h       |    3 +
- src/southbridge/amd/sb700/spi.c         |  148 +++++++++++++++++++++++++++++++
- src/southbridge/amd/sb700/spi.h         |   21 +++++
+ src/southbridge/amd/sb700/Makefile.inc  |   1 +
+ src/southbridge/amd/sb700/bootblock.c   |   4 +-
+ src/southbridge/amd/sb700/early_setup.c |  39 +++++++--
+ src/southbridge/amd/sb700/lpc.c         |  12 ++-
+ src/southbridge/amd/sb700/sb700.h       |   3 +
+ src/southbridge/amd/sb700/spi.c         | 148 ++++++++++++++++++++++++++++++++
+ src/southbridge/amd/sb700/spi.h         |  21 +++++
  7 files changed, 216 insertions(+), 12 deletions(-)
  create mode 100644 src/southbridge/amd/sb700/spi.c
  create mode 100644 src/southbridge/amd/sb700/spi.h
@@ -361,5 +363,5 @@ index 0000000..9b76b35
 +void spi_release_bus(struct spi_slave *slave);
 \ No newline at end of file
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0020-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch b/resources/libreboot/patch/kgpe-d16/0017-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch
index 7f55dae..e7ce695 100644
--- a/resources/libreboot/patch/kgpe-d16/0020-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch
+++ b/resources/libreboot/patch/kgpe-d16/0017-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch
@@ -1,11 +1,13 @@
-From 5f367eefa624cdc66127e0effafdc08d68352c4e Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From d09d475241b1017919ac2048177ce5ab60f7328f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:26:30 -0500
-Subject: [PATCH 020/146] superio/nuvoton/nct5572d: Enable power state after
+Subject: [PATCH 017/139] superio/nuvoton/nct5572d: Enable power state after
  power failure support
 
+Change-Id: Ia0313b9ecd64c9e6f99a140772ebb35abe0175fd
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/superio/nuvoton/nct5572d/superio.c |   31 +++++++++++++++++++++++++++++++
+ src/superio/nuvoton/nct5572d/superio.c | 31 +++++++++++++++++++++++++++++++
  1 file changed, 31 insertions(+)
 
 diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c
@@ -76,5 +78,5 @@ index c5278d6..ccf2416 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0021-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch b/resources/libreboot/patch/kgpe-d16/0018-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch
index d9b8f34..0fac423 100644
--- a/resources/libreboot/patch/kgpe-d16/0021-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch
+++ b/resources/libreboot/patch/kgpe-d16/0018-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch
@@ -1,15 +1,16 @@
-From 9e460817405fe102ad414a71c85ff2b68a8f4469 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 38e3b0862f6e914b010c004ff03cb9063452e26c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:39:34 -0500
-Subject: [PATCH 021/146] northbridge/amd/amdfam10: Add Suspend to RAM (S3)
+Subject: [PATCH 018/139] northbridge/amd/amdfam10: Add Suspend to RAM (S3)
  Flash data storage area
 
+Change-Id: I169fafc3a61e11c3e4781190053e57bf34502d7b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/Kconfig          |    6 +++
- src/northbridge/amd/amdfam10/Makefile.inc     |   19 ++++++++++
- src/northbridge/amd/amdfam10/northbridge.c    |    4 ++
- src/northbridge/amd/amdfam10/raminit_amdmct.c |   50 ++++++++++++++-----------
- 4 files changed, 57 insertions(+), 22 deletions(-)
+ src/northbridge/amd/amdfam10/Kconfig          |  6 ++++
+ src/northbridge/amd/amdfam10/Makefile.inc     | 19 ++++++++++
+ src/northbridge/amd/amdfam10/raminit_amdmct.c | 50 +++++++++++++++------------
+ 3 files changed, 53 insertions(+), 22 deletions(-)
 
 diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
 index 4d7147d..ff92fca 100644
@@ -56,33 +57,11 @@ index 8a105fd..b4097b4 100644
 +endif
 +
  endif
-diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index 7bd8675..880129b 100644
---- a/src/northbridge/amd/amdfam10/northbridge.c
-+++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -54,6 +54,8 @@
- #include <sb_cimx.h>
- #endif
- 
-+#include "../amdmct/mct_ddr3/s3utils.h"
-+
- struct amdfam10_sysconf_t sysconf;
- 
- #define FX_DEVS NODE_NUMS
-@@ -1413,6 +1415,8 @@ static void root_complex_enable_dev(struct device *dev)
- 	/* Do not delay UMA setup, as a device on the PCI bus may evaluate
- 	   the global uma_memory variables already in its enable function. */
- 	if (!done) {
-+		save_mct_information_to_nvram();
-+
- 		setup_bsp_ramtop();
- 		setup_uma_memory();
- 		done = 1;
 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-index fa14e4f..9c2612c 100644
+index 3f33eba..5068e7a 100644
 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
 +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-@@ -101,6 +101,10 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq
+@@ -110,6 +110,10 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq
  #include "../amdmct/mct_ddr3/mct_d.h"
  #include "../amdmct/mct_ddr3/mct_d_gcc.h"
  
@@ -93,7 +72,7 @@ index fa14e4f..9c2612c 100644
  #include "../amdmct/wrappers/mcti_d.c"
  #include "../amdmct/mct_ddr3/mct_d.c"
  
-@@ -240,33 +244,35 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
+@@ -249,33 +253,35 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
  	size_t i;
  	struct DCTStatStruc *pDCTstatA = NULL;
  
@@ -152,5 +131,5 @@ index fa14e4f..9c2612c 100644
  }
  #endif
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0022-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch b/resources/libreboot/patch/kgpe-d16/0019-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch
index de64998..482bedb 100644
--- a/resources/libreboot/patch/kgpe-d16/0022-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0019-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch
@@ -1,23 +1,52 @@
-From 2a7645f564b30a7914b8036c1b6919c9ffcbf9a2 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From b1e36a17d254e15459729ebfc3a83df4a2b28468 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:40:31 -0500
-Subject: [PATCH 022/146] northbridge/amd/amdmct/mct_ddr3: Add initial Suspend
+Subject: [PATCH 019/139] northbridge/amd/amdmct/mct_ddr3: Add initial Suspend
  to RAM (S3) support
 
+Change-Id: Ic97567851fa40295bc21cefd7537407b99d71709
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   |  166 +++----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |  112 +++++
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |  612 +++++++++++++++++++++++++
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h |   28 ++
- 4 files changed, 839 insertions(+), 79 deletions(-)
+ src/northbridge/amd/amdfam10/northbridge.c    |   8 +
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   | 154 ++++---
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   | 112 +++++
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 610 ++++++++++++++++++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.h |  28 ++
+ 5 files changed, 840 insertions(+), 72 deletions(-)
  create mode 100644 src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
  create mode 100644 src/northbridge/amd/amdmct/mct_ddr3/s3utils.h
 
+diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
+index 74cecc8..9cc3d96 100644
+--- a/src/northbridge/amd/amdfam10/northbridge.c
++++ b/src/northbridge/amd/amdfam10/northbridge.c
+@@ -54,6 +54,10 @@
+ #include <sb_cimx.h>
+ #endif
+ 
++#if IS_ENABLED(CONFIG_DIMM_DDR3)
++#include "../amdmct/mct_ddr3/s3utils.h"
++#endif
++
+ struct amdfam10_sysconf_t sysconf;
+ 
+ #define FX_DEVS NODE_NUMS
+@@ -1413,6 +1417,10 @@ static void root_complex_enable_dev(struct device *dev)
+ 	/* Do not delay UMA setup, as a device on the PCI bus may evaluate
+ 	   the global uma_memory variables already in its enable function. */
+ 	if (!done) {
++#if IS_ENABLED(CONFIG_DIMM_DDR3)
++		save_mct_information_to_nvram();
++#endif
++
+ 		setup_bsp_ramtop();
+ 		setup_uma_memory();
+ 		done = 1;
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index fa59d71..0c06444 100644
+index fa59d71..a8212c5 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -272,92 +272,100 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -272,91 +272,101 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  	u8 Node, NodesWmem;
  	u32 node_sys_base;
  
@@ -30,7 +59,18 @@ index fa59d71..0c06444 100644
 -	for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
 -		struct DCTStatStruc *pDCTstat;
 -		pDCTstat = pDCTstatA + Node;
--
++	if (s3resume) {
++#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
++		printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
++		restore_mct_information_from_nvram();
++#endif
++	} else {
++		NodesWmem = 0;
++		node_sys_base = 0;
++		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
++			struct DCTStatStruc *pDCTstat;
++			pDCTstat = pDCTstatA + Node;
+ 
 -		/* Zero out data structures to avoid false detection of DIMMs */
 -		memset(pDCTstat, 0, sizeof(struct DCTStatStruc));
 -
@@ -72,39 +112,9 @@ index fa59d71..0c06444 100644
 -		printk(BIOS_DEBUG, "No Nodes?!\n");
 -		goto fatalexit;
 -	}
--
--	printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n");
--	SyncDCTsReady_D(pMCTstat, pDCTstatA);	/* Make sure DCTs are ready for accesses.*/
--
--	printk(BIOS_DEBUG, "mctAutoInitMCT_D: HTMemMapInit_D\n");
--	HTMemMapInit_D(pMCTstat, pDCTstatA);	/* Map local memory into system address space.*/
--	mctHookAfterHTMap();
--
--	printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
--	CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */
--	mctHookAfterCPU();			/* Setup external northbridge(s) */
--
--	printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
--	DQSTiming_D(pMCTstat, pDCTstatA);	/* Get Receiver Enable and DQS signal timing*/
--
--	printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
--	UMAMemTyping_D(pMCTstat, pDCTstatA);	/* Fix up for UMA sizing */
--
--	printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
--	mct_OtherTiming(pMCTstat, pDCTstatA);
-+	if (s3resume) {
-+		printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
-+		restore_mct_information_from_nvram();
-+	} else {
-+		NodesWmem = 0;
-+		node_sys_base = 0;
-+		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
-+			struct DCTStatStruc *pDCTstat;
-+			pDCTstat = pDCTstatA + Node;
-+	
 +			/* Zero out data structures to avoid false detection of DIMMs */
 +			memset(pDCTstat, 0, sizeof(struct DCTStatStruc));
-+	
++
 +			/* Initialize data structures */
 +			pDCTstat->Node_ID = Node;
 +			pDCTstat->dev_host = PA_HOST(Node);
@@ -112,7 +122,7 @@ index fa59d71..0c06444 100644
 +			pDCTstat->dev_dct = PA_DCT(Node);
 +			pDCTstat->dev_nbmisc = PA_NBMISC(Node);
 +			pDCTstat->NodeSysBase = node_sys_base;
-+	
++
 +			printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_init Node %d\n", Node);
 +			mct_init(pMCTstat, pDCTstat);
 +			mctNodeIDDebugPort_D();
@@ -121,13 +131,13 @@ index fa59d71..0c06444 100644
 +				printk(BIOS_DEBUG, "mctAutoInitMCT_D: clear_legacy_Mode\n");
 +				clear_legacy_Mode(pMCTstat, pDCTstat);
 +				pDCTstat->LogicalCPUID = mctGetLogicalCPUID_D(Node);
-+	
++
 +				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_InitialMCT_D\n");
 +				mct_InitialMCT_D(pMCTstat, pDCTstat);
-+	
++
 +				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctSMBhub_Init\n");
 +				mctSMBhub_Init(Node);		/* Switch SMBUS crossbar to proper node*/
-+	
++
 +				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_initDCT\n");
 +				mct_initDCT(pMCTstat, pDCTstat);
 +				if (pDCTstat->ErrCode == SC_FatalErr) {
@@ -143,60 +153,73 @@ index fa59d71..0c06444 100644
 +			printk(BIOS_DEBUG, "No Nodes?!\n");
 +			goto fatalexit;
 +		}
-+	
+ 
+-	printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n");
+-	SyncDCTsReady_D(pMCTstat, pDCTstatA);	/* Make sure DCTs are ready for accesses.*/
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n");
 +		SyncDCTsReady_D(pMCTstat, pDCTstatA);	/* Make sure DCTs are ready for accesses.*/
-+	
+ 
+-	printk(BIOS_DEBUG, "mctAutoInitMCT_D: HTMemMapInit_D\n");
+-	HTMemMapInit_D(pMCTstat, pDCTstatA);	/* Map local memory into system address space.*/
+-	mctHookAfterHTMap();
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: HTMemMapInit_D\n");
 +		HTMemMapInit_D(pMCTstat, pDCTstatA);	/* Map local memory into system address space.*/
 +		mctHookAfterHTMap();
-+	
+ 
+-	printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
+-	CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */
+-	mctHookAfterCPU();			/* Setup external northbridge(s) */
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
 +		CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */
 +		mctHookAfterCPU();			/* Setup external northbridge(s) */
-+
+ 
+-	printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
+-	DQSTiming_D(pMCTstat, pDCTstatA);	/* Get Receiver Enable and DQS signal timing*/
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
 +		DQSTiming_D(pMCTstat, pDCTstatA);	/* Get Receiver Enable and DQS signal timing*/
-+
+ 
+-	printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
+-	UMAMemTyping_D(pMCTstat, pDCTstatA);	/* Fix up for UMA sizing */
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
 +		UMAMemTyping_D(pMCTstat, pDCTstatA);	/* Fix up for UMA sizing */
-+
+ 
+-	printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
+-	mct_OtherTiming(pMCTstat, pDCTstatA);
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
 +		mct_OtherTiming(pMCTstat, pDCTstatA);
-+
-+
-+		if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/
-+			goto restartinit;
-+		}
  
 -	if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/
 -		goto restartinit;
 -	}
-+		InterleaveNodes_D(pMCTstat, pDCTstatA);
-+		InterleaveChannels_D(pMCTstat, pDCTstatA);
  
 -	InterleaveNodes_D(pMCTstat, pDCTstatA);
 -	InterleaveChannels_D(pMCTstat, pDCTstatA);
-+		printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n");
-+		if (ECCInit_D(pMCTstat, pDCTstatA)) {		/* Setup ECC control and ECC check-bits*/
-+			printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n");
-+			MCTMemClr_D(pMCTstat,pDCTstatA);
++		if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/
++			goto restartinit;
 +		}
  
 -	printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n");
 -	if (ECCInit_D(pMCTstat, pDCTstatA)) {		/* Setup ECC control and ECC check-bits*/
 -		printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n");
 -		MCTMemClr_D(pMCTstat,pDCTstatA);
-+		mct_FinalMCT_D(pMCTstat, pDCTstatA);
-+		printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus);
- 	}
+-	}
++		InterleaveNodes_D(pMCTstat, pDCTstatA);
++		InterleaveChannels_D(pMCTstat, pDCTstatA);
++
++		printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n");
++		if (ECCInit_D(pMCTstat, pDCTstatA)) {		/* Setup ECC control and ECC check-bits*/
++			printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n");
++			MCTMemClr_D(pMCTstat,pDCTstatA);
++		}
  
 -	mct_FinalMCT_D(pMCTstat, pDCTstatA);
 -	printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus);
--
++		mct_FinalMCT_D(pMCTstat, pDCTstatA);
++		printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus);
++	}
+ 
  	return;
  
- fatalexit:
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
 index 219aa42..c790d7e 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -329,10 +352,10 @@ index 219aa42..c790d7e 100644
  ===============================================================================*/
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 new file mode 100644
-index 0000000..79576d6
+index 0000000..78523e8
 --- /dev/null
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-@@ -0,0 +1,612 @@
+@@ -0,0 +1,610 @@
 +/*
 + * This file is part of the coreboot project.
 + *
@@ -371,17 +394,15 @@ index 0000000..79576d6
 +
 +ssize_t get_s3nv_file_offset(void)
 +{
-+	struct cbfs_file file;
-+	ssize_t offset;
-+	struct cbfs_media *media = CBFS_DEFAULT_MEDIA;
-+
-+	offset = cbfs_locate_file(media, &file, S3NV_FILE_NAME);
-+	if (offset < 0) {
++	struct region_device s3nv_region;
++	struct cbfsf s3nv_cbfs_file;
++	if (cbfs_boot_locate(&s3nv_cbfs_file, S3NV_FILE_NAME, NULL)) {
 +		printk(BIOS_DEBUG, "S3 state file not found in CBFS: %s\n", S3NV_FILE_NAME);
 +		return -1;
 +	}
++	cbfs_file_data(&s3nv_region, &s3nv_cbfs_file);
 +
-+	return offset;
++	return s3nv_region.region.offset;
 +}
 +
 +static uint32_t read_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, uint32_t index)
@@ -982,5 +1003,5 @@ index 0000000..dcddcad
 +void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data);
 \ No newline at end of file
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0023-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch b/resources/libreboot/patch/kgpe-d16/0020-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch
index 163bd7a..672a21f 100644
--- a/resources/libreboot/patch/kgpe-d16/0023-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0020-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch
@@ -1,10 +1,12 @@
-From 9ce37d36d63d39880fb2ff50823d087c93e3d7d3 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 043f3abb58733fe14feb7cca5c2101f6a905aeb8 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:46:24 -0500
-Subject: [PATCH 023/146] cpu/amd/car: Add initial Suspend to RAM (S3) support
+Subject: [PATCH 020/139] cpu/amd/car: Add initial Suspend to RAM (S3) support
 
+Change-Id: I1e1a67fa3c2c13cebcf8f0af318055b9d97d0a59
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/car/post_cache_as_ram.c |   12 ++++++++++++
+ src/cpu/amd/car/post_cache_as_ram.c | 12 ++++++++++++
  1 file changed, 12 insertions(+)
 
 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
@@ -50,5 +52,5 @@ index 230d1aa..e265de1 100644
  	prepare_ramstage_region(resume_backup_memory);
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0024-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch b/resources/libreboot/patch/kgpe-d16/0021-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch
index 711736e..83ee459 100644
--- a/resources/libreboot/patch/kgpe-d16/0024-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch
+++ b/resources/libreboot/patch/kgpe-d16/0021-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch
@@ -1,15 +1,17 @@
-From f8fce40052840f6c876cfdc85caaec91de977a38 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 65fa0d700672fcc4556f0d3300912e336a727d87 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 7 May 2015 01:32:08 -0500
-Subject: [PATCH 024/146] mainboard/asus/kgpe-d16: Add initial Suspend to RAM
+Subject: [PATCH 021/139] mainboard/asus/kgpe-d16: Add initial Suspend to RAM
  (S3) support
 
+Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/Kconfig          |    3 +
- src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl |  639 +++++++++++++-------------
- src/mainboard/asus/kgpe-d16/dsdt.asl         |    5 +-
- src/mainboard/asus/kgpe-d16/romstage.c       |   34 +-
- src/mainboard/asus/kgpe-d16/spd_notes.txt    |   16 +
+ src/mainboard/asus/kgpe-d16/Kconfig          |   3 +
+ src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 639 ++++++++++++++-------------
+ src/mainboard/asus/kgpe-d16/dsdt.asl         |   5 +-
+ src/mainboard/asus/kgpe-d16/romstage.c       |  34 +-
+ src/mainboard/asus/kgpe-d16/spd_notes.txt    |  16 +
  5 files changed, 369 insertions(+), 328 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
@@ -826,5 +828,5 @@ index 623a88f..ddd5cc8 100644
 +Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
 \ No newline at end of file
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0025-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch b/resources/libreboot/patch/kgpe-d16/0022-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch
index e4ec543..debb88e 100644
--- a/resources/libreboot/patch/kgpe-d16/0025-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch
+++ b/resources/libreboot/patch/kgpe-d16/0022-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch
@@ -1,11 +1,13 @@
-From 10204a5acccb903d407b241501e316506199f60d Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From ec5844dce6ad1a2c1528ea7cb6f41f408fd48a4f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 19:00:34 -0500
-Subject: [PATCH 025/146] include/smbios: Update SMBIOS memory structures to
+Subject: [PATCH 022/139] include/smbios: Update SMBIOS memory structures to
  version 2.8
 
+Change-Id: Icda915933c4ebf3a735d9e1d4e4dbb1138a06b39
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/include/smbios.h |    6 ++++--
+ src/include/smbios.h | 6 ++++--
  1 file changed, 4 insertions(+), 2 deletions(-)
 
 diff --git a/src/include/smbios.h b/src/include/smbios.h
@@ -27,5 +29,5 @@ index b654c23..fdb7bbd 100644
  } __attribute__((packed));
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch b/resources/libreboot/patch/kgpe-d16/0023-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch
index 7c45877..0867c83 100644
--- a/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch
+++ b/resources/libreboot/patch/kgpe-d16/0023-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch
@@ -1,16 +1,34 @@
-From ca270728b0d2232efb4384f645d993403f4bc24e Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 4cc0cdf4b04ba705d302a60a7f5905c17fe9bffe Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 18:56:05 -0500
-Subject: [PATCH 027/146] northbridge/amd/amdfam10: Set DIMM voltage based on
+Subject: [PATCH 023/139] northbridge/amd/amdfam10: Set DIMM voltage based on
  SPD data
 
+Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/acpi.c         |    3 +-
- src/northbridge/amd/amdfam10/northbridge.c  |   73 ++++++++++++++++++++++-----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |    6 +++
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |    6 +++
- 4 files changed, 73 insertions(+), 15 deletions(-)
+ src/northbridge/amd/amdfam10/Kconfig        |  4 ++
+ src/northbridge/amd/amdfam10/acpi.c         |  3 +-
+ src/northbridge/amd/amdfam10/northbridge.c  | 75 ++++++++++++++++++++++++-----
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |  8 +++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |  6 +++
+ 5 files changed, 81 insertions(+), 15 deletions(-)
 
+diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
+index ff92fca..ada5b9f 100644
+--- a/src/northbridge/amd/amdfam10/Kconfig
++++ b/src/northbridge/amd/amdfam10/Kconfig
+@@ -83,6 +83,10 @@ config DIMM_REGISTERED
+ 	bool
+ 	default n
+ 
++config DIMM_VOLTAGE_SET_SUPPORT
++	bool
++	default n
++
+ if DIMM_FBDIMM
+ 	config DIMM_SUPPORT
+ 		hex
 diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
 index 4b86e96..92433bb 100644
 --- a/src/northbridge/amd/amdfam10/acpi.c
@@ -26,10 +44,10 @@ index 4b86e96..92433bb 100644
  		}
  	}
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index 880129b..d0a0787 100644
+index 9cc3d96..3b302e8 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -948,19 +948,38 @@ static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *cur
+@@ -950,19 +950,38 @@ static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *cur
  
  static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed)
  {
@@ -81,7 +99,7 @@ index 880129b..d0a0787 100644
  	}
  }
  
-@@ -1046,6 +1065,34 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
+@@ -1048,6 +1067,36 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
  					snprintf(string_buffer, sizeof (string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]);
  					t->serial_number = smbios_add_string(t->eos, string_buffer);
  				}
@@ -91,6 +109,7 @@ index 880129b..d0a0787 100644
 +					t->maximum_voltage = 1800;
 +					t->configured_voltage = 1800;
 +				} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
++#if IS_ENABLED(CONFIG_DIMM_DDR3)
 +					/* Find the maximum and minimum supported voltages */
 +					uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot];
 +					if (supported_voltages & 0x8)
@@ -112,25 +131,28 @@ index 880129b..d0a0787 100644
 +						t->maximum_voltage = 1150;
 +
 +					t->configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot];
++#endif
 +				}
  				t->memory_error_information_handle = 0xFFFE;	/* no error information handle available */
  				single_len = t->length + smbios_string_table_len(t->eos);
  				len += single_len;
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 0c06444..303c6c7 100644
+index a8212c5..12dfff1 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -327,6 +327,9 @@ restartinit:
- 			printk(BIOS_DEBUG, "No Nodes?!\n");
+@@ -330,6 +330,11 @@ restartinit:
  			goto fatalexit;
  		}
-+
+ 
++#if IS_ENABLED(DIMM_VOLTAGE_SET_SUPPORT)
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: DIMMSetVoltage\n");
 +		DIMMSetVoltages(pMCTstat, pDCTstatA);	/* Set the DIMM voltages (mainboard specific) */
- 	
++#endif
++
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n");
  		SyncDCTsReady_D(pMCTstat, pDCTstatA);	/* Make sure DCTs are ready for accesses.*/
-@@ -2120,6 +2123,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+ 
+@@ -2122,6 +2127,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  					pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3);
  					pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3);
  				}
@@ -172,5 +194,5 @@ index c790d7e..a947c2d 100644
  void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
  void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0026-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch b/resources/libreboot/patch/kgpe-d16/0024-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch
index bdf17ce..059aefc 100644
--- a/resources/libreboot/patch/kgpe-d16/0026-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch
+++ b/resources/libreboot/patch/kgpe-d16/0024-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch
@@ -1,15 +1,30 @@
-From b5d34134e15285aeff92567703530d5c7d372562 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 7cc2167cf68f778b06a3defcb42b6b9ebdbce2e5 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 10 May 2015 04:37:56 -0500
-Subject: [PATCH 026/146] mainboard/asus/kgpe-d16: Set DDR3 memory voltage
+Subject: [PATCH 024/139] mainboard/asus/kgpe-d16: Set DDR3 memory voltage
  based on SPD data
 
+Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.default |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout  |    5 ++
- src/mainboard/asus/kgpe-d16/romstage.c   |   76 ++++++++++++++++++++++++++++--
- 3 files changed, 77 insertions(+), 5 deletions(-)
+ src/mainboard/asus/kgpe-d16/Kconfig      |  1 +
+ src/mainboard/asus/kgpe-d16/cmos.default |  1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout  |  5 +++
+ src/mainboard/asus/kgpe-d16/romstage.c   | 76 +++++++++++++++++++++++++++++---
+ 4 files changed, 78 insertions(+), 5 deletions(-)
 
+diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
+index f9556fc..9471692 100644
+--- a/src/mainboard/asus/kgpe-d16/Kconfig
++++ b/src/mainboard/asus/kgpe-d16/Kconfig
+@@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+ 	select DIMM_DDR3
+ 	select DIMM_REGISTERED
+ 	# select QRANK_DIMM_SUPPORT
++	select DIMM_VOLTAGE_SET_SUPPORT
+ 	select NORTHBRIDGE_AMD_AMDFAM10
+ 	select SOUTHBRIDGE_AMD_SR5650
+ 	select SOUTHBRIDGE_AMD_SB700
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
 index e920297..39a4778 100644
 --- a/src/mainboard/asus/kgpe-d16/cmos.default
@@ -147,5 +162,5 @@ index 3431bab..18e7c16 100644
  	set_lpc_sticky_ctl(1);	/* Retain LPC/IMC GPIO configuration during S3 sleep */
  	if (!s3resume) {	/* Avoid supply voltage glitches while the DIMMs are retaining data */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-romstage-spinlock-option.patch b/resources/libreboot/patch/kgpe-d16/0025-src-console-Add-x86-romstage-spinlock-option.patch
index 97b6fa6..2f8ef7f 100644
--- a/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-romstage-spinlock-option.patch
+++ b/resources/libreboot/patch/kgpe-d16/0025-src-console-Add-x86-romstage-spinlock-option.patch
@@ -1,11 +1,13 @@
-From 14dead11fc372b694a24358216b60bdd274d8d21 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 2eced49516682afa1c56ac1e83a8f4260d4dec2a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 18 May 2015 16:04:10 -0500
-Subject: [PATCH 028/146] src/console: Add x86 romstage spinlock option
+Subject: [PATCH 025/139] src/console: Add x86 romstage spinlock option
 
+Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/arch/x86/include/arch/smp/spinlock.h |   10 +++++++++-
- src/console/printk.c                     |   19 +++++++++++++++++++
+ src/arch/x86/include/arch/smp/spinlock.h | 10 +++++++++-
+ src/console/printk.c                     | 19 +++++++++++++++++++
  2 files changed, 28 insertions(+), 1 deletion(-)
 
 diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
@@ -94,5 +96,5 @@ index aab7ff5..2aae980 100644
  
  	return i;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0029-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch b/resources/libreboot/patch/kgpe-d16/0026-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch
index 3c734e0..638d21b 100644
--- a/resources/libreboot/patch/kgpe-d16/0029-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch
+++ b/resources/libreboot/patch/kgpe-d16/0026-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch
@@ -1,18 +1,20 @@
-From 0004a1c007784bd577e2323061cd12460b76b2a8 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From ff54c12aa8d07a74ff4e84a5b020f64eb554ac4c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 31 May 2015 18:46:40 -0500
-Subject: [PATCH 029/146] northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend
+Subject: [PATCH 026/139] northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend
  overrunning the stack size limit
 
+Change-Id: Id7441dacef2e46e283d1fc99d5e5fa3f20e0d097
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |   16 +++++++++++++---
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 16 +++++++++++++---
  1 file changed, 13 insertions(+), 3 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index 79576d6..2ea7dc1 100644
+index 78523e8..1dcbea0 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-@@ -545,10 +545,17 @@ int8_t save_mct_information_to_nvram(void)
+@@ -543,10 +543,17 @@ int8_t save_mct_information_to_nvram(void)
  
  	struct spi_flash *flash;
  	ssize_t s3nv_offset;
@@ -32,7 +34,7 @@ index 79576d6..2ea7dc1 100644
  
  	/* Obtain CBFS file offset */
  	s3nv_offset = get_s3nv_file_offset();
-@@ -578,7 +585,10 @@ int8_t save_mct_information_to_nvram(void)
+@@ -576,7 +583,10 @@ int8_t save_mct_information_to_nvram(void)
  
  	/* Erase and write data structure */
  	flash->erase(flash, s3nv_offset, CONFIG_S3_DATA_SIZE);
@@ -45,5 +47,5 @@ index 79576d6..2ea7dc1 100644
  	/* Tear down SPI flash access */
  	flash->spi->rw = SPI_WRITE_FLAG;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch b/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch
new file mode 100644
index 0000000..852fc39
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch
@@ -0,0 +1,53 @@
+From ade973158610c177dcdaa98cef1b44ebd6ad9255 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Mon, 1 Jun 2015 02:40:24 -0500
+Subject: [PATCH 027/139] northbridge/amd/amdmct/mct_ddr3: Fix failing S3
+ resume
+
+Change-Id: I852a8132ff2f39f9297447455ad03d728ce9c5f6
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 16 +++++++++++++---
+ 1 file changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+index 1dcbea0..c9bcac1 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+@@ -602,7 +602,9 @@ int8_t save_mct_information_to_nvram(void)
+ int8_t restore_mct_information_from_nvram(void)
+ {
+ 	ssize_t s3nv_offset;
+-	struct amd_s3_persistent_data persistent_data;
++	ssize_t s3nv_file_offset;
++	void * s3nv_cbfs_file_ptr;
++	struct amd_s3_persistent_data *persistent_data;
+ 
+ 	/* Obtain CBFS file offset */
+ 	s3nv_offset = get_s3nv_file_offset();
+@@ -610,11 +612,19 @@ int8_t restore_mct_information_from_nvram(void)
+ 		return -1;
+ 
+ 	/* Align flash pointer to nearest boundary */
++	s3nv_file_offset = s3nv_offset;
+ 	s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1);
+ 	s3nv_offset += CONFIG_S3_DATA_SIZE;
++	s3nv_file_offset = s3nv_offset - s3nv_file_offset;
+ 
+-	cbfs_read(CBFS_DEFAULT_MEDIA, &persistent_data, s3nv_offset, sizeof(struct amd_s3_persistent_data));
+-	restore_mct_data_from_save_variable(&persistent_data);
++	/* Map data structure in CBFS and restore settings */
++	s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL);
++	if (!s3nv_cbfs_file_ptr) {
++		printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME);
++		return -1;
++	}
++	persistent_data = (s3nv_cbfs_file_ptr + s3nv_file_offset);
++	restore_mct_data_from_save_variable(persistent_data);
+ 
+ 	return 0;
+ }
+\ No newline at end of file
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0032-src-console-Add-x86-printk-spinlock-support.patch b/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-printk-spinlock-support.patch
index 9f4c705..2baeb9c 100644
--- a/resources/libreboot/patch/kgpe-d16/0032-src-console-Add-x86-printk-spinlock-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-printk-spinlock-support.patch
@@ -1,17 +1,20 @@
-From c15c778ced025a5a778e4c1d7ad03a40529f4d41 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5748ef1b46c9625a81b63c9141dfe2bf55dccc20 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 19:23:49 -0500
-Subject: [PATCH 032/146] src/console: Add x86 printk spinlock support
+Subject: [PATCH 028/139] src/console: Add x86 printk spinlock support
 
+Change-Id: Ib189ab842ede603b8d5080012ceb92e6964d4fe0
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/Kconfig                              |    4 ++++
- src/arch/x86/include/arch/smp/spinlock.h |    1 +
- src/console/printk.c                     |    6 +++---
- src/cpu/amd/car/post_cache_as_ram.c      |   22 +++++++++++++++-------
- 4 files changed, 23 insertions(+), 10 deletions(-)
+ src/Kconfig                              |  4 ++++
+ src/arch/x86/include/arch/smp/spinlock.h |  1 +
+ src/console/printk.c                     |  6 +++---
+ src/cpu/amd/car/disable_cache_as_ram.c   | 10 ++++++++++
+ src/cpu/amd/car/post_cache_as_ram.c      | 20 ++++++++++++++------
+ 5 files changed, 32 insertions(+), 9 deletions(-)
 
 diff --git a/src/Kconfig b/src/Kconfig
-index bab05f2..2e6b5bc 100644
+index 2822bfe..4e46364 100644
 --- a/src/Kconfig
 +++ b/src/Kconfig
 @@ -447,6 +447,10 @@ config HAVE_HARD_RESET
@@ -68,8 +71,29 @@ index 2aae980..5a23db0 100644
  	spin_unlock(romstage_console_lock());
  #endif
  #else
+diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
+index 3b464b8..5eccf79 100644
+--- a/src/cpu/amd/car/disable_cache_as_ram.c
++++ b/src/cpu/amd/car/disable_cache_as_ram.c
+@@ -24,6 +24,16 @@
+ 
+ #include <cpu/x86/cache.h>
+ 
++static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
++{
++	uint32_t family;
++
++	family = cpuid_eax(0x80000001);
++	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
++
++	return family;
++}
++
+ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
+ {
+ 	msr_t msr;
 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
-index e265de1..e7a41e5 100644
+index e265de1..257b41a 100644
 --- a/src/cpu/amd/car/post_cache_as_ram.c
 +++ b/src/cpu/amd/car/post_cache_as_ram.c
 @@ -84,6 +84,10 @@ static void prepare_ramstage_region(void *resume_backup_memory)
@@ -89,13 +113,12 @@ index e265de1..e7a41e5 100644
  #ifdef BU_CFG2_MSR
 -    msr_t msr;
 -    unsigned int uiMask = 0xFFFFFFF7;
--
++	msr_t msr;
++	unsigned int uiMask = 0xFFFFFFF7;
+ 
 -    msr = rdmsr(BU_CFG2_MSR);
 -    msr.hi &= uiMask; // set bit 35 to 0
 -    wrmsr(BU_CFG2_MSR, msr);
-+	msr_t msr;
-+	unsigned int uiMask = 0xFFFFFFF7;
-+	
 +	msr = rdmsr(BU_CFG2_MSR);
 +	msr.hi &= uiMask;	// IcDisSpecTlbWr (bit 35) = 0
 +	wrmsr(BU_CFG2_MSR, msr);
@@ -122,5 +145,5 @@ index e265de1..e7a41e5 100644
  	size_t car_size = car_data_size();
  	void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0033-lib-stack-Add-stack-overrun-detection.patch b/resources/libreboot/patch/kgpe-d16/0029-lib-stack-Add-stack-overrun-detection.patch
index eef072d..b0fc1e3 100644
--- a/resources/libreboot/patch/kgpe-d16/0033-lib-stack-Add-stack-overrun-detection.patch
+++ b/resources/libreboot/patch/kgpe-d16/0029-lib-stack-Add-stack-overrun-detection.patch
@@ -1,10 +1,12 @@
-From d2d52a97ccabc604e0a4ee2f43522bac2f93d47a Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From aa92a6ff110c9fd77f6b157fa509988d597ad2e0 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 19:31:03 -0500
-Subject: [PATCH 033/146] lib/stack: Add stack overrun detection
+Subject: [PATCH 029/139] lib/stack: Add stack overrun detection
 
+Change-Id: I9a59fcb7cf221ae590a047c520e7aff99e23ecf1
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/lib/stack.c |    5 +++--
+ src/lib/stack.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)
 
 diff --git a/src/lib/stack.c b/src/lib/stack.c
@@ -32,5 +34,5 @@ index 52dd723..bebeea2 100644
  		return -1;
  	}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0034-cpu-x86-lapic-Add-stack-overrun-detection.patch b/resources/libreboot/patch/kgpe-d16/0030-cpu-x86-lapic-Add-stack-overrun-detection.patch
index 56ee3b5..5defeab 100644
--- a/resources/libreboot/patch/kgpe-d16/0034-cpu-x86-lapic-Add-stack-overrun-detection.patch
+++ b/resources/libreboot/patch/kgpe-d16/0030-cpu-x86-lapic-Add-stack-overrun-detection.patch
@@ -1,10 +1,12 @@
-From 1539fd430edf754b165301386b121f95c9b60791 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From e30acf3fb35f09d788f29f9603124bcbc24723fb Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 19:31:20 -0500
-Subject: [PATCH 034/146] cpu/x86/lapic: Add stack overrun detection
+Subject: [PATCH 030/139] cpu/x86/lapic: Add stack overrun detection
 
+Change-Id: I03e43f38e0d2e51141208ebb169ad8deba77ab78
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/x86/lapic/lapic_cpu_init.c |    2 ++
+ src/cpu/x86/lapic/lapic_cpu_init.c | 2 ++
  1 file changed, 2 insertions(+)
 
 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -28,5 +30,5 @@ index 7fedd00..faa1f1f 100644
  		checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i);
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0030-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch b/resources/libreboot/patch/kgpe-d16/0030-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch
deleted file mode 100644
index baae3c5..0000000
--- a/resources/libreboot/patch/kgpe-d16/0030-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From e88253116622c39c99511cef99791bf0d8422e95 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Mon, 1 Jun 2015 02:40:24 -0500
-Subject: [PATCH 030/146] northbridge/amd/amdmct/mct_ddr3: Fix failing S3
- resume
-
----
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |   14 +++++++++++---
- 1 file changed, 11 insertions(+), 3 deletions(-)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index 2ea7dc1..98b533b 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-@@ -604,7 +604,9 @@ int8_t save_mct_information_to_nvram(void)
- int8_t restore_mct_information_from_nvram(void)
- {
- 	ssize_t s3nv_offset;
--	struct amd_s3_persistent_data persistent_data;
-+	struct amd_s3_persistent_data *persistent_data;
-+	struct cbfs_media default_media;
-+	struct cbfs_media* media = CBFS_DEFAULT_MEDIA;
- 
- 	/* Obtain CBFS file offset */
- 	s3nv_offset = get_s3nv_file_offset();
-@@ -615,8 +617,14 @@ int8_t restore_mct_information_from_nvram(void)
- 	s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1);
- 	s3nv_offset += CONFIG_S3_DATA_SIZE;
- 
--	cbfs_read(CBFS_DEFAULT_MEDIA, &persistent_data, s3nv_offset, sizeof(struct amd_s3_persistent_data));
--	restore_mct_data_from_save_variable(&persistent_data);
-+	/* Map data structure in CBFS and restore settings */
-+	if (init_backing_media(&media, &default_media))
-+		return -1;
-+
-+	media->open(media);
-+	persistent_data = media->map(media, s3nv_offset, sizeof(struct amd_s3_persistent_data));
-+	restore_mct_data_from_save_variable(persistent_data);
-+	media->close(media);
- 
- 	return 0;
- }
-\ No newline at end of file
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0031-northbridge-amd-amdmct-Fix-S3-suspend-resume-with-la.patch b/resources/libreboot/patch/kgpe-d16/0031-northbridge-amd-amdmct-Fix-S3-suspend-resume-with-la.patch
deleted file mode 100644
index 6754fc1..0000000
--- a/resources/libreboot/patch/kgpe-d16/0031-northbridge-amd-amdmct-Fix-S3-suspend-resume-with-la.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 67497b91b5d5e9d28264cbbcdfb772e40860ad09 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Tue, 2 Jun 2015 15:55:35 -0500
-Subject: [PATCH 031/146] northbridge/amd/amdmct: Fix S3 suspend/resume with
- latest CBFS changes
-
----
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |   28 ++++++++++++-------------
- 1 file changed, 14 insertions(+), 14 deletions(-)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index 98b533b..c9bcac1 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-@@ -36,17 +36,15 @@ static ssize_t get_s3nv_file_offset(void);
- 
- ssize_t get_s3nv_file_offset(void)
- {
--	struct cbfs_file file;
--	ssize_t offset;
--	struct cbfs_media *media = CBFS_DEFAULT_MEDIA;
--
--	offset = cbfs_locate_file(media, &file, S3NV_FILE_NAME);
--	if (offset < 0) {
-+	struct region_device s3nv_region;
-+	struct cbfsf s3nv_cbfs_file;
-+	if (cbfs_boot_locate(&s3nv_cbfs_file, S3NV_FILE_NAME, NULL)) {
- 		printk(BIOS_DEBUG, "S3 state file not found in CBFS: %s\n", S3NV_FILE_NAME);
- 		return -1;
- 	}
-+	cbfs_file_data(&s3nv_region, &s3nv_cbfs_file);
- 
--	return offset;
-+	return s3nv_region.region.offset;
- }
- 
- static uint32_t read_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, uint32_t index)
-@@ -604,9 +602,9 @@ int8_t save_mct_information_to_nvram(void)
- int8_t restore_mct_information_from_nvram(void)
- {
- 	ssize_t s3nv_offset;
-+	ssize_t s3nv_file_offset;
-+	void * s3nv_cbfs_file_ptr;
- 	struct amd_s3_persistent_data *persistent_data;
--	struct cbfs_media default_media;
--	struct cbfs_media* media = CBFS_DEFAULT_MEDIA;
- 
- 	/* Obtain CBFS file offset */
- 	s3nv_offset = get_s3nv_file_offset();
-@@ -614,17 +612,19 @@ int8_t restore_mct_information_from_nvram(void)
- 		return -1;
- 
- 	/* Align flash pointer to nearest boundary */
-+	s3nv_file_offset = s3nv_offset;
- 	s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1);
- 	s3nv_offset += CONFIG_S3_DATA_SIZE;
-+	s3nv_file_offset = s3nv_offset - s3nv_file_offset;
- 
- 	/* Map data structure in CBFS and restore settings */
--	if (init_backing_media(&media, &default_media))
-+	s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL);
-+	if (!s3nv_cbfs_file_ptr) {
-+		printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME);
- 		return -1;
--
--	media->open(media);
--	persistent_data = media->map(media, s3nv_offset, sizeof(struct amd_s3_persistent_data));
-+	}
-+	persistent_data = (s3nv_cbfs_file_ptr + s3nv_file_offset);
- 	restore_mct_data_from_save_variable(persistent_data);
--	media->close(media);
- 
- 	return 0;
- }
-\ No newline at end of file
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0035-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch b/resources/libreboot/patch/kgpe-d16/0031-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch
index 75fbc26..d43fab6 100644
--- a/resources/libreboot/patch/kgpe-d16/0035-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch
+++ b/resources/libreboot/patch/kgpe-d16/0031-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch
@@ -1,11 +1,13 @@
-From 6ee3b567040bc49b93eb218cded2727c098b1d5b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 7102e3001406f8eedbfbbeefafb2f27b62b47d03 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 19:30:38 -0500
-Subject: [PATCH 035/146] southbridge/amd/sr5650: Add AMD Family 15h CPU
+Subject: [PATCH 031/139] southbridge/amd/sr5650: Add AMD Family 15h CPU
  support
 
+Change-Id: I88203907270db1a268bd377151f15c24fca1efdc
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sr5650/early_setup.c |    2 ++
+ src/southbridge/amd/sr5650/early_setup.c | 2 ++
  1 file changed, 2 insertions(+)
 
 diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
@@ -22,5 +24,5 @@ index 664f60a..62b0dab 100644
  		printk(BIOS_INFO, "CPU Rev is not recognized.\n");
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0032-cpu-amd-Move-model_10xxx-to-family_10h-family_15h.patch b/resources/libreboot/patch/kgpe-d16/0032-cpu-amd-Move-model_10xxx-to-family_10h-family_15h.patch
new file mode 100644
index 0000000..a255f78
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0032-cpu-amd-Move-model_10xxx-to-family_10h-family_15h.patch
@@ -0,0 +1,7898 @@
+From 54b88ab6e8f0b5a48bf8b0df168a6d12d44b09df Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 16 Oct 2015 14:24:06 -0500
+Subject: [PATCH 032/139] cpu/amd: Move model_10xxx to family_10h-family_15h
+
+Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/Kconfig                                |    2 +-
+ src/cpu/amd/family_10h-family_15h/Kconfig          |   88 ++
+ src/cpu/amd/family_10h-family_15h/Makefile.inc     |   14 +
+ src/cpu/amd/family_10h-family_15h/defaults.h       |  479 +++++++++
+ src/cpu/amd/family_10h-family_15h/fidvid.c         | 1049 ++++++++++++++++++++
+ src/cpu/amd/family_10h-family_15h/init_cpus.c      |  968 ++++++++++++++++++
+ .../amd/family_10h-family_15h/model_10xxx_init.c   |  165 +++
+ .../amd/family_10h-family_15h/monotonic_timer.c    |   98 ++
+ src/cpu/amd/family_10h-family_15h/powernow_acpi.c  |  311 ++++++
+ src/cpu/amd/family_10h-family_15h/processor_name.c |  323 ++++++
+ src/cpu/amd/family_10h-family_15h/ram_calc.c       |   54 +
+ src/cpu/amd/family_10h-family_15h/ram_calc.h       |   25 +
+ .../amd/family_10h-family_15h/update_microcode.c   |   71 ++
+ src/cpu/amd/model_10xxx/Kconfig                    |   88 --
+ src/cpu/amd/model_10xxx/Makefile.inc               |   14 -
+ src/cpu/amd/model_10xxx/defaults.h                 |  479 ---------
+ src/cpu/amd/model_10xxx/fidvid.c                   | 1049 --------------------
+ src/cpu/amd/model_10xxx/init_cpus.c                |  968 ------------------
+ src/cpu/amd/model_10xxx/model_10xxx_init.c         |  165 ---
+ src/cpu/amd/model_10xxx/monotonic_timer.c          |   98 --
+ src/cpu/amd/model_10xxx/powernow_acpi.c            |  311 ------
+ src/cpu/amd/model_10xxx/processor_name.c           |  323 ------
+ src/cpu/amd/model_10xxx/ram_calc.c                 |   54 -
+ src/cpu/amd/model_10xxx/ram_calc.h                 |   25 -
+ src/cpu/amd/model_10xxx/update_microcode.c         |   71 --
+ src/cpu/amd/socket_AM2r2/Makefile.inc              |    2 +-
+ src/cpu/amd/socket_AM3/Makefile.inc                |    2 +-
+ src/cpu/amd/socket_ASB2/Makefile.inc               |    2 +-
+ src/cpu/amd/socket_C32/Makefile.inc                |    2 +-
+ src/cpu/amd/socket_F_1207/Makefile.inc             |    2 +-
+ src/cpu/amd/socket_G34/Makefile.inc                |    2 +-
+ src/mainboard/advansus/a785e-i/romstage.c          |    2 +-
+ src/mainboard/amd/bimini_fam10/romstage.c          |    2 +-
+ src/mainboard/amd/mahogany_fam10/romstage.c        |    2 +-
+ .../amd/serengeti_cheetah_fam10/romstage.c         |    2 +-
+ src/mainboard/amd/tilapia_fam10/romstage.c         |    2 +-
+ src/mainboard/asus/kfsn4-dre/romstage.c            |    2 +-
+ src/mainboard/asus/kgpe-d16/romstage.c             |    2 +-
+ src/mainboard/asus/m4a78-em/romstage.c             |    2 +-
+ src/mainboard/asus/m4a785-m/romstage.c             |    2 +-
+ src/mainboard/asus/m5a88-v/romstage.c              |    2 +-
+ src/mainboard/avalue/eax-785e/romstage.c           |    2 +-
+ src/mainboard/gigabyte/ma785gm/romstage.c          |    2 +-
+ src/mainboard/gigabyte/ma785gmt/romstage.c         |    2 +-
+ src/mainboard/gigabyte/ma78gm/romstage.c           |    2 +-
+ src/mainboard/hp/dl165_g6_fam10/romstage.c         |    2 +-
+ src/mainboard/iei/kino-780am2-fam10/romstage.c     |    2 +-
+ src/mainboard/jetway/pa78vm5/romstage.c            |    2 +-
+ src/mainboard/msi/ms9652_fam10/romstage.c          |    2 +-
+ src/mainboard/supermicro/h8dmr_fam10/romstage.c    |    2 +-
+ src/mainboard/supermicro/h8qme_fam10/romstage.c    |    2 +-
+ src/mainboard/supermicro/h8scm_fam10/romstage.c    |    2 +-
+ src/mainboard/tyan/s2912_fam10/romstage.c          |    2 +-
+ src/northbridge/amd/amdfam10/northbridge.c         |    2 +-
+ 54 files changed, 3675 insertions(+), 3675 deletions(-)
+ create mode 100644 src/cpu/amd/family_10h-family_15h/Kconfig
+ create mode 100644 src/cpu/amd/family_10h-family_15h/Makefile.inc
+ create mode 100644 src/cpu/amd/family_10h-family_15h/defaults.h
+ create mode 100644 src/cpu/amd/family_10h-family_15h/fidvid.c
+ create mode 100644 src/cpu/amd/family_10h-family_15h/init_cpus.c
+ create mode 100644 src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+ create mode 100644 src/cpu/amd/family_10h-family_15h/monotonic_timer.c
+ create mode 100644 src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+ create mode 100644 src/cpu/amd/family_10h-family_15h/processor_name.c
+ create mode 100644 src/cpu/amd/family_10h-family_15h/ram_calc.c
+ create mode 100644 src/cpu/amd/family_10h-family_15h/ram_calc.h
+ create mode 100644 src/cpu/amd/family_10h-family_15h/update_microcode.c
+ delete mode 100644 src/cpu/amd/model_10xxx/Kconfig
+ delete mode 100644 src/cpu/amd/model_10xxx/Makefile.inc
+ delete mode 100644 src/cpu/amd/model_10xxx/defaults.h
+ delete mode 100644 src/cpu/amd/model_10xxx/fidvid.c
+ delete mode 100644 src/cpu/amd/model_10xxx/init_cpus.c
+ delete mode 100644 src/cpu/amd/model_10xxx/model_10xxx_init.c
+ delete mode 100644 src/cpu/amd/model_10xxx/monotonic_timer.c
+ delete mode 100644 src/cpu/amd/model_10xxx/powernow_acpi.c
+ delete mode 100644 src/cpu/amd/model_10xxx/processor_name.c
+ delete mode 100644 src/cpu/amd/model_10xxx/ram_calc.c
+ delete mode 100644 src/cpu/amd/model_10xxx/ram_calc.h
+ delete mode 100644 src/cpu/amd/model_10xxx/update_microcode.c
+
+diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
+index 3a02043..8abc984 100644
+--- a/src/cpu/amd/Kconfig
++++ b/src/cpu/amd/Kconfig
+@@ -12,7 +12,7 @@ source src/cpu/amd/socket_F_1207/Kconfig
+ source src/cpu/amd/socket_S1G1/Kconfig
+ 
+ source src/cpu/amd/model_fxx/Kconfig
+-source src/cpu/amd/model_10xxx/Kconfig
++source src/cpu/amd/family_10h-family_15h/Kconfig
+ source src/cpu/amd/geode_gx2/Kconfig
+ source src/cpu/amd/geode_lx/Kconfig
+ 
+diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
+new file mode 100644
+index 0000000..7c47e27
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/Kconfig
+@@ -0,0 +1,88 @@
++config CPU_AMD_MODEL_10XXX
++	bool
++	select ARCH_BOOTBLOCK_X86_32
++	select ARCH_VERSTAGE_X86_32
++	select ARCH_ROMSTAGE_X86_32
++	select ARCH_RAMSTAGE_X86_32
++	select SSE
++	select SSE2
++	select MMCONF_SUPPORT_DEFAULT
++	select TSC_SYNC_LFENCE
++	select UDELAY_LAPIC
++	select HAVE_MONOTONIC_TIMER
++	select SUPPORT_CPU_UCODE_IN_CBFS
++	select CPU_MICROCODE_MULTIPLE_FILES
++
++if CPU_AMD_MODEL_10XXX
++
++config NUM_IPI_STARTS
++	int
++	default 1
++
++config CPU_ADDR_BITS
++	int
++	default 48
++
++config DCACHE_RAM_BASE
++	hex
++	default 0xc4000
++
++config DCACHE_RAM_SIZE
++	hex
++	default 0x0c000
++
++config DCACHE_BSP_STACK_SIZE
++	hex
++	default 0x2000
++
++config DCACHE_BSP_STACK_SLUSH
++	hex
++	default 0x1000
++
++config DCACHE_AP_STACK_SIZE
++	hex
++	default 0x400
++
++config UDELAY_IO
++	bool
++	default n
++
++config SET_FIDVID
++	bool
++	default y
++
++config MAX_PHYSICAL_CPUS
++	int
++	default 1
++
++config LIFT_BSP_APIC_ID
++	bool
++	default n
++
++if SET_FIDVID
++config SET_FIDVID_DEBUG
++	bool
++	default y
++
++config SET_FIDVID_STORE_AP_APICID_AT_FIRST
++	bool
++	default y
++
++config SET_FIDVID_CORE0_ONLY
++	bool
++	default n
++
++# 0: all cores
++# 1: core 0 only
++# 2: all but core 0
++config SET_FIDVID_CORE_RANGE
++	int
++	default 0
++
++endif	# SET_FIDVID
++
++config UDELAY_LAPIC_FIXED_FSB
++	int
++	default 200
++
++endif	# CPU_AMD_MODEL_10XXX
+diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
+new file mode 100644
+index 0000000..5a81ab8
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
+@@ -0,0 +1,14 @@
++romstage-y += ../../x86/mtrr/earlymtrr.c
++ramstage-y += model_10xxx_init.c
++ramstage-y += processor_name.c
++
++romstage-y += update_microcode.c
++romstage-y += ram_calc.c
++ramstage-y += ram_calc.c
++ramstage-y += monotonic_timer.c
++ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
++
++# Microcode for Family 10h, 11h, 12h, and 14h
++cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
++microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
++microcode_amd.bin-type := microcode
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
+new file mode 100644
+index 0000000..6fd1a7e
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
+@@ -0,0 +1,479 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2008 Advanced Micro Devices, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#include <northbridge/amd/amdmct/amddefs.h>
++#include <cpu/amd/mtrr.h>
++
++/*
++ * Default MSR and errata settings.
++ */
++static const struct {
++	u32 msr;
++	u32 revision;
++	u32 platform;
++	u32 data_lo;
++	u32 data_hi;
++	u32 mask_lo;
++	u32 mask_hi;
++} fam10_msr_default[] = {
++	{ TOP_MEM2, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000000,
++	  0xFFFFFFFF, 0xFFFFFFFF },
++
++	{ SYSCFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  3 << 21, 0x00000000,
++	  3 << 21, 0x00000000 },	/* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
++
++	{ HWCR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  1 << 4, 0x00000000,
++	  1 << 4, 0x00000000 },		/* [INVD_WBINVD]=1 */
++
++	{ MC4_CTL_MASK, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0xF << 19, 0x00000000,
++	  0xF << 19, 0x00000000 },	/* [RtryHt[0..3]]=1 */
++
++	{ DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR,
++	  0x00000000, 0x00000004,
++	  0x00000000, 0x0000000C },	/* [REQ_CTR] = 1 for Server */
++
++	{ DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR,
++	  0x00000000, 0x00000000,
++	  0x00000000, 0x00000C00 },	/* Erratum 326 */
++
++	{ NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
++	  0x00000000, 1 << 22,
++	  0x00000000, 1 << 22 },	/* [ApicInitIDLo]=1 */
++
++	{ BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL,
++	  1 << 29, 0x00000000,
++	  1 << 29, 0x00000000 },	/* For Bx Smash1GPages=1 */
++
++	{ DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  1 << 24, 0x00000000,
++	  1 << 24, 0x00000000 },	/* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
++
++	{ LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
++	  0 << 1, 0x00000000,
++	  1 << 1, 0x00000000 },		/* IDX_MATCH_ALL=0 */
++
++	{ BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
++	  1 << 21, 0x00000000,
++	  1 << 21, 0x00000000 },	/* Erratum #254 DR B1 BU_CFG[21]=1 */
++
++	{ BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
++	  1 << 23, 0x00000000,
++	  1 << 23, 0x00000000 },	/* Erratum #309 BU_CFG[23]=1 */
++
++	/* CPUID_EXT_FEATURES */
++	{ CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
++	  1 << 28, 0x00000000,
++	  1 << 28, 0x00000000 },	/* [HyperThreadFeatEn]=1 */
++
++	{ CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC,
++	  0x00000000, 1 << (33-32),
++	  0x00000000, 1 << (33-32) },	/* [ExtendedFeatEn]=1 */
++
++	{ BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
++	  0x00000000, 1 << (35-32),
++	  0x00000000, 1 << (35-32) },	/* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */
++
++	{ OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
++	  0x00000004, 0x00000000,
++	  0x00000004, 0x00000000},	/* B0 or Above, OSVW_ID_Length is 0004h */
++
++	{ OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
++	  0x0000000C, 0x00000000,
++	  0x0000000C, 0x00000000},	/* Cx and Dx multiple-link processor */
++
++	{ BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL,
++	  0x00000000, 1 << (50-32),
++	  0x00000000, 1 << (50-32)},	/* D0 or Above, RdMmExtCfgQwEn*/
++
++	{ CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
++	  0x00000000, 1 << (51 - 32),
++	  0x00000000, 1 << (51 - 32)},	/* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
++};
++
++
++/*
++ * Default PCI and errata settings.
++ */
++static const struct {
++	u8  function;
++	u16 offset;
++	u32 revision;
++	u32 platform;
++	u32 data;
++	u32 mask;
++} fam10_pci_default[] = {
++
++	/* Function 0 - HT Config */
++
++	{ 0, 0x68, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x004E4800, 0x006E6800 },	/* [19:17] for 8bit APIC config,
++	  [14:13] BufPriRel = 2h [11] RspPassPW set,
++	  [22:21] DsNpReqLmt = 10b */
++
++	/* Errata 281 Workaround */
++	{ 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
++	  AMD_PTYPE_SVR, 0x00200000, 0x00600000 },	/* [22:21] DsNpReqLmt0 = 01b */
++
++	{ 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	/* Link Global Retry Control Register */
++	{ 0, 0x150, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00073900, 0x00073F00 },
++
++	/*  Errata 351
++	 * System software should program the Link Extended Control Registers[LS2En]
++	 * (F0x[18C:170][8]) to 0b for all links. System software should also
++	 * program Link Global Extended Control Register[ForceFullT0]
++	 * (F0x16C[15:13]) to 000b */
++
++	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
++	  0x00000000, 0x00000100 },
++	{ 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++	{ 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++	{ 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++	{ 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++	{ 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++	{ 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++	{ 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00000100 },
++
++	/* Link Global Extended Control Register */
++	{ 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000014, 0x0000003F },	/* [15:13] ForceFullT0 = 0b,
++								 * Set T0Time 14h per BKDG */
++
++
++	/* Function 1 - Map Init */
++
++	/* Before reading F1x114_x2 or F1x114_x3 software must
++	 * initialize the registers or NB Array MCA errors may
++	 * occur.  BIOS should initialize index 0h of F1x114_x2 and
++	 * F1x114_x3 to prevent reads from F1x114 from generating NB
++	 * Array MCA errors.  BKDG Doc #3116 Rev 1.07
++	 */
++
++	{ 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x20000000, 0xFFFFFFFF },	/* Select extended MMIO Base */
++
++	{ 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0xFFFFFFFF },	/* Clear map  */
++
++	{ 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x30000000, 0xFFFFFFFF },	/* Select extended MMIO Base */
++
++	{ 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0xFFFFFFFF },	/* Clear map  */
++
++	/* Function 2 - DRAM Controller */
++
++	/* Function 3 - Misc. Control */
++	{ 3, 0x40, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000100, 0x00000100 },	/* [8] MstrAbrtEn */
++
++	{ 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x4A30005C, 0x4A30005C },	/* [30] SyncOnDramAdrParErrEn = 1,
++					   [27] NbMcaToMstCpuEn = 1,
++					   [25] DisPciCfgCpuErrRsp = 1,
++					   [21] SyncOnAnyErrEn = 1,
++					   [20] SyncOnWDTEn = 1,
++					   [6] CpuErrDis = 1,
++					   [4] SyncPktPropDis = 1,
++					   [3] SyncPktGenDis = 1,
++					   [2] SyncOnUcEccEn = 1 */
++
++	/* XBAR buffer settings */
++	{ 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00018052, 0x700780F7 },
++
++	/* Errata 281 Workaround */
++	{ 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1),
++	  AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
++
++	{ 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
++	  0x60018051, 0x700780F7 },
++
++	{ 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00041153, 0x777777F7 },
++
++	{ 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
++	  0x61221151, 0x777777F7 },
++
++	{ 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
++	  0x00080101, 0x000F7777 },
++
++	{ 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00090914, 0x707FFF1F },
++
++	/* Errata 281 Workaround */
++	{ 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
++	 AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
++
++	{ 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
++	  0x00070814, 0x007FFF1F },
++
++	{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00800756, 0x00F3FFFF },
++
++	{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
++	  0x00C37756, 0x00F3FFFF },
++
++	{ 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
++	  0x00000036, 0x000000FF },
++
++	/* Errata 281 Workaround */
++	{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
++	 AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
++	 	/* [3:0] RspTok = 0001b */
++
++	{ 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
++	  0x8000052A, 0xD5FFFFFF },
++
++	/* ACPI Power State Control Reg1 */
++	{ 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0xE6002200, 0xFFFFFFFF },
++
++	/* ACPI Power State Control Reg2 */
++	{ 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0xA0E641E6, 0xFFFFFFFF },
++
++	{ 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
++	  0x00000080, 0x00000080 },	/* [7] PSIVidEnable */
++
++	{ 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
++	  0x00002800, 0x000003800 },	/* [13:11] PllLockTime = 5 */
++
++	{ 3, 0xA0, (AMD_FAM10_ALL & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
++	  0x00000800, 0x000003800 },	/* [13:11] PllLockTime = 1 */
++
++	/* Reported Temp Control Register */
++	{ 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000080, 0x00000080 },	/* [7] TempSlewDnEn = 1 */
++
++	/* Clock Power/Timing Control 0 Register */
++	{ 3, 0xD4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0xC0000F00, 0xF0000F00 },	/*  [31] NbClkDivApplyAll = 1,
++		[30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
++
++	/* Clock Power/Timing Control 1 Register */
++	{ 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x03000016, 0x0F000077 },	/* [6:4] VSRampTime = 1,
++		[2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */
++
++
++	/* Clock Power/Timing Control 2 Register */
++	{ 3, 0xDC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00005000, 0x00007000 },	/* [14:12] NbsynPtrAdj = 5 */
++
++
++	/* Extended NB MCA Config Register */
++	{ 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x007003E2, 0x007003E2 },	/* [22:20] = SyncFloodOn_Err = 7,
++					   [9] SyncOnUncNbAryEn = 1 ,
++					   [8] SyncOnProtEn = 1,
++					   [7] SyncFloodOnTgtAbtErr = 1,
++					   [6] SyncFloodOnDatErr = 1,
++					   [5] DisPciCfgCpuMstAbtRsp = 1,
++					   [1] SyncFloodOnUsPwDataErr = 1 */
++
++	/* errata 346 - Fam10 C2, C3
++	 *  System software should set F3x188[22] to 1b. */
++	{ 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
++	  0x00400000, 0x00400000 },
++
++	/* L3 Control Register */
++	{ 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00001000, 0x00001000 },	/* [12] = L3PrivReplEn */
++
++	/* IBS Control Register */
++	{ 3, 0x1CC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
++	  0x00000100, 0x00000100 },	/* [8] = LvtOffsetVal */
++};
++
++
++/*
++ * Default HyperTransport Phy and errata settings.
++ */
++static const struct {
++	u16 htreg;	/* HT Phy Register index */
++	u32 revision;
++	u32 platform;
++	u32 linktype;
++	u32 data;
++	u32 mask;
++} fam10_htphy_default[] = {
++
++	/* Errata 344 - Fam10 C2/C3, D0/D1
++	 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
++	{ 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++
++	{ 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++
++	/* Errata 354 - Fam10 C2, C3
++	 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
++	{ 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++
++	{ 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++	{ 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00000040, 0x00000040 },
++
++	/* Errata 327 - Fam10 C2/C3, D0/D1
++	 * BIOS should set the Link Phy Impedance Register[RttCtl]
++	 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
++	 * Link Phy Impedance Register[RttIndex]
++	 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
++	{ 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x40040000, 0xe01F0000 },
++	{ 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x40040000, 0xe01F0000 },
++
++	{ 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00004000, 0x00006000 },	/* HT_PHY_DLL_REG */
++
++	{ 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00004000, 0x00006000 },	/* HT_PHY_DLL_REG */
++
++	{ 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00004400, 0x00006400 },	/* HT_PHY_DLL_REG */
++
++	{ 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x00004400, 0x00006400 },	/* HT_PHY_DLL_REG */
++
++	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
++					   completeness */
++
++	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
++					   completeness */
++
++	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	  0x0000006D, 0x000000FF },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
++
++	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
++	  0x0000006D, 0x000000FF }, 	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
++
++	/* Link Phy Receiver Loop Filter Registers */
++	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
++					   [21:14] LfcMin = 10h */
++
++	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
++					   [21:14] LfcMin = 10h */
++
++	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
++					   [21:14] LfcMin = 08h */
++
++	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
++					   [21:14] LfcMin = 08h */
++
++	{ 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
++								   [20:16] RttIndex = 04h */
++};
+diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
+new file mode 100644
+index 0000000..99ffcc8
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
+@@ -0,0 +1,1049 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2007 Advanced Micro Devices, Inc.
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++/*
++ * This file initializes the CPU cores for voltage and frequency settings
++ * in the different power states.
++ */
++/*
++
++checklist (functions are in this file if no source file named)
++Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
++
++2.4.2.6 Requirements for p-states
++
++1.- F3x[84:80] According to table 100 : prep_fid_change
++
++2.- COF/VID :
++     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
++               fixPsNbVidBeforeWR(...)
++     2.4.2.9.1 Step 8 enable_fid_change
++               We do this for all nodes, I don't understand BKDG 100% on
++               whether this is or isn't meant by "on the local
++               processor". Must be OK.
++     2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
++     2.4.2.9.1 Steps 11-12 init_fidvid_stage2
++     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
++               needs specific circuitry.
++
++3.-  2.4.2.7 dualPlaneOnly(dev)
++
++4.-  2.4.2.8 applyBoostFIDOffset(dev)
++
++5.-  enableNbPState1(dev)
++
++6.- 2.4.1.7
++    a) UpdateSinglePlaneNbVid()
++    b) setVSRamp(), called from  prep_fid_change
++    c) prep_fid_change
++    d) improperly, for lack of voltage regulator details?,
++        F3xA0[PsiVidEn] in defaults.h
++        F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
++
++7.- TODO (Core Performance Boost is only available in revision E cpus, and we
++          don't seem to support those yet, at least they don't have any
++          constant in amddefs.h )
++
++8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
++    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
++    if the warm reset is issued by coreboot to update NbFid. So it is required
++    or not ? How can I tell who issued warm reset ?
++    Coreboot transitions to P0 instead, which is not recommended, and does
++    not follow 2.4.2.15.2 to do so.
++
++9.- TODO Requires information on current delivery capability
++    (depends on mainboard and maybe power supply ?). One might use a config
++    option with the maximum number of Amperes that the board can deliver to CPU.
++
++10.- [Multiprocessor] TODO 2.4.2.12
++     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
++     but not sure this is what is meant by "Determine the valid set of
++     P-states based on enabled P-states indicated
++     in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
++
++11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
++
++12.- generate ACPI for p-states.
++     generated in powernow_acpi.c amd_generate_powernow()
++
++"must also be completed"
++
++a.-  PllLockTime set in ruleset in defaults.h
++     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
++     any two enabled P-states", but since it does not say "only if"
++     I guess it is safe to do it always.
++
++b.-  prep_fid_change(...)
++
++ */
++
++#if CONFIG_SET_FIDVID
++
++#include <northbridge/amd/amdht/AsPsDefs.h>
++
++static inline void print_debug_fv(const char *str, u32 val)
++{
++#if CONFIG_SET_FIDVID_DEBUG
++	printk(BIOS_DEBUG, "%s%x\n", str, val);
++#endif
++}
++
++static inline void print_debug_fv_8(const char *str, u8 val)
++{
++#if CONFIG_SET_FIDVID_DEBUG
++	printk(BIOS_DEBUG, "%s%02x\n", str, val);
++#endif
++}
++
++static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
++{
++#if CONFIG_SET_FIDVID_DEBUG
++	printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
++#endif
++}
++
++struct fidvid_st {
++	u32 common_fid;
++};
++
++static void enable_fid_change(u8 fid)
++{
++	u32 dword;
++	u32 nodes;
++	device_t dev;
++	int i;
++
++	nodes = get_nodes();
++
++	for (i = 0; i < nodes; i++) {
++		dev = NODE_PCI(i, 3);
++		dword = pci_read_config32(dev, 0xd4);
++		dword &= ~0x1F;
++		dword |= (u32) fid & 0x1F;
++		dword |= 1 << 5;	// enable
++		pci_write_config32(dev, 0xd4, dword);
++		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
++		       dword);
++	}
++}
++
++static void applyBoostFIDOffset(  device_t dev ) {
++  // BKDG 2.4.2.8
++  // revision E only, but E is apparently not supported yet, therefore untested
++  if ((cpuid_edx(0x80000007) & CPB_MASK)
++      &&  ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) {
++      u32 core =  get_node_core_id_x().coreid;
++      u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
++      msr_t msr =  rdmsr(PS_REG_BASE);
++      u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
++      cpuFid = cpuFid + asymetricBoostThisCore;
++      msr.lo &=   ~PS_CPU_FID_MASK;
++      msr.lo |= cpuFid ;
++      wrmsr(PS_REG_BASE , msr);
++
++  }
++}
++
++static void enableNbPState1( device_t dev ) {
++  u32 cpuRev =  mctGetLogicalCPUID(0xFF);
++  if (cpuRev & AMD_FAM10_C3) {
++    u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
++    if ( nbPState){
++      u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
++      u32 i;
++      for (i = nbPState; i < NM_PS_REG; i++) {
++         msr_t msr =  rdmsr(PS_REG_BASE + i);
++         if (msr.hi &  PS_EN_MASK ) {
++            msr.hi |= NB_DID_M_ON;
++            msr.lo &= NB_VID_MASK_OFF;
++	    msr.lo |= ( nbVid1 << NB_VID_POS);
++	    wrmsr(PS_REG_BASE + i, msr);
++	 }
++      }
++    }
++  }
++}
++
++static u8 setPStateMaxVal( device_t dev ) {
++      u8 i,maxpstate=0;
++      for (i = 0; i < NM_PS_REG; i++) {
++         msr_t msr =  rdmsr(PS_REG_BASE + i);
++         if (msr.hi & PS_IDD_VALUE_MASK) {
++	   msr.hi |= PS_EN_MASK ;
++	     wrmsr(PS_REG_BASE + i, msr);
++	 }
++         if (msr.hi & PS_EN_MASK) {
++	   maxpstate = i;
++	 }
++      }
++      //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
++      u32 reg = pci_read_config32(dev, CPTC2);
++      reg &= PS_MAX_VAL_MASK;
++      reg |= (maxpstate << PS_MAX_VAL_POS);
++      pci_write_config32(dev, CPTC2,reg);
++      return maxpstate;
++}
++
++static void dualPlaneOnly(  device_t dev ) {
++  // BKDG 2.4.2.7
++
++  u32 cpuRev =  mctGetLogicalCPUID(0xFF);
++  if ((mctGetProcessorPackageType() ==  AMD_PKGTYPE_AM3_2r2)
++      && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E
++    if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK)
++	 && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){
++      if (cpuid_edx(0x80000007) & CPB_MASK) {
++          // revision E only, but E is apparently not supported yet, therefore untested
++         msr_t minPstate = rdmsr(0xC0010065);
++         wrmsr(0xC0010065, rdmsr(0xC0010068) );
++         wrmsr(0xC0010068,minPstate);
++      } else {
++	 msr_t msr;
++         msr.lo=0; msr.hi=0;
++         wrmsr(0xC0010064, rdmsr(0xC0010068) );
++         wrmsr(0xC0010068, msr );
++      }
++
++      //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
++      u8 maxpstate = setPStateMaxVal(dev);
++
++      u32 reg = pci_read_config32(dev, HTC_REG);
++      reg &= HTC_PS_LMT_MASK;
++      reg |= (maxpstate << PS_LIMIT_POS);
++      pci_write_config32(dev, HTC_REG,reg);
++
++    }
++  }
++}
++
++static int vidTo100uV(u8 vid)
++{// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV
++ // BKDG #31116 rev 3.48 2.4.1.6
++  int voltage;
++  if (vid >= 0x7c) {
++    voltage = 0;
++  } else {
++    voltage = (15500 - (125*vid));
++  }
++  return voltage;
++}
++
++static void setVSRamp(device_t dev) {
++	/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSRampTime]
++         * If this field accepts 8 values between 10 and 500 us why
++         * does page 324 say "BIOS should set this field to 001b."
++         * (20 us) ?
++         * Shouldn't it depend on the voltage regulators, mainboard
++         * or something ?
++         */
++        u32 dword;
++	dword = pci_read_config32(dev, 0xd8);
++	dword &= VSRAMP_MASK;
++	dword |= VSRAMP_VALUE;
++	pci_write_config32(dev, 0xd8, dword);
++}
++
++static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
++{
++	u8 pviModeFlag;
++	u8 highVoltageVid, lowVoltageVid, bValue;
++	u16 minimumSlamTime;
++	u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 };	/* Reg settings scaled by 100 */
++	u32 dtemp;
++	msr_t msr;
++
++	/* This function calculates the VsSlamTime using the range of possible
++	 * voltages instead of a hardcoded 200us.
++         * Note: his function is called only from prep_fid_change,
++         * and that from init_cpus.c finalize_node_setup()
++         * (after set AMD MSRs and init ht )
++	 */
++
++        /* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSSlamTime] */
++	/* Calculate Slam Time
++	 * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV
++	 * In our case, we will scale the values by 100 to avoid
++	 * decimals.
++	 */
++
++	/* Determine if this is a PVI or SVI system */
++	dtemp = pci_read_config32(dev, 0xA0);
++
++	if (dtemp & PVI_MODE)
++		pviModeFlag = 1;
++	else
++		pviModeFlag = 0;
++
++	/* Get P0's voltage */
++        /* MSRC001_00[68:64] are not programmed yet when called from
++	   prep_fid_change, one might use F4x1[F0:E0] instead, but
++	   theoretically MSRC001_00[68:64] are equal to them after
++	   reset. */
++	msr = rdmsr(0xC0010064);
++	highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
++        if (!(msr.hi & 0x80000000)) {
++  	    printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");
++            highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0)
++                                     >> PS_CPU_VID_SHFT) & 0x7F);
++	}
++
++	/* If SVI, we only care about CPU VID.
++	 * If PVI, determine the higher voltage b/t NB and CPU
++	 */
++	if (pviModeFlag) {
++		bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
++		if (highVoltageVid > bValue)
++			highVoltageVid = bValue;
++	}
++
++	/* Get PSmax's index */
++	msr = rdmsr(0xC0010061);
++	bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
++
++	/* Get PSmax's VID */
++	msr = rdmsr(0xC0010064 + bValue);
++	lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
++        if (!(msr.hi & 0x80000000)) {
++	    printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue);
++            lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4))
++                                     >> PS_CPU_VID_SHFT) & 0x7F);
++	}
++
++	/* If SVI, we only care about CPU VID.
++	 * If PVI, determine the higher voltage b/t NB and CPU
++         * BKDG 2.4.1.7 (a)
++ 	 */
++	if (pviModeFlag) {
++		bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
++		if (lowVoltageVid > bValue)
++			lowVoltageVid = bValue;
++	}
++
++	/* Get AltVID */
++	dtemp = pci_read_config32(dev, 0xDC);
++	bValue = (u8) (dtemp & BIT_MASK_7);
++
++	/* Use the VID with the lowest voltage (higher VID) */
++	if (lowVoltageVid < bValue)
++		lowVoltageVid = bValue;
++
++        u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB;
++	minimumSlamTime =  (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */
++
++
++	/* Now round up to nearest register setting.
++	 * Note that if we don't find a value, we
++	 * will fall through to a value of 7
++	 */
++	for (bValue = 0; bValue < 7; bValue++) {
++		if (minimumSlamTime <= vSlamTimes[bValue])
++			break;
++	}
++
++	/* Apply the value */
++	dtemp = pci_read_config32(dev, 0xD8);
++	dtemp &= VSSLAM_MASK;
++	dtemp |= bValue;
++	pci_write_config32(dev, 0xd8, dtemp);
++}
++
++static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
++        u8 link0isGen3 = 0;
++        u8 offset;
++        if (AMD_CpuFindCapability(node, 0, &offset)) {
++	  link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
++	}
++        /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
++           S1g3 in link Gen3 mode, but I don't know how to tell
++           package S1g3 from S1g4 */
++	if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
++           && link0isGen3) {
++	  return 5 ; /* divide clk by 128*/
++        } else {
++	  return 4 ; /* divide clk by 16 */
++        }
++}
++
++
++static u32 power_up_down(int node, u8 procPkg) {
++       u32 dword=0;
++        /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
++        u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2)
++                             || (procPkg == AMD_PKGTYPE_S1gX)
++                             || (procPkg == AMD_PKGTYPE_ASB2));
++
++        if (singleLinkFlag) {
++	  /*
++           * PowerStepUp=01000b - 50nS
++	   * PowerStepDown=01000b - 50ns
++	   */
++	  dword |= PW_STP_UP50 | PW_STP_DN50;
++	} else {
++          u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
++          u32 isocEn = 0;
++          int j;
++	  for(j=0 ; (j<4) && (!isocEn) ; j++ ) {
++	    u8 offset;
++	    if (AMD_CpuFindCapability(node, j, &offset)) {
++	      isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
++	    }
++          }
++
++          if (dispRefModeEn || isocEn) {
++        	dword |= PW_STP_UP50 | PW_STP_DN50 ;
++          } else {
++		/* get number of cores for PowerStepUp & PowerStepDown in server
++		   1 core - 400nS  - 0000b
++		   2 cores - 200nS - 0010b
++		   3 cores - 133nS -> 100nS - 0011b
++		   4 cores - 100nS - 0011b
++		 */
++		switch (get_core_num_in_bsp(node)) {
++		case 0:
++			dword |= PW_STP_UP400 | PW_STP_DN400;
++			break;
++		case 1:
++		case 2:
++			dword |= PW_STP_UP200 | PW_STP_DN200;
++			break;
++		case 3:
++			dword |= PW_STP_UP100 | PW_STP_DN100;
++			break;
++		default:
++			dword |= PW_STP_UP100 | PW_STP_DN100;
++			break;
++		}
++	  }
++	}
++        return dword;
++}
++
++static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
++       	device_t dev = NODE_PCI(node, 3);
++
++	/* Program fields in Clock Power/Control register0 (F3xD4) */
++
++	/* set F3xD4 Clock Power/Timing Control 0 Register
++	 * NbClkDidApplyAll=1b
++	 * NbClkDid=100b or 101b
++	 * PowerStepUp= "platform dependent"
++	 * PowerStepDown= "platform dependent"
++	 * LinkPllLink=01b
++	 * ClkRampHystCtl=HW default
++         * ClkRampHystSel=1111b
++	 */
++        u32 dword= pci_read_config32(dev, 0xd4);
++	dword &= CPTC0_MASK;
++        dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL;
++        dword |= (nb_clk_did(node,cpuRev,procPkg) <<  NB_CLKDID_SHIFT);
++
++        dword |= power_up_down(node, procPkg);
++
++	pci_write_config32(dev, 0xd4, dword);
++
++}
++
++static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
++	/* check PVI/SVI */
++	u32 dword = pci_read_config32(dev, 0xa0);
++
++	/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xA0[VSSlamVidMod] */
++	/* PllLockTime and PsiVidEn set in ruleset in defaults.h */
++	if (dword & PVI_MODE) {	/* PVI */
++		/* set slamVidMode to 0 for PVI */
++		dword &= VID_SLAM_OFF ;
++	} else {	/* SVI */
++		/* set slamVidMode to 1 for SVI */
++		dword |= VID_SLAM_ON;
++	}
++        /* set the rest of A0 since we're at it... */
++
++	if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
++		dword |= NB_PSTATE_FORCE_ON;
++	} // else should we clear it ?
++
++
++        if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
++		dword |= BP_INS_TRI_EN_ON ;
++	}
++
++	   /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
++        #if CONFIG_SVI_HIGH_FREQ
++	if (cpuRev & AMD_FAM10_C3) {
++		dword |= SVI_HIGH_FREQ_ON;
++	}
++	#endif
++	pci_write_config32(dev, 0xa0, dword);
++}
++
++static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
++	/* Note the following settings are additional from the ported
++	 * function setFidVidRegs()
++	 */
++        /* adjust FIFO between nb and core clocks to max allowed
++           values (min latency) */
++	u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK;
++        u8 nbSynPtrAdj;
++	if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) )
++	    || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0)))  {
++	  nbSynPtrAdj = 5;
++	} else {
++          nbSynPtrAdj = 6;
++	}
++
++	u32 dword = pci_read_config32(dev, 0xDc);
++        dword &= ~ NB_SYN_PTR_ADJ_MASK;
++	dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS;
++        /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */
++	pci_write_config32(dev, 0xdc, dword);
++}
++
++static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
++                /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
++        u32 dword;
++	u32 c1= 1;
++        if (cpuRev & (AMD_DR_Bx)) {
++            // will coreboot ever enable cache scrubbing ?
++            // if it does, will it be enough to check the current state
++            // or should we configure for what we'll set up later ?
++            dword = pci_read_config32(dev, 0x58);
++            u32 scrubbingCache = dword &
++	                        ( (0x1F << 16) // DCacheScrub
++		 	          | (0x1F << 8) ); // L2Scrub
++ 	    if (scrubbingCache) {
++	        c1 = 0x80;
++	    } else {
++	        c1 = 0xA0;
++	    }
++	} else { // rev C or later
++	    // same doubt as cache scrubbing: ok to check current state ?
++            dword = pci_read_config32(dev, 0xDC);
++            u32 cacheFlushOnHalt = dword & (7 << 16);
++            if (!cacheFlushOnHalt) {
++       	       c1 = 0x80;
++       	    }
++       	}
++       	dword = (c1 << 24) | (0xE641E6);
++	pci_write_config32(dev, 0x84, dword);
++
++
++        /* FIXME: BKDG Table 100 says if the link is at a Gen1
++frequency and the chipset does not support a 10us minimum LDTSTOP
++assertion time, then { If ASB2 && SVI then smaf001 = F6h else
++smaf001=87h. } else ...  I hardly know what it means or how to check
++it from here, so I bluntly assume it is false and code here the else,
++which is easier  */
++
++        u32 smaf001 = 0xE6;
++        if (cpuRev & AMD_DR_Bx ) {
++	    smaf001 = 0xA6;
++        } else {
++            #if CONFIG_SVI_HIGH_FREQ
++                if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
++		       smaf001 = 0xF6;
++                }
++            #endif
++        }
++        u32 fidvidChange = 0;
++        if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX))
++		    || (cpuRev & AMD_RB_C3) ) {
++                       fidvidChange=0x0B;
++        }
++	dword = (0xE6 << 24) | (fidvidChange << 16)
++                        | (smaf001 << 8) | 0x81;
++	pci_write_config32(dev, 0x80, dword);
++}
++
++static void prep_fid_change(void)
++{
++        u32 dword;
++	u32 nodes;
++	device_t dev;
++	int i;
++
++	/* This needs to be run before any Pstate changes are requested */
++
++	nodes = get_nodes();
++
++	for (i = 0; i < nodes; i++) {
++		printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i);
++		dev = NODE_PCI(i, 3);
++                u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
++	        u8 procPkg =  mctGetProcessorPackageType();
++
++		setVSRamp(dev);
++		/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSSlamTime] */
++		/* Figure out the value for VsSlamTime and program it */
++		recalculateVsSlamTimeSettingOnCorePre(dev);
++
++		config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
++
++                config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
++		config_nb_syn_ptr_adj(dev,cpuRev);
++
++		config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
++
++		dword = pci_read_config32(dev, 0x80);
++		printk(BIOS_DEBUG, "  F3x80: %08x\n", dword);
++		dword = pci_read_config32(dev, 0x84);
++		printk(BIOS_DEBUG, "  F3x84: %08x\n", dword);
++		dword = pci_read_config32(dev, 0xD4);
++		printk(BIOS_DEBUG, "  F3xD4: %08x\n", dword);
++		dword = pci_read_config32(dev, 0xD8);
++		printk(BIOS_DEBUG, "  F3xD8: %08x\n", dword);
++		dword = pci_read_config32(dev, 0xDC);
++		printk(BIOS_DEBUG, "  F3xDC: %08x\n", dword);
++	}
++}
++
++static void waitCurrentPstate(u32 target_pstate){
++  msr_t initial_msr = rdmsr(TSC_MSR);
++  msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
++  msr_t tsc_msr;
++  u8 timedout ;
++
++  /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
++   * P1 that is a copy of P0, therefore has the same NB DID but the
++   * TSC will count twice per tick, so we have to wait for twice the
++   * count to achieve the desired timeout. But I'm likely to
++   * misunderstand this...
++   */
++  u32 corrected_timeout = (    (pstate_msr.lo==1)
++			    && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
++                          WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT  ;
++  msr_t timeout;
++
++  timeout.lo = initial_msr.lo + corrected_timeout ;
++  timeout.hi = initial_msr.hi;
++  if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
++     timeout.hi++;
++  }
++
++  // assuming TSC ticks at 1.25 ns per tick (800 MHz)
++  do {
++      pstate_msr = rdmsr(CUR_PSTATE_MSR);
++      tsc_msr = rdmsr(TSC_MSR);
++      timedout = (tsc_msr.hi > timeout.hi)
++        	|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
++  } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
++
++  if (pstate_msr.lo != target_pstate) {
++    msr_t limit_msr = rdmsr(0xc0010061);
++    printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo);
++
++    do { // should we just go on instead ?
++      pstate_msr = rdmsr(CUR_PSTATE_MSR);
++    } while ( pstate_msr.lo != target_pstate  ) ;
++  }
++}
++
++static void set_pstate(u32 nonBoostedPState) {
++  	msr_t msr;
++
++	// Transition P0 for calling core.
++	msr = rdmsr(0xC0010062);
++
++	msr.lo = nonBoostedPState;
++	wrmsr(0xC0010062, msr);
++
++	/* Wait for P0 to set. */
++        waitCurrentPstate(nonBoostedPState);
++}
++
++
++
++
++static void UpdateSinglePlaneNbVid(void)
++{
++	u32 nbVid, cpuVid;
++	u8 i;
++	msr_t msr;
++
++	/* copy higher voltage (lower VID) of NBVID & CPUVID to both */
++	for (i = 0; i < 5; i++) {
++		msr = rdmsr(PS_REG_BASE + i);
++		nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
++		cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
++
++		if (nbVid != cpuVid) {
++			if (nbVid > cpuVid)
++				nbVid = cpuVid;
++
++			msr.lo = msr.lo & PS_BOTH_VID_OFF;
++			msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
++			msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
++			wrmsr(PS_REG_BASE + i, msr);
++		}
++	}
++}
++
++static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
++ {
++ 	msr_t msr;
++ 	u8 startup_pstate;
++
++ 	/* This function sets NbVid before the warm reset.
++ 	 *       Get StartupPstate from MSRC001_0071.
++	 *       Read Pstate register pointed by [StartupPstate].
++ 	 *       and copy its content to P0 and P1 registers.
++ 	 *       Copy newNbVid to P0[NbVid].
++ 	 *       transition to P1 on all cores,
++ 	 *       then transition to P0 on core 0.
++ 	 *       Wait for MSRC001_0063[CurPstate] = 000b on core 0.
++         * see BKDG rev 3.48  2.4.2.9.1 BIOS NB COF and VID Configuration
++         *                              for SVI and Single-Plane PVI Systems
++ 	 */
++
++ 	msr = rdmsr(0xc0010071);
++	startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
++
++	/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for
++	 * this node in P0.  Then transition to P1 for corex and P0
++	 * for core0.  These setting will be cleared by the warm reset
++	 */
++	msr = rdmsr(0xC0010064 + startup_pstate);
++	wrmsr(0xC0010065, msr);
++	wrmsr(0xC0010064, msr);
++
++        /* missing step 2 from BDKG , F3xDC[PstateMaxVal] =
++         * max(1,F3xDC[PstateMaxVal] ) because it would take
++         * synchronization between cores and we don't think
++         * PstatMaxVal is going to be 0 on cold reset anyway ?
++	 */
++        if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) {
++  	   printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
++	};
++
++	msr.lo &= ~0xFE000000;	// clear nbvid
++	msr.lo |= (newNbVid << 25);
++	wrmsr(0xC0010064, msr);
++
++	if (pviMode) { /* single plane*/
++	  UpdateSinglePlaneNbVid();
++        }
++
++	// Transition to P1 for all APs and P0 for core0.
++        set_pstate(1);
++
++	if (coreid == 0) {
++             set_pstate(0);
++ 	}
++
++	/* missing step 7 (restore PstateMax to 0 if needed) because
++	 * we skipped step 2
++	 */
++
++}
++
++static u32 needs_NB_COF_VID_update(void)
++{
++	u8 nb_cof_vid_update;
++	u8 nodes;
++	u8 i;
++
++	/* If any node has nb_cof_vid_update set all nodes need an update. */
++	nodes = get_nodes();
++	nb_cof_vid_update = 0;
++	for (i = 0; i < nodes; i++) {
++                u32 cpuRev = mctGetLogicalCPUID(i) ;
++                u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D));
++		if (nbCofVidUpdateDefined
++                    && (pci_read_config32(NODE_PCI(i, 3), 0x1FC)
++                        & NB_COF_VID_UPDATE_MASK)) {
++			nb_cof_vid_update = 1;
++			break;
++		}
++	}
++	return nb_cof_vid_update;
++}
++
++static u32 init_fidvid_core(u32 nodeid, u32 coreid)
++{
++	device_t dev;
++	u32 vid_max;
++	u32 fid_max = 0;
++	u8 nb_cof_vid_update = needs_NB_COF_VID_update();
++	u8 pvimode;
++	u32 reg1fc;
++
++	/* Steps 1-6 of BIOS NB COF and VID Configuration
++	 * for SVI and Single-Plane PVI Systems. BKDG 2.4.2.9 #31116 rev 3.48
++	 */
++
++	dev = NODE_PCI(nodeid, 3);
++	pvimode = pci_read_config32(dev, PW_CTL_MISC) & PVI_MODE;
++	reg1fc = pci_read_config32(dev, 0x1FC);
++
++	if (nb_cof_vid_update) {
++                vid_max = (reg1fc &  SINGLE_PLANE_NB_VID_MASK ) >>  SINGLE_PLANE_NB_VID_SHIFT ;
++	        fid_max = (reg1fc &  SINGLE_PLANE_NB_FID_MASK ) >>  SINGLE_PLANE_NB_FID_SHIFT ;
++
++	        if (!pvimode) { /* SVI, dual power plane */
++         		vid_max = vid_max - ((reg1fc &  DUAL_PLANE_NB_VID_OFF_MASK ) >>  DUAL_PLANE_NB_VID_SHIFT );
++			fid_max = fid_max +  ((reg1fc &  DUAL_PLANE_NB_FID_OFF_MASK ) >>  DUAL_PLANE_NB_FID_SHIFT );
++		}
++		/* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
++		fixPsNbVidBeforeWR(vid_max, coreid,dev,pvimode);
++
++		/* fid setup is handled by the BSP at the end. */
++
++	} else {	/* ! nb_cof_vid_update */
++		/* Use max values */
++		if (pvimode)
++			UpdateSinglePlaneNbVid();
++	}
++
++	return ((nb_cof_vid_update << 16) | (fid_max << 8));
++
++}
++
++static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
++{
++	u32 send;
++
++	printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
++
++        send = init_fidvid_core(nodeid,coreid);
++	send |= (apicid << 24);	// ap apicid
++
++	// Send signal to BSP about this AP max fid
++	// This also indicates this AP is ready for warm reset (if required).
++	lapic_write(LAPIC_MSG_REG, send | F10_APSTATE_RESET);
++}
++
++static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
++{
++	u32 fidmax;
++	u32 fidmax_new;
++
++	fidmax = (fid_packed >> 8) & 0xFF;
++
++	fidmax_new = (fid_packed_new >> 8) & 0xFF;
++
++	if (fidmax > fidmax_new) {
++		fidmax = fidmax_new;
++	}
++
++	fid_packed &= 0xFF << 16;
++	fid_packed |= (fidmax << 8);
++	fid_packed |= fid_packed_new & (0xFF << 16);	// set nb_cof_vid_update
++
++	return fid_packed;
++}
++
++static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
++{
++	u32 readback = 0;
++	u32 timeout = 1;
++
++	struct fidvid_st *fvp = gp;
++	int loop;
++
++	print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
++
++	loop = 100000;
++	while (--loop > 0) {
++		if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
++			continue;
++		if ((readback & 0x3f) == 1) {
++			timeout = 0;
++			break;	/* target ap is in stage 1 */
++		}
++	}
++
++	if (timeout) {
++		printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
++		       __func__, ap_apicid);
++		return;
++	}
++
++	print_debug_fv("\treadback = ", readback);
++
++	fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
++
++	print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
++
++}
++
++static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
++{
++	msr_t msr;
++	u8 i;
++	u8 StartupPstate;
++
++	/* BKDG 2.4.2.9.1 11-12
++         * This function copies newNbVid to NbVid bits in P-state
++	 * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of
++	 * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in
++	 * P-state Registers[4:0] if its IddValue!=0 in case of
++	 * NbVidUpdatedAll=1. Then transition to StartPstate.
++	 */
++
++	/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
++	for (i = 0; i < 5; i++) {
++		msr = rdmsr(0xC0010064 + i);
++		/*  NbDid (bit 22 of P-state Reg) == 0  or NbVidUpdatedAll = 1 */
++		if (   (msr.hi & PS_IDD_VALUE_MASK)
++                    && (msr.hi & PS_EN_MASK)
++                    &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) {
++			msr.lo &= PS_NB_VID_M_OFF;
++			msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT;
++			wrmsr(0xC0010064 + i, msr);
++		}
++	}
++
++        /* Not documented. Would overwrite Nb_Vids just copied
++         * should we just update cpu_vid or nothing at all ?
++	 */
++	if (pviMode) { //single plane
++            UpdateSinglePlaneNbVid();
++	}
++	/* For each core in the system, transition all cores to StartupPstate */
++	msr = rdmsr(0xC0010071);
++	StartupPstate = msr.hi & 0x07;
++
++	/* Set and wait for StartupPstate to set. */
++        set_pstate(StartupPstate);
++
++}
++
++static void finalPstateChange(void)
++{
++	/* Enable P0 on all cores for best performance.
++	 * Linux can slow them down later if need be.
++	 * It is safe since they will be in C1 halt
++	 * most of the time anyway.
++	 */
++	set_pstate(0);
++}
++
++static void init_fidvid_stage2(u32 apicid, u32 nodeid)
++{
++	msr_t msr;
++	device_t dev;
++	u32 reg1fc;
++	u32 dtemp;
++	u32 nbvid;
++	u8 nb_cof_vid_update = needs_NB_COF_VID_update();
++	u8 NbVidUpdateAll;
++	u8 pvimode;
++
++	/* After warm reset finish the fid/vid setup for all cores. */
++
++	/* If any node has nb_cof_vid_update set all nodes need an update. */
++
++	dev = NODE_PCI(nodeid, 3);
++	pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
++	reg1fc = pci_read_config32(dev, 0x1FC);
++	nbvid = (reg1fc >> 7) & 0x7F;
++	NbVidUpdateAll = (reg1fc >> 1) & 1;
++
++	if (nb_cof_vid_update) {
++		if (!pvimode) {	/* SVI */
++			nbvid = nbvid - ((reg1fc >> 17) & 0x1F);
++		}
++		/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
++		fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode);
++ 	} else {		/* !nb_cof_vid_update */
++		if (pvimode)
++			UpdateSinglePlaneNbVid();
++	}
++	dtemp = pci_read_config32(dev, 0xA0);
++	dtemp &= PLLLOCK_OFF;
++	dtemp |= PLLLOCK_DFT_L;
++	pci_write_config32(dev, 0xA0, dtemp);
++
++        dualPlaneOnly(dev);
++        applyBoostFIDOffset(dev);
++        enableNbPState1(dev);
++
++	finalPstateChange();
++
++	/* Set TSC to tick at the P0 ndfid rate */
++	msr = rdmsr(HWCR);
++	msr.lo |= 1 << 24;
++	wrmsr(HWCR, msr);
++}
++
++
++#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
++struct ap_apicid_st {
++	u32 num;
++	// it could use 256 bytes for 64 node quad core system
++	u8 apicid[NODE_NUMS * 4];
++};
++
++static void store_ap_apicid(unsigned ap_apicid, void *gp)
++{
++	struct ap_apicid_st *p = gp;
++
++	p->apicid[p->num++] = ap_apicid;
++
++}
++#endif
++
++
++static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
++{
++#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
++	struct ap_apicid_st ap_apicidx;
++	u32 i;
++#endif
++	struct fidvid_st fv;
++
++	printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
++
++	/* Steps 1-6 of BIOS NB COF and VID Configuration
++	 * for SVI and Single-Plane PVI Systems.
++	 */
++
++	fv.common_fid = init_fidvid_core(0,0);
++
++	print_debug_fv("BSP fid = ", fv.common_fid);
++
++#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY
++	/* For all APs (We know the APIC ID of all APs even when the APIC ID
++	   is lifted) remote read from AP LAPIC_MSG_REG about max fid.
++	   Then calculate the common max fid that can be used for all
++	   APs and BSP */
++	ap_apicidx.num = 0;
++
++	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
++
++	for (i = 0; i < ap_apicidx.num; i++) {
++		init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
++	}
++#else
++	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
++#endif
++
++	print_debug_fv("common_fid = ", fv.common_fid);
++
++	if (fv.common_fid & (1 << 16)) {	/* check nb_cof_vid_update */
++
++		// Enable the common fid and other settings.
++		enable_fid_change((fv.common_fid >> 8) & 0x1F);
++
++		// nbfid change need warm reset, so reset at first
++		return 1;
++	}
++
++	return 0;		// No FID/VID changes. Don't reset
++}
++#endif
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+new file mode 100644
+index 0000000..8de6d25
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+@@ -0,0 +1,968 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#include "cpu/amd/car/post_cache_as_ram.c"
++#include "defaults.h"
++#include <stdlib.h>
++#include <cpu/x86/lapic.h>
++#include <cpu/x86/mtrr.h>
++#include <northbridge/amd/amdfam10/amdfam10.h>
++#include <northbridge/amd/amdht/AsPsDefs.h>
++#include <northbridge/amd/amdht/porting.h>
++
++#include <northbridge/amd/amdfam10/raminit_amdmct.c>
++#include <reset.h>
++
++static void prep_fid_change(void);
++static void init_fidvid_stage2(u32 apicid, u32 nodeid);
++void cpuSetAMDMSR(void);
++
++#if CONFIG_PCI_IO_CFG_EXT
++static void set_EnableCf8ExtCfg(void)
++{
++	// set the NB_CFG[46]=1;
++	msr_t msr;
++	msr = rdmsr(NB_CFG_MSR);
++	// EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
++	msr.hi |= (1 << (46 - 32));
++	wrmsr(NB_CFG_MSR, msr);
++}
++#else
++static void set_EnableCf8ExtCfg(void) { }
++#endif
++
++
++typedef void (*process_ap_t) (u32 apicid, void *gp);
++
++//core_range = 0 : all cores
++//core range = 1 : core 0 only
++//core range = 2 : cores other than core0
++
++static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
++			void *gp)
++{
++	// here assume the OS don't change our apicid
++	u32 ap_apicid;
++
++	u32 nodes;
++	u32 siblings;
++	u32 disable_siblings;
++	u32 cores_found;
++	u32 nb_cfg_54;
++	int i, j;
++	u32 ApicIdCoreIdSize;
++	uint8_t rev_gte_d = 0;
++	uint8_t dual_node = 0;
++	uint32_t f3xe8;
++
++	/* get_nodes define in ht_wrapper.c */
++	nodes = get_nodes();
++
++	if (!CONFIG_LOGICAL_CPUS ||
++	    read_option(multi_core, 0) != 0) {	// 0 means multi core
++		disable_siblings = 1;
++	} else {
++		disable_siblings = 0;
++	}
++
++	/* Assume that all node are same stepping, otherwise we can use use
++	   nb_cfg_54 from bsp for all nodes */
++	nb_cfg_54 = read_nb_cfg_54();
++	f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
++
++	if (cpuid_eax(0x80000001) >= 0x8)
++		/* Revision D or later */
++		rev_gte_d = 1;
++
++	if (rev_gte_d)
++		 /* Check for dual node capability */
++		if (f3xe8 & 0x20000000)
++			dual_node = 1;
++
++	ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf);
++	if (ApicIdCoreIdSize) {
++		siblings = ((1 << ApicIdCoreIdSize) - 1);
++	} else {
++		siblings = 3;	//quad core
++	}
++
++	for (i = 0; i < nodes; i++) {
++		cores_found = get_core_num_in_bsp(i);
++		if (siblings > cores_found)
++			siblings = cores_found;
++
++		u32 jstart, jend;
++
++		if (core_range == 2) {
++			jstart = 1;
++		} else {
++			jstart = 0;
++		}
++
++		if (disable_siblings || (core_range == 1)) {
++			jend = 0;
++		} else {
++			jend = cores_found;
++		}
++
++		for (j = jstart; j <= jend; j++) {
++			if (dual_node) {
++				ap_apicid = 0;
++				if (nb_cfg_54) {
++					ap_apicid |= ((i >> 1) & 0x3) << 4;			/* Node ID */
++					ap_apicid |= ((i & 0x1) * (siblings + 1)) + j;		/* Core ID */
++				} else {
++					ap_apicid |= i & 0x3;					/* Node ID */
++					ap_apicid |= (((i & 0x1) * (siblings + 1)) + j) << 4;	/* Core ID */
++				}
++			} else {
++				ap_apicid =
++				i * (nb_cfg_54 ? (siblings + 1) : 1) +
++				j * (nb_cfg_54 ? 1 : 64);
++			}
++
++
++#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
++#if !CONFIG_LIFT_BSP_APIC_ID
++			if ((i != 0) || (j != 0))	/* except bsp */
++#endif
++				ap_apicid += CONFIG_APIC_ID_OFFSET;
++#endif
++
++			if (ap_apicid == bsp_apicid)
++				continue;
++
++			process_ap(ap_apicid, gp);
++
++		}
++	}
++}
++
++static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
++{
++	int timeout;
++	u32 status;
++	int result;
++	lapic_wait_icr_idle();
++	lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
++	lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
++
++/* Extra busy check compared to lapic.h */
++	timeout = 0;
++	do {
++		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
++	} while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
++
++	timeout = 0;
++	do {
++		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
++	} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
++
++	result = -1;
++
++	if (status == LAPIC_ICR_RR_VALID) {
++		*pvalue = lapic_read(LAPIC_RRR);
++		result = 0;
++	}
++	return result;
++}
++
++#if CONFIG_SET_FIDVID
++static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
++#endif
++
++static inline __attribute__ ((always_inline))
++void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
++				const char *str)
++{
++	printk(BIOS_DEBUG,
++	       "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str,
++	       apicid, id.nodeid, id.coreid);
++}
++
++static u32 wait_cpu_state(u32 apicid, u32 state)
++{
++	u32 readback = 0;
++	u32 timeout = 1;
++	int loop = 4000000;
++	while (--loop > 0) {
++		if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0)
++			continue;
++		if ((readback & 0x3f) == state || (readback & 0x3f) == F10_APSTATE_RESET) {
++			timeout = 0;
++			break;	//target cpu is in stage started
++		}
++	}
++	if (timeout) {
++		if (readback) {
++			timeout = readback;
++		}
++	}
++
++	return timeout;
++}
++
++static void wait_ap_started(u32 ap_apicid, void *gp)
++{
++	u32 timeout;
++	timeout = wait_cpu_state(ap_apicid, F10_APSTATE_STARTED);
++	printk(BIOS_DEBUG, "* AP %02x", ap_apicid);
++	if (timeout) {
++		printk(BIOS_DEBUG, " timed out:%08x\n", timeout);
++	} else {
++		printk(BIOS_DEBUG, "started\n");
++	}
++}
++
++void wait_all_other_cores_started(u32 bsp_apicid)
++{
++	// all aps other than core0
++	printk(BIOS_DEBUG, "started ap apicid: ");
++	for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0);
++	printk(BIOS_DEBUG, "\n");
++}
++
++void allow_all_aps_stop(u32 bsp_apicid)
++{
++	/* Called by the BSP to indicate AP can stop */
++
++	/* FIXME Do APs use this? */
++
++	// allow aps to stop use 6 bits for state
++	lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED);
++}
++
++static void enable_apic_ext_id(u32 node)
++{
++	u32 val;
++
++	val = pci_read_config32(NODE_HT(node), 0x68);
++	val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
++	pci_write_config32(NODE_HT(node), 0x68, val);
++}
++
++static void STOP_CAR_AND_CPU(void)
++{
++	msr_t msr;
++
++	/* Disable L2 IC to L3 connection (Only for CAR) */
++	msr = rdmsr(BU_CFG2);
++	msr.lo &= ~(1 << ClLinesToNbDis);
++	wrmsr(BU_CFG2, msr);
++
++	disable_cache_as_ram();	// inline
++	/* stop all cores except node0/core0 the bsp .... */
++	stop_this_cpu();
++}
++
++static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
++{
++	u32 bsp_apicid = 0;
++	u32 apicid;
++	struct node_core_id id;
++
++	/* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */
++	uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE;
++	uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH;
++	uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE;
++	uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size;
++	void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);
++	if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
++		printk(BIOS_WARNING,
++			"sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n",
++			sysinfo, sysinfo + 1, lower_stack_region_boundary);
++
++	/*
++	 * already set early mtrr in cache_as_ram.inc
++	 */
++
++	/* that is from initial apicid, we need nodeid and coreid
++	   later */
++	id = get_node_core_id_x();
++
++	/* NB_CFG MSR is shared between cores, so we need make sure
++	   core0 is done at first --- use wait_all_core0_started  */
++	if (id.coreid == 0) {
++		set_apicid_cpuid_lo();	/* only set it on core0 */
++		set_EnableCf8ExtCfg();	/* only set it on core0 */
++#if CONFIG_ENABLE_APIC_EXT_ID
++		enable_apic_ext_id(id.nodeid);
++#endif
++	}
++
++	enable_lapic();
++
++#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
++	u32 initial_apicid = get_initial_apicid();
++
++#if !CONFIG_LIFT_BSP_APIC_ID
++	if (initial_apicid != 0)	// other than bsp
++#endif
++	{
++		/* use initial apic id to lift it */
++		u32 dword = lapic_read(LAPIC_ID);
++		dword &= ~(0xff << 24);
++		dword |=
++		    (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
++
++		lapic_write(LAPIC_ID, dword);
++	}
++#if CONFIG_LIFT_BSP_APIC_ID
++	bsp_apicid += CONFIG_APIC_ID_OFFSET;
++#endif
++
++#endif
++
++	/* get the apicid, it may be lifted already */
++	apicid = lapicid();
++
++	// show our apicid, nodeid, and coreid
++	if (id.coreid == 0) {
++		if (id.nodeid != 0)	//all core0 except bsp
++			print_apicid_nodeid_coreid(apicid, id, " core0: ");
++	} else {		//all other cores
++		print_apicid_nodeid_coreid(apicid, id, " corex: ");
++	}
++
++	if (cpu_init_detectedx) {
++		print_apicid_nodeid_coreid(apicid, id,
++					   "\n\n\nINIT detected from ");
++		printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n");
++		soft_reset();
++	}
++
++	if (id.coreid == 0) {
++		if (!(warm_reset_detect(id.nodeid)))	//FIXME: INIT is checked above but check for more resets?
++			distinguish_cpu_resets(id.nodeid);	// Also indicates we are started
++	}
++	// Mark the core as started.
++	lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED);
++
++	if (apicid != bsp_apicid) {
++		/* Setup each AP's cores MSRs.
++		 * This happens after HTinit.
++		 * The BSP runs this code in it's own path.
++		 */
++		update_microcode(cpuid_eax(1));
++
++		cpuSetAMDMSR();
++
++#if CONFIG_SET_FIDVID
++#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY
++		// Run on all AP for proper FID/VID setup.
++		if (id.coreid == 0)	// only need set fid for core0
++#endif
++		{
++			// check warm(bios) reset to call stage2 otherwise do stage1
++			if (warm_reset_detect(id.nodeid)) {
++				printk(BIOS_DEBUG,
++				       "init_fidvid_stage2 apicid: %02x\n",
++				       apicid);
++				init_fidvid_stage2(apicid, id.nodeid);
++			} else {
++				printk(BIOS_DEBUG,
++				       "init_fidvid_ap(stage1) apicid: %02x\n",
++				       apicid);
++				init_fidvid_ap(apicid, id.nodeid, id.coreid);
++			}
++		}
++#endif
++
++		/* AP is ready, configure MTRRs and go to sleep */
++		set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
++
++		STOP_CAR_AND_CPU();
++
++		printk(BIOS_DEBUG,
++		       "\nAP %02x should be halted but you are reading this....\n",
++		       apicid);
++	}
++
++	return bsp_apicid;
++}
++
++static u32 is_core0_started(u32 nodeid)
++{
++	u32 htic;
++	device_t device;
++	device = NODE_PCI(nodeid, 0);
++	htic = pci_read_config32(device, HT_INIT_CONTROL);
++	htic &= HTIC_ColdR_Detect;
++	return htic;
++}
++
++void wait_all_core0_started(void)
++{
++	/* When core0 is started, it will distingush_cpu_resets
++	 * So wait for that to finish */
++	u32 i;
++	u32 nodes = get_nodes();
++
++	printk(BIOS_DEBUG, "core0 started: ");
++	for (i = 1; i < nodes; i++) {	// skip bsp, because it is running on bsp
++		while (!is_core0_started(i)) {
++		}
++		printk(BIOS_DEBUG, " %02x", i);
++	}
++	printk(BIOS_DEBUG, "\n");
++}
++
++#if CONFIG_MAX_PHYSICAL_CPUS > 1
++/**
++ * void start_node(u32 node)
++ *
++ *  start the core0 in node, so it can generate HT packet to feature code.
++ *
++ * This function starts the AP nodes core0s. wait_all_core0_started() in
++ * romstage.c waits for all the AP to be finished before continuing
++ * system init.
++ */
++static void start_node(u8 node)
++{
++	u32 val;
++
++	/* Enable routing table */
++	printk(BIOS_DEBUG, "Start node %02x", node);
++
++#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
++	/* For FAM10 support, we need to set Dram base/limit for the new node */
++	pci_write_config32(NODE_MP(node), 0x44, 0);
++	pci_write_config32(NODE_MP(node), 0x40, 3);
++#endif
++
++	/* Allow APs to make requests (ROM fetch) */
++	val = pci_read_config32(NODE_HT(node), 0x6c);
++	val &= ~(1 << 1);
++	pci_write_config32(NODE_HT(node), 0x6c, val);
++
++	printk(BIOS_DEBUG, " done.\n");
++}
++
++/**
++ * static void setup_remote_node(u32 node)
++ *
++ * Copy the BSP Address Map to each AP.
++ */
++static void setup_remote_node(u8 node)
++{
++	/* There registers can be used with F1x114_x Address Map at the
++	   same time, So must set them even 32 node */
++	static const u16 pci_reg[] = {
++		/* DRAM Base/Limits Registers */
++		0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
++		0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
++		0x144, 0x14c, 0x154, 0x15c, 0x164, 0x16c, 0x174, 0x17c,
++		0x140, 0x148, 0x150, 0x158, 0x160, 0x168, 0x170, 0x178,
++		/* MMIO Base/Limits Registers */
++		0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
++		0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
++		/* IO Base/Limits Registers */
++		0xc4, 0xcc, 0xd4, 0xdc,
++		0xc0, 0xc8, 0xd0, 0xd8,
++		/* Configuration Map Registers */
++		0xe0, 0xe4, 0xe8, 0xec,
++	};
++	u16 i;
++
++	printk(BIOS_DEBUG, "setup_remote_node: %02x", node);
++
++	/* copy the default resource map from node 0 */
++	for (i = 0; i < ARRAY_SIZE(pci_reg); i++) {
++		u32 value;
++		u16 reg;
++		reg = pci_reg[i];
++		value = pci_read_config32(NODE_MP(0), reg);
++		pci_write_config32(NODE_MP(node), reg, value);
++
++	}
++	printk(BIOS_DEBUG, " done\n");
++}
++#endif				/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
++
++static void AMD_Errata281(u8 node, u32 revision, u32 platform)
++{
++	/* Workaround for Transaction Scheduling Conflict in
++	 * Northbridge Cross Bar.  Implement XCS Token adjustment
++	 * for ganged links.  Also, perform fix up for the mixed
++	 * revision case.
++	 */
++
++	u32 reg, val;
++	u8 i;
++	u8 mixed = 0;
++	u8 nodes = get_nodes();
++
++	if (platform & AMD_PTYPE_SVR) {
++		/* For each node we need to check for a "broken" node */
++		if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) {
++			for (i = 0; i < nodes; i++) {
++				if (mctGetLogicalCPUID(i) &
++				    (AMD_DR_B0 | AMD_DR_B1)) {
++					mixed = 1;
++					break;
++				}
++			}
++		}
++
++		if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) {
++
++			/* F0X68[22:21] DsNpReqLmt0 = 01b */
++			val = pci_read_config32(NODE_PCI(node, 0), 0x68);
++			val &= ~0x00600000;
++			val |= 0x00200000;
++			pci_write_config32(NODE_PCI(node, 0), 0x68, val);
++
++			/* F3X6C */
++			val = pci_read_config32(NODE_PCI(node, 3), 0x6C);
++			val &= ~0x700780F7;
++			val |= 0x00010094;
++			pci_write_config32(NODE_PCI(node, 3), 0x6C, val);
++
++			/* F3X7C */
++			val = pci_read_config32(NODE_PCI(node, 3), 0x7C);
++			val &= ~0x707FFF1F;
++			val |= 0x00144514;
++			pci_write_config32(NODE_PCI(node, 3), 0x7C, val);
++
++			/* F3X144[3:0] RspTok = 0001b */
++			val = pci_read_config32(NODE_PCI(node, 3), 0x144);
++			val &= ~0x0000000F;
++			val |= 0x00000001;
++			pci_write_config32(NODE_PCI(node, 3), 0x144, val);
++
++			for (i = 0; i < 3; i++) {
++				reg = 0x148 + (i * 4);
++				val = pci_read_config32(NODE_PCI(node, 3), reg);
++				val &= ~0x000000FF;
++				val |= 0x000000DB;
++				pci_write_config32(NODE_PCI(node, 3), reg, val);
++			}
++		}
++	}
++}
++
++static void AMD_Errata298(void)
++{
++	/* Workaround for L2 Eviction May Occur during operation to
++	 * set Accessed or dirty bit.
++	 */
++
++	msr_t msr;
++	u8 i;
++	u8 affectedRev = 0;
++	u8 nodes = get_nodes();
++
++	/* For each core we need to check for a "broken" node */
++	for (i = 0; i < nodes; i++) {
++		if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) {
++			affectedRev = 1;
++			break;
++		}
++	}
++
++	if (affectedRev) {
++		msr = rdmsr(HWCR);
++		msr.lo |= 0x08;	/* Set TlbCacheDis bit[3] */
++		wrmsr(HWCR, msr);
++
++		msr = rdmsr(BU_CFG);
++		msr.lo |= 0x02;	/* Set TlbForceMemTypeUc bit[1] */
++		wrmsr(BU_CFG, msr);
++
++		msr = rdmsr(OSVW_ID_Length);
++		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
++		wrmsr(OSVW_ID_Length, msr);
++
++		msr = rdmsr(OSVW_Status);
++		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
++		wrmsr(OSVW_Status, msr);
++	}
++
++	if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) {
++		msr = rdmsr(OSVW_ID_Length);
++		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
++		wrmsr(OSVW_ID_Length, msr);
++
++	}
++}
++
++static u32 get_platform_type(void)
++{
++	u32 ret = 0;
++
++	switch (SYSTEM_TYPE) {
++	case 1:
++		ret |= AMD_PTYPE_DSK;
++		break;
++	case 2:
++		ret |= AMD_PTYPE_MOB;
++		break;
++	case 0:
++		ret |= AMD_PTYPE_SVR;
++		break;
++	default:
++		break;
++	}
++
++	/* FIXME: add UMA support. */
++
++	/* All Fam10 are multi core */
++	ret |= AMD_PTYPE_MC;
++
++	return ret;
++}
++
++static void AMD_SetupPSIVID_d(u32 platform_type, u8 node)
++{
++	u32 dword;
++	int i;
++	msr_t msr;
++
++	if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) {
++
++		/* The following code sets the PSIVID to the lowest support P state
++		 * assuming that the VID for the lowest power state is below
++		 * the VDD voltage regulator threshold. (This also assumes that there
++		 * is a Pstate lower than P0)
++		 */
++
++		for (i = 4; i >= 0; i--) {
++			msr = rdmsr(PS_REG_BASE + i);
++			/*  Pstate valid? */
++			if (msr.hi & PS_EN_MASK) {
++				dword = pci_read_config32(NODE_PCI(i, 3), 0xA0);
++				dword &= ~0x7F;
++				dword |= (msr.lo >> 9) & 0x7F;
++				pci_write_config32(NODE_PCI(i, 3), 0xA0, dword);
++				break;
++			}
++		}
++	}
++}
++
++/**
++ * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links.
++ *  HT Phy operations are not valid on links that aren't present, so this
++ *  prevents invalid accesses.
++ *
++ * Returns the offset of the link register.
++ */
++static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
++{
++	u32 reg;
++	u32 val;
++
++	/* get start of CPU HT Host Capabilities */
++	val = pci_read_config32(NODE_PCI(node, 0), 0x34);
++	val &= 0xFF;		//reg offset of first link
++
++	cap_count++;
++
++	/* Traverse through the capabilities. */
++	do {
++		reg = pci_read_config32(NODE_PCI(node, 0), val);
++		/* Is the capability block a HyperTransport capability block? */
++		if ((reg & 0xFF) == 0x08) {
++			/* Is the HT capability block an HT Host Capability? */
++			if ((reg & 0xE0000000) == (1 << 29))
++				cap_count--;
++		}
++
++		if (cap_count)
++			val = (reg >> 8) & 0xFF;	//update reg offset
++	} while (cap_count && val);
++
++	*offset = (u8) val;
++
++	/* If requested capability found val != 0 */
++	if (!cap_count)
++		return TRUE;
++	else
++		return FALSE;
++}
++
++/**
++ * AMD_checkLinkType - Compare desired link characteristics using a logical
++ *     link type mask.
++ *
++ * Returns the link characteristic mask.
++ */
++static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
++{
++	u32 val;
++	u32 linktype = 0;
++
++	/* Check connect, init and coherency */
++	val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18);
++	val &= 0x1F;
++
++	if (val == 3)
++		linktype |= HTPHY_LINKTYPE_COHERENT;
++
++	if (val == 7)
++		linktype |= HTPHY_LINKTYPE_NONCOHERENT;
++
++	if (linktype) {
++		/* Check gen3 */
++		val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08);
++
++		if (((val >> 8) & 0x0F) > 6)
++			linktype |= HTPHY_LINKTYPE_HT3;
++		else
++			linktype |= HTPHY_LINKTYPE_HT1;
++
++		/* Check ganged */
++		val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170);
++
++		if (val & 1)
++			linktype |= HTPHY_LINKTYPE_GANGED;
++		else
++			linktype |= HTPHY_LINKTYPE_UNGANGED;
++	}
++	return linktype;
++}
++
++/**
++ * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update
++ *   a phy setting for that link.
++ */
++static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry)
++{
++	u32 phyReg;
++	u32 phyBase;
++	u32 val;
++
++	/* Determine this link's portal */
++	if (link > 3)
++		link -= 4;
++
++	phyBase = ((u32) link << 3) | 0x180;
++
++	/* Get the portal control register's initial value
++	 * and update it to access the desired phy register
++	 */
++	phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase);
++
++	if (fam10_htphy_default[entry].htreg > 0x1FF) {
++		phyReg &= ~HTPHY_DIRECT_OFFSET_MASK;
++		phyReg |= HTPHY_DIRECT_MAP;
++	} else {
++		phyReg &= ~HTPHY_OFFSET_MASK;
++	}
++
++	/* Now get the current phy register data
++	 * LinkPhyDone = 0, LinkPhyWrite = 0 is a read
++	 */
++	phyReg |= fam10_htphy_default[entry].htreg;
++	pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
++
++	do {
++		val = pci_read_config32(NODE_PCI(node, 4), phyBase);
++	} while (!(val & HTPHY_IS_COMPLETE_MASK));
++
++	/* Now we have the phy register data, apply the change */
++	val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4);
++	val &= ~fam10_htphy_default[entry].mask;
++	val |= fam10_htphy_default[entry].data;
++	pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val);
++
++	/* write it through the portal to the phy
++	 * LinkPhyDone = 0, LinkPhyWrite = 1 is a write
++	 */
++	phyReg |= HTPHY_WRITE_CMD;
++	pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
++
++	do {
++		val = pci_read_config32(NODE_PCI(node, 4), phyBase);
++	} while (!(val & HTPHY_IS_COMPLETE_MASK));
++}
++
++void cpuSetAMDMSR(void)
++{
++	/* This routine loads the CPU with default settings in fam10_msr_default
++	 * table . It must be run after Cache-As-RAM has been enabled, and
++	 * Hypertransport initialization has taken place.  Also note
++	 * that it is run on the current processor only, and only for the current
++	 * processor core.
++	 */
++	msr_t msr;
++	u8 i;
++	u32 revision, platform;
++
++	printk(BIOS_DEBUG, "cpuSetAMDMSR ");
++
++	revision = mctGetLogicalCPUID(0xFF);
++	platform = get_platform_type();
++
++	for (i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
++		if ((fam10_msr_default[i].revision & revision) &&
++		    (fam10_msr_default[i].platform & platform)) {
++			msr = rdmsr(fam10_msr_default[i].msr);
++			msr.hi &= ~fam10_msr_default[i].mask_hi;
++			msr.hi |= fam10_msr_default[i].data_hi;
++			msr.lo &= ~fam10_msr_default[i].mask_lo;
++			msr.lo |= fam10_msr_default[i].data_lo;
++			wrmsr(fam10_msr_default[i].msr, msr);
++		}
++	}
++	AMD_Errata298();
++
++	printk(BIOS_DEBUG, " done\n");
++}
++
++static void cpuSetAMDPCI(u8 node)
++{
++	/* This routine loads the CPU with default settings in fam10_pci_default
++	 * table . It must be run after Cache-As-RAM has been enabled, and
++	 * Hypertransport initialization has taken place.  Also note
++	 * that it is run for the first core on each node
++	 */
++	u8 i, j;
++	u32 revision, platform;
++	u32 val;
++	u8 offset;
++
++	printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
++
++	revision = mctGetLogicalCPUID(node);
++	platform = get_platform_type();
++
++	AMD_SetupPSIVID_d(platform, node);	/* Set PSIVID offset which is not table driven */
++
++	for (i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
++		if ((fam10_pci_default[i].revision & revision) &&
++		    (fam10_pci_default[i].platform & platform)) {
++			val = pci_read_config32(NODE_PCI(node,
++							 fam10_pci_default[i].
++							 function),
++						fam10_pci_default[i].offset);
++			val &= ~fam10_pci_default[i].mask;
++			val |= fam10_pci_default[i].data;
++			pci_write_config32(NODE_PCI(node,
++						    fam10_pci_default[i].
++						    function),
++					   fam10_pci_default[i].offset, val);
++		}
++	}
++
++	for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
++		if ((fam10_htphy_default[i].revision & revision) &&
++		    (fam10_htphy_default[i].platform & platform)) {
++			/* HT Phy settings either apply to both sublinks or have
++			 * separate registers for sublink zero and one, so there
++			 * will be two table entries. So, here we only loop
++			 * through the sublink zeros in function zero.
++			 */
++			for (j = 0; j < 4; j++) {
++				if (AMD_CpuFindCapability(node, j, &offset)) {
++					if (AMD_checkLinkType(node, j, offset)
++					    & fam10_htphy_default[i].linktype) {
++						AMD_SetHtPhyRegister(node, j,
++								     i);
++					}
++				} else {
++					/* No more capabilities,
++					 * link not present
++					 */
++					break;
++				}
++			}
++		}
++	}
++
++	/* FIXME: add UMA support and programXbarToSriReg(); */
++
++	AMD_Errata281(node, revision, platform);
++
++	/* FIXME: if the dct phy doesn't init correct it needs to reset.
++	   if (revision & (AMD_DR_B2 | AMD_DR_B3))
++	   dctPhyDiag(); */
++
++	printk(BIOS_DEBUG, " done\n");
++}
++
++#ifdef UNUSED_CODE
++static void cpuInitializeMCA(void)
++{
++	/* Clears Machine Check Architecture (MCA) registers, which power on
++	 * containing unknown data, on currently running processor.
++	 * This routine should only be executed on initial power on (cold boot),
++	 * not across a warm reset because valid data is present at that time.
++	 */
++
++	msr_t msr;
++	u32 reg;
++	u8 i;
++
++	if (cpuid_edx(1) & 0x4080) {	/* MCE and MCA (edx[7] and edx[14]) */
++		msr = rdmsr(MCG_CAP);
++		if (msr.lo & MCG_CTL_P) {	/* MCG_CTL_P bit is set? */
++			msr.lo &= 0xFF;
++			msr.lo--;
++			msr.lo <<= 2;	/* multiply the count by 4 */
++			reg = MC0_STA + msr.lo;
++			msr.lo = msr.hi = 0;
++			for (i = 0; i < 4; i++) {
++				wrmsr(reg, msr);
++				reg -= 4;	/* Touch status regs for each bank */
++			}
++		}
++	}
++}
++#endif
++
++/**
++ * finalize_node_setup()
++ *
++ * Do any additional post HT init
++ *
++ */
++static void finalize_node_setup(struct sys_info *sysinfo)
++{
++	u8 i;
++	u8 nodes = get_nodes();
++	u32 reg;
++
++	/* read Node0 F0_0x64 bit [8:10] to find out SbLink # */
++	reg = pci_read_config32(NODE_HT(0), 0x64);
++	sysinfo->sblk = (reg >> 8) & 7;
++	sysinfo->sbbusn = 0;
++	sysinfo->nodes = nodes;
++	sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
++
++	for (i = 0; i < nodes; i++) {
++		cpuSetAMDPCI(i);
++	}
++
++#if CONFIG_SET_FIDVID
++	// Prep each node for FID/VID setup.
++	prep_fid_change();
++#endif
++
++#if CONFIG_MAX_PHYSICAL_CPUS > 1
++	/* Skip the BSP, start at node 1 */
++	for (i = 1; i < nodes; i++) {
++		setup_remote_node(i);
++		start_node(i);
++	}
++#endif
++}
++
++#include "fidvid.c"
+diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+new file mode 100644
+index 0000000..b942c1a
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+@@ -0,0 +1,165 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2007 Advanced Micro Devices, Inc.
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#include <console/console.h>
++#include <cpu/x86/msr.h>
++#include <cpu/amd/mtrr.h>
++#include <device/device.h>
++#include <device/pci.h>
++#include <string.h>
++#include <cpu/x86/msr.h>
++#include <cpu/x86/smm.h>
++#include <cpu/x86/pae.h>
++#include <pc80/mc146818rtc.h>
++#include <cpu/x86/lapic.h>
++#include "northbridge/amd/amdfam10/amdfam10.h"
++#include <cpu/amd/model_10xxx_rev.h>
++#include <cpu/cpu.h>
++#include <cpu/x86/cache.h>
++#include <cpu/x86/mtrr.h>
++#include <cpu/amd/multicore.h>
++#include <cpu/amd/model_10xxx_msr.h>
++
++#define MCI_STATUS 0x401
++
++static void model_10xxx_init(device_t dev)
++{
++	u8 i;
++	msr_t msr;
++	struct node_core_id id;
++#if CONFIG_LOGICAL_CPUS
++	u32 siblings;
++#endif
++
++	id = get_node_core_id(read_nb_cfg_54());	/* nb_cfg_54 can not be set */
++	printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
++
++	/* Turn on caching if we haven't already */
++	x86_enable_cache();
++	amd_setup_mtrrs();
++	x86_mtrr_check();
++
++	disable_cache();
++
++	/* zero the machine check error status registers */
++	msr.lo = 0;
++	msr.hi = 0;
++	for (i = 0; i < 5; i++) {
++		wrmsr(MCI_STATUS + (i * 4), msr);
++	}
++
++	enable_cache();
++
++	/* Enable the local cpu apics */
++	setup_lapic();
++
++	/* Set the processor name string */
++	init_processor_name();
++
++#if CONFIG_LOGICAL_CPUS
++	siblings = cpuid_ecx(0x80000008) & 0xff;
++
++	if (siblings > 0) {
++		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
++		msr.lo |= 1 << 28;
++		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
++
++		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
++		msr.hi |= 1 << (33 - 32);
++		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
++	}
++	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
++#endif
++
++	/* DisableCf8ExtCfg */
++	msr = rdmsr(NB_CFG_MSR);
++	msr.hi &= ~(1 << (46 - 32));
++	wrmsr(NB_CFG_MSR, msr);
++
++	msr = rdmsr(BU_CFG2_MSR);
++	/* Clear ClLinesToNbDis */
++	msr.lo &= ~(1 << 15);
++	/* Clear bit 35 as per Erratum 343 */
++	msr.hi &= ~(1 << (35-32));
++	wrmsr(BU_CFG2_MSR, msr);
++
++	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
++		printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
++
++		/* Set SMM base address for this CPU */
++		msr = rdmsr(SMM_BASE_MSR);
++		msr.lo = SMM_BASE - (lapicid() * 0x400);
++		wrmsr(SMM_BASE_MSR, msr);
++
++		/* Enable the SMM memory window */
++		msr = rdmsr(SMM_MASK_MSR);
++		msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
++		wrmsr(SMM_MASK_MSR, msr);
++	} else {
++		printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
++
++		/* Set SMM base address for this CPU */
++		msr = rdmsr(SMM_BASE_MSR);
++		msr.lo = SMM_BASE - (lapicid() * 0x400);
++		wrmsr(SMM_BASE_MSR, msr);
++
++		/* Disable the SMM memory window */
++		msr.hi = 0x0;
++		msr.lo = 0x0;
++		wrmsr(SMM_MASK_MSR, msr);
++	}
++
++	/* Set SMMLOCK to avoid exploits messing with SMM */
++	msr = rdmsr(HWCR_MSR);
++	msr.lo |= (1 << 0);
++	wrmsr(HWCR_MSR, msr);
++
++}
++
++static struct device_operations cpu_dev_ops = {
++	.init = model_10xxx_init,
++};
++
++static struct cpu_device_id cpu_table[] = {
++//AMD_GH_SUPPORT
++	{ X86_VENDOR_AMD, 0x100f00 },		/* SH-F0 L1 */
++	{ X86_VENDOR_AMD, 0x100f10 },		/* M2 */
++	{ X86_VENDOR_AMD, 0x100f20 },		/* S1g1 */
++	{ X86_VENDOR_AMD, 0x100f21 },
++	{ X86_VENDOR_AMD, 0x100f2A },
++	{ X86_VENDOR_AMD, 0x100f22 },
++	{ X86_VENDOR_AMD, 0x100f23 },
++	{ X86_VENDOR_AMD, 0x100f40 },		/* RB-C0 */
++	{ X86_VENDOR_AMD, 0x100F42 },           /* RB-C2 */
++	{ X86_VENDOR_AMD, 0x100F43 },           /* RB-C3 */
++	{ X86_VENDOR_AMD, 0x100F52 },           /* BL-C2 */
++	{ X86_VENDOR_AMD, 0x100F62 },           /* DA-C2 */
++	{ X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
++	{ X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
++	{ X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
++	{ X86_VENDOR_AMD, 0x100F91 },           /* HY-D1 */
++	{ X86_VENDOR_AMD, 0x100FA0 },           /* PH-E0 */
++	{ 0, 0 },
++};
++
++static const struct cpu_driver model_10xxx __cpu_driver = {
++	.ops      = &cpu_dev_ops,
++	.id_table = cpu_table,
++};
+diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
+new file mode 100644
+index 0000000..8c02fd1
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
+@@ -0,0 +1,98 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ * Copyright (C) 2013 Google, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++#include <stdint.h>
++#include <arch/cpu.h>
++#include <cpu/x86/msr.h>
++#include <timer.h>
++#include <device/pci.h>
++#include <device/pci_ids.h>
++
++#include <northbridge/amd/amdht/AsPsDefs.h>
++#include <cpu/amd/model_10xxx_msr.h>
++
++static struct monotonic_counter {
++	int initialized;
++	uint32_t core_frequency;
++	struct mono_time time;
++	uint64_t last_value;
++} mono_counter;
++
++static inline uint64_t read_counter_msr(void)
++{
++	msr_t counter_msr;
++
++	counter_msr = rdmsr(TSC_MSR);
++
++	return ((uint64_t)counter_msr.hi << 32) | (uint64_t)counter_msr.lo;
++}
++
++static void init_timer(void)
++{
++	uint8_t model;
++	uint32_t cpuid_fms;
++	uint8_t cpufid;
++	uint8_t cpudid;
++	uint8_t boost_capable = 0;
++
++	/* Get CPU model */
++	cpuid_fms = cpuid_eax(0x80000001);
++	model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4);
++
++	/* Get boost capability */
++	if ((model == 0x8) || (model == 0x9)) {	/* revision D */
++		boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2;
++	}
++
++	/* Set up TSC (BKDG v3.62 section 2.9.4)*/
++	msr_t msr = rdmsr(HWCR_MSR);
++	msr.lo |= 0x1000000;
++	wrmsr(HWCR_MSR, msr);
++
++	/* Get core Pstate 0 frequency in MHz */
++	msr = rdmsr(0xC0010064 + boost_capable);
++	cpufid = (msr.lo & 0x3f);
++	cpudid = (msr.lo & 0x1c0) >> 6;
++	mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
++
++	mono_counter.last_value = read_counter_msr();
++	mono_counter.initialized = 1;
++}
++
++void timer_monotonic_get(struct mono_time *mt)
++{
++	uint64_t current_tick;
++	uint32_t usecs_elapsed = 0;
++
++	if (!mono_counter.initialized)
++		init_timer();
++
++	current_tick = read_counter_msr();
++	if (mono_counter.core_frequency != 0)
++		usecs_elapsed = (current_tick - mono_counter.last_value) / mono_counter.core_frequency;
++
++	/* Update current time and tick values only if a full tick occurred. */
++	if (usecs_elapsed) {
++		mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
++		mono_counter.last_value = current_tick;
++	}
++
++	/* Save result. */
++	*mt = mono_counter.time;
++}
+diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+new file mode 100644
+index 0000000..98ef08a
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+@@ -0,0 +1,311 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
++ * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#include <console/console.h>
++#include <stdint.h>
++#include <cpu/x86/msr.h>
++#include <arch/acpigen.h>
++#include <cpu/amd/powernow.h>
++#include <device/pci.h>
++#include <device/pci_ids.h>
++#include <cpu/x86/msr.h>
++#include <cpu/amd/mtrr.h>
++#include <cpu/amd/amdfam10_sysconf.h>
++#include <arch/cpu.h>
++#include <northbridge/amd/amdht/AsPsDefs.h>
++#include <northbridge/amd/amdmct/mct/mct.h>
++#include <northbridge/amd/amdmct/amddefs.h>
++
++static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power,
++				u32 *pstate_latency, u32 *pstate_control,
++				u32 *pstate_status, int coreID,
++				u32 pcontrol_blk, u8 plen, u8 onlyBSP,
++				uint8_t single_link)
++{
++	int i;
++	struct cpuid_result cpuid1;
++
++	if ((onlyBSP) && (coreID != 0)) {
++	    plen = 0;
++	    pcontrol_blk = 0;
++	}
++
++	acpigen_write_processor(coreID, pcontrol_blk, plen);
++	acpigen_write_empty_PCT();
++	acpigen_write_name("_PSS");
++
++	/* add later to total sum */
++	acpigen_write_package(pstate_num);
++
++	for (i = 0;i < pstate_num; i++)
++		acpigen_write_PSS_package(pstate_feq[i],
++					  pstate_power[i],
++					  pstate_latency[i],
++					  pstate_latency[i],
++					  pstate_control[i],
++					  pstate_status[i]);
++
++	/* update the package size */
++	acpigen_pop_len();
++
++	/* Write PPC object */
++	acpigen_write_PPC(pstate_num);
++
++	/* Write PSD indicating coordination type */
++	if ((single_link) && (mctGetLogicalCPUID(0) & AMD_DR_GT_Bx)) {
++		/* Revision C or greater single-link processor */
++		cpuid1 = cpuid(0x80000008);
++		acpigen_write_PSD_package(0, (cpuid1.ecx & 0xff) + 1, SW_ALL);
++	}
++	else {
++		/* Find the local APIC ID for the specified core ID */
++		struct device* cpu;
++		int cpu_index = 0;
++		for (cpu = all_devices; cpu; cpu = cpu->next) {
++			if ((cpu->path.type != DEVICE_PATH_APIC) ||
++				(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
++				continue;
++			if (!cpu->enabled)
++				continue;
++			if (cpu_index == coreID)
++				break;
++			cpu_index++;
++		}
++
++		if (cpu)
++			acpigen_write_PSD_package(cpu->path.apic.apic_id, 1, SW_ANY);
++	}
++
++	/* patch the whole Processor token length */
++	acpigen_pop_len();
++}
++
++/*
++* For details of this algorithm, please refer to the BDKG 3.62 page 69
++*
++* WARNING: The core count algorithm below assumes that all processors
++* are identical, with the same number of active cores.  While the BKDG
++* states the BIOS must enforce this coreboot does not currently do so.
++* As a result it is possible that this code may break if an illegal
++* processor combination is installed.  If it does break please fix the
++* code in the proper locations!
++*/
++void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
++{
++	u8 processor_brand[49];
++	u32 *v;
++	struct cpuid_result cpuid1;
++
++	u16 Pstate_feq[10];
++	u32 Pstate_power[10];
++	u32 Pstate_latency[10];
++	u32 Pstate_control[10];
++	u32 Pstate_status[10];
++	u8 Pstate_num;
++	u8 cmp_cap;
++	u8 index;
++	msr_t msr;
++
++	/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
++	cpuid1 = cpuid(0x80000002);
++	v = (u32 *) processor_brand;
++	v[0] = cpuid1.eax;
++	v[1] = cpuid1.ebx;
++	v[2] = cpuid1.ecx;
++	v[3] = cpuid1.edx;
++	cpuid1 = cpuid(0x80000003);
++	v[4] = cpuid1.eax;
++	v[5] = cpuid1.ebx;
++	v[6] = cpuid1.ecx;
++	v[7] = cpuid1.edx;
++	cpuid1 = cpuid(0x80000004);
++	v[8] = cpuid1.eax;
++	v[9] = cpuid1.ebx;
++	v[10] = cpuid1.ecx;
++	v[11] = cpuid1.edx;
++	processor_brand[48] = 0;
++	printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
++
++	uint32_t dtemp;
++	uint8_t node_index;
++	uint8_t node_count;
++	uint8_t cores_per_node;
++	uint8_t total_core_count;
++
++	/*
++	 * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
++	 * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
++	 * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore
++	 */
++	printk(BIOS_INFO, "Pstates algorithm ...\n");
++	/* Get number of cores */
++	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8);
++	cmp_cap = (dtemp & 0x3000) >> 12;
++	if (mctGetLogicalCPUID(0) & AMD_FAM10_REV_D)	/* revision D */
++		cmp_cap |= (dtemp & 0x8000) >> 13;
++	/* Get number of nodes */
++	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
++	node_count = ((dtemp & 0x70) >> 4) + 1;
++	cores_per_node = cmp_cap + 1;
++
++	/* Compute total number of cores installed in system */
++	total_core_count = cores_per_node * node_count;
++
++	Pstate_num = 0;
++
++	/* See if the CPUID(0x80000007) returned EDX[7]==1b */
++	cpuid1 = cpuid(0x80000007);
++	if ((cpuid1.edx & 0x80) != 0x80) {
++		printk(BIOS_INFO, "No valid set of P-states\n");
++		return;
++	}
++
++	uint8_t pviModeFlag;
++	uint8_t Pstate_max;
++	uint8_t cpufid;
++	uint8_t cpudid;
++	uint8_t cpuvid;
++	uint8_t cpuidd;
++	uint8_t cpuidv;
++	uint8_t power_step_up;
++	uint8_t power_step_down;
++	uint8_t pll_lock_time;
++	uint32_t expanded_cpuidv;
++	uint32_t core_frequency;
++	uint32_t core_power;
++	uint32_t core_latency;
++	uint32_t core_voltage;	/* multiplied by 10000 */
++	uint8_t single_link;
++
++	/* Determine if this is a PVI or SVI system */
++	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
++
++	if (dtemp & PVI_MODE)
++		pviModeFlag = 1;
++	else
++		pviModeFlag = 0;
++
++	/* Get PSmax's index */
++	msr = rdmsr(0xC0010061);
++	Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
++
++	/* Determine if all enabled Pstates have the same fidvid */
++	uint8_t i;
++	uint8_t cpufid_prev = (rdmsr(0xC0010064).lo & 0x3f);
++	uint8_t all_enabled_cores_have_same_cpufid = 1;
++	for (i = 1; i < Pstate_max; i++) {
++		cpufid = rdmsr(0xC0010064 + i).lo & 0x3f;
++		if (cpufid != cpufid_prev) {
++			all_enabled_cores_have_same_cpufid = 0;
++			break;
++		}
++	}
++
++	/* Populate tables with all Pstate information */
++	for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) {
++		/* Get power state information */
++		msr = rdmsr(0xC0010064 + Pstate_num);
++		cpufid = (msr.lo & 0x3f);
++		cpudid = (msr.lo & 0x1c0) >> 6;
++		cpuvid = (msr.lo & 0xfe00) >> 9;
++		cpuidd = (msr.hi & 0xff);
++		cpuidv = (msr.hi & 0x300) >> 8;
++		core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
++		if (pviModeFlag) {
++			if (cpuvid >= 0x20) {
++				core_voltage = 7625 - (((cpuvid - 0x20) * 10000) / 80);
++			}
++			else {
++				core_voltage = 15500 - ((cpuvid * 10000) / 40);
++			}
++		}
++		else {
++			cpuvid = cpuvid & 0x7f;
++			if (cpuvid >= 0x7c)
++				core_voltage = 0;
++			else
++				core_voltage = 15500 - ((cpuvid * 10000) / 80);
++		}
++		switch (cpuidv) {
++			case 0x0:
++				expanded_cpuidv = 1;
++				break;
++			case 0x1:
++				expanded_cpuidv = 10;
++				break;
++			case 0x2:
++				expanded_cpuidv = 100;
++				break;
++			case 0x3:
++				expanded_cpuidv = 1000;
++				break;
++			default:
++				printk(BIOS_ERR, "%s:%s:%d: Invalid cpuidv, "
++					"not generating pstate tables.\n",
++					__FILE__, __func__, __LINE__);
++				return;
++		}
++		core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
++
++		/* Calculate transition latency */
++		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xD4);
++		power_step_up = (dtemp & 0xf000000) >> 24;
++		power_step_down = (dtemp & 0xf00000) >> 20;
++		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
++		pll_lock_time = (dtemp & 0x3800) >> 11;
++		if (all_enabled_cores_have_same_cpufid)
++			core_latency = ((12 * power_step_down) + power_step_up) / 1000;
++		else
++			core_latency = (12 * (power_step_down + power_step_up) / 1000)
++						 + pll_lock_time;
++
++		Pstate_feq[Pstate_num] = core_frequency;
++		Pstate_power[Pstate_num] = core_power;
++		Pstate_latency[Pstate_num] = core_latency;
++		Pstate_control[Pstate_num] = Pstate_num;
++		Pstate_status[Pstate_num] = Pstate_num;
++	}
++
++	/* Print Pstate frequency, power, and latency */
++	for (index = 0; index < Pstate_num; index++) {
++		printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
++			    Pstate_feq[index]);
++		printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
++			    Pstate_power[index]);
++		printk(BIOS_INFO, "Pstate_latency[%d] = %dus\n", index,
++			    Pstate_latency[index]);
++	}
++
++	char pscope[] = "\\_PR";
++
++	acpigen_write_scope(pscope);
++	for (index = 0; index < total_core_count; index++) {
++		/* Determine if this is a single-link processor */
++		node_index = 0x18 + (index / cores_per_node);
++		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80);
++		single_link = !!(((dtemp & 0xff00) >> 8) == 0);
++
++		write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power,
++				Pstate_latency, Pstate_control, Pstate_status,
++				index, pcontrol_blk, plen, onlyBSP, single_link);
++	}
++	acpigen_pop_len();
++}
+diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c
+new file mode 100644
+index 0000000..12c45c9
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/processor_name.c
+@@ -0,0 +1,323 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2007 Advanced Micro Devices, Inc.
++ * Copyright (C) 2008 Peter Stuge
++ * Copyright (C) 2010 Marc Jones <marcj303@gmail.com>
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++/*
++ * This code sets the Processor Name String for AMD64 CPUs.
++ *
++ * Revision Guide for AMD Family 10h Processors
++ * Publication # 41322 Revision: 3.17 Issue Date: February 2008
++ */
++
++#include <console/console.h>
++#include <string.h>
++#include <cpu/x86/msr.h>
++#include <cpu/amd/mtrr.h>
++#include <cpu/cpu.h>
++#include <cpu/amd/model_10xxx_rev.h>
++
++/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
++ * If you change these names your BIOS will _NOT_ pass the AMD validation and
++ * your mainboard will not be posted on the AMD Recommended Motherboard Website
++ */
++
++struct str_s {
++	u8 Pg;
++	u8 NC;
++	u8 String;
++	char const *value;
++};
++
++
++static const struct str_s String1_socket_F[] = {
++	{0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 83"},
++	{0x00, 0x01, 0x01, "Dual-Core AMD Opteron(tm) Processor 23"},
++	{0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 83"},
++	{0x00, 0x03, 0x01, "Quad-Core AMD Opteron(tm) Processor 23"},
++	{0x00, 0x05, 0x00, "Six-Core AMD Opteron(tm) Processor 84"},
++	{0x00, 0x05, 0x01, "Six-Core AMD Opteron(tm) Processor 24"},
++	{0x00, 0x03, 0x02, "Embedded AMD Opteron(tm) Processor 83"},
++	{0x00, 0x03, 0x03, "Embedded AMD Opteron(tm) Processor 23"},
++	{0x00, 0x03, 0x04, "Embedded AMD Opteron(tm) Processor 13"},
++	{0x00, 0x03, 0x05, "AMD Phenom(tm) FX-"},
++	{0x01, 0x01, 0x01, "Embedded AMD Opteron(tm) Processor"},
++	{0, 0, 0, NULL}
++};
++
++static const struct str_s String2_socket_F[] = {
++	{0x00, 0xFF, 0x02, " EE"},
++	{0x00, 0xFF, 0x0A, " SE"},
++	{0x00, 0xFF, 0x0B, " HE"},
++	{0x00, 0xFF, 0x0C, " EE"},
++	{0x00, 0xFF, 0x0D, " Quad-Core Processor"},
++	{0x00, 0xFF, 0x0F, ""},
++	{0x01, 0x01, 0x01, "GF HE"},
++	{0, 0, 0, NULL}
++};
++
++
++static const struct str_s String1_socket_AM2[] = {
++	{0x00, 0x00, 0x00, "AMD Athlon(tm) Processor LE-"},
++	{0x00, 0x00, 0x01, "AMD Sempron(tm) Processor LE-"},
++	{0x00, 0x00, 0x02, "AMD Sempron(tm) 1"},
++	{0x00, 0x00, 0x03, "AMD Athlon(tm) II 1"},
++	{0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 13"},
++	{0x00, 0x01, 0x01, "AMD Athlon(tm)"},
++	{0x00, 0x01, 0x03, "AMD Athlon(tm) II X2 2"},
++	{0x00, 0x01, 0x04, "AMD Athlon(tm) II X2 B"},
++	{0x00, 0x01, 0x05, "AMD Athlon(tm) II X2"},
++	{0x00, 0x01, 0x07, "AMD Phenom(tm) II X2 5"},
++	{0x00, 0x01, 0x0A, "AMD Phenom(tm) II X2"},
++	{0x00, 0x01, 0x0B, "AMD Phenom(tm) II X2 B"},
++	{0x00, 0x02, 0x00, "AMD Phenom(tm)"},
++	{0x00, 0x02, 0x03, "AMD Phenom(tm) II X3 B"},
++	{0x00, 0x02, 0x04, "AMD Phenom(tm) II X3"},
++	{0x00, 0x02, 0x07, "AMD Athlon(tm) II X3 4"},
++	{0x00, 0x02, 0x08, "AMD Phenom(tm) II X3 7"},
++	{0x00, 0x02, 0x0A, "AMD Athlon(tm) II X3"},
++	{0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 13"},
++	{0x00, 0x03, 0x01, "AMD Phenom(tm) FX-"},
++	{0x00, 0x03, 0x02, "AMD Phenom(tm)"},
++	{0x00, 0x03, 0x03, "AMD Phenom(tm) II X4 9"},
++	{0x00, 0x03, 0x04, "AMD Phenom(tm) II X4 8"},
++	{0x00, 0x03, 0x07, "AMD Phenom(tm) II X4 B"},
++	{0x00, 0x03, 0x08, "AMD Phenom(tm) II X4"},
++	{0x00, 0x03, 0x0A, "AMD Athlon(tm) II X4 6"},
++	{0x00, 0x03, 0x0F, "AMD Athlon(tm) II X4"},
++	{0, 0, 0, NULL}
++};
++
++static const struct str_s String2_socket_AM2[] = {
++	{0x00, 0x00, 0x00, "00"},
++	{0x00, 0x00, 0x01, "10"},
++	{0x00, 0x00, 0x02, "20"},
++	{0x00, 0x00, 0x03, "30"},
++	{0x00, 0x00, 0x04, "40"},
++	{0x00, 0x00, 0x05, "50"},
++	{0x00, 0x00, 0x06, "60"},
++	{0x00, 0x00, 0x07, "70"},
++	{0x00, 0x00, 0x08, "80"},
++	{0x00, 0x00, 0x09, "90"},
++	{0x00, 0x00, 0x09, " Processor"},
++	{0x00, 0x00, 0x09, "u Processor"},
++	{0x00, 0x01, 0x00, "00 Dual-Core Processor"},
++	{0x00, 0x01, 0x01, "00e Dual-Core Processor"},
++	{0x00, 0x01, 0x02, "00B Dual-Core Processor"},
++	{0x00, 0x01, 0x03, "50 Dual-Core Processor"},
++	{0x00, 0x01, 0x04, "50e Dual-Core Processor"},
++	{0x00, 0x01, 0x05, "50B Dual-Core Processor"},
++	{0x00, 0x01, 0x06, " Processor"},
++	{0x00, 0x01, 0x07, "e Processor"},
++	{0x00, 0x01, 0x09, "0 Processor"},
++	{0x00, 0x01, 0x0A, "0e Processor"},
++	{0x00, 0x01, 0x0B, "u Processor"},
++	{0x00, 0x02, 0x00, "00 Triple-Core Processor"},
++	{0x00, 0x02, 0x01, "00e Triple-Core Processor"},
++	{0x00, 0x02, 0x02, "00B Triple-Core Processor"},
++	{0x00, 0x02, 0x03, "50 Triple-Core Processor"},
++	{0x00, 0x02, 0x04, "50e Triple-Core Processor"},
++	{0x00, 0x02, 0x05, "50B Triple-Core Processor"},
++	{0x00, 0x02, 0x06, " Processor"},
++	{0x00, 0x02, 0x07, "e Processor"},
++	{0x00, 0x02, 0x09, "0e Processor"},
++	{0x00, 0x02, 0x0A, "0 Processor"},
++	{0x00, 0x03, 0x00, "00 Quad-Core Processor"},
++	{0x00, 0x03, 0x01, "00e Quad-Core Processor"},
++	{0x00, 0x03, 0x02, "00B Quad-Core Processor"},
++	{0x00, 0x03, 0x03, "50 Quad-Core Processor"},
++	{0x00, 0x03, 0x04, "50e Quad-Core Processor"},
++	{0x00, 0x03, 0x05, "50B Quad-Core Processor"},
++	{0x00, 0x03, 0x06, " Processor"},
++	{0x00, 0x03, 0x07, "e Processor"},
++	{0x00, 0x03, 0x09, "0e Processor"},
++	{0x00, 0x03, 0x0A, " SE"},
++	{0x00, 0x03, 0x0B, " HE"},
++	{0x00, 0x03, 0x0C, " EE"},
++	{0x00, 0x03, 0x0D, " Quad-Core Processor"},
++	{0x00, 0x03, 0x0E, "0 Processor"},
++	{0x00, 0xFF, 0x0F, ""},
++	{0, 0, 0, NULL}
++};
++
++static const struct str_s String1_socket_G34[] = {
++	{0x00, 0x07, 0x00, "AMD Opteron(tm) Processor 61"},
++	{0x00, 0x0B, 0x00, "AMD Opteron(tm) Processor 61"},
++	{0x01, 0x07, 0x01, "Embedded AMD Opteron(tm) Processor "},
++	{0, 0, 0, NULL}
++};
++
++static const struct str_s String2_socket_G34[] = {
++	{0x00, 0x07, 0x00, " HE"},
++	{0x00, 0x07, 0x01, " SE"},
++	{0x00, 0x0B, 0x00, " HE"},
++	{0x00, 0x0B, 0x01, " SE"},
++	{0x00, 0x0B, 0x0F, ""},
++	{0x01, 0x07, 0x01, " QS"},
++	{0x01, 0x07, 0x02, " KS"},
++	{0, 0, 0, NULL}
++};
++
++static const struct str_s String1_socket_C32[] = {
++	{0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"},
++	{0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"},
++	{0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "},
++	{0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "},
++	{0, 0, 0, NULL}
++};
++
++static const struct str_s String2_socket_C32[] = {
++	{0x00, 0x03, 0x00, " HE"},
++	{0x00, 0x03, 0x01, " EE"},
++	{0x00, 0x05, 0x00, " HE"},
++	{0x00, 0x05, 0x01, " EE"},
++	{0x01, 0x03, 0x01, "QS HE"},
++	{0x01, 0x03, 0x02, "LE HE"},
++	{0x01, 0x05, 0x01, "KX HE"},
++	{0x01, 0x05, 0x02, "GL EE"},
++	{0, 0, 0, NULL}
++};
++
++const char *unknown = "AMD Processor model unknown";
++const char *unknown2 = " type unknown";
++const char *sample = "AMD Engineering Sample";
++const char *thermal = "AMD Thermal Test Kit";
++
++
++static int strcpymax(char *dst, const char *src, int buflen)
++{
++	int i;
++	for (i = 0; i < buflen && src[i]; i++)
++		dst[i] = src[i];
++	if (i >= buflen)
++		i--;
++	dst[i] = 0;
++	return i;
++}
++
++
++int init_processor_name(void)
++{
++	/* variable names taken from fam10 revision guide for clarity */
++	u32 BrandId;	/* CPUID Fn8000_0001_EBX */
++	u8 String1;	/* BrandID[14:11] */
++	u8 String2;	/* BrandID[3:0] */
++	u8 Model;	/* BrandID[10:4] */
++	u8 Pg;		/* BrandID[15] */
++	u8 PkgTyp;	/* BrandID[31:28] */
++	u8 NC;		/* CPUID Fn8000_0008_ECX */
++	const char *processor_name_string = unknown;
++	char program_string[48];
++	u32 *p_program_string = (u32 *)program_string;
++	msr_t msr;
++	int i, j = 0, str2_checkNC = 1;
++	const struct str_s *str, *str2;
++
++
++	/* Find out which CPU brand it is */
++	BrandId = cpuid_ebx(0x80000001);
++	String1 = (u8)((BrandId >> 11) & 0x0F);
++	String2 = (u8)((BrandId >> 0) & 0x0F);
++	Model = (u8)((BrandId >> 4) & 0x7F);
++	Pg = (u8)((BrandId >> 15) & 0x01);
++	PkgTyp = (u8)((BrandId >> 28) & 0x0F);
++	NC = (u8)(cpuid_ecx(0x80000008) & 0xFF);
++
++	/* null the string */
++	memset(program_string, 0, sizeof(program_string));
++
++	if (!Model) {
++		processor_name_string = Pg ? thermal : sample;
++		goto done;
++	}
++
++	switch (PkgTyp) {
++	case 0:		/* F1207 */
++		str = String1_socket_F;
++		str2 = String2_socket_F;
++		str2_checkNC = 0;
++		break;
++	case 1:		/* AM2 */
++		str = String1_socket_AM2;
++		str2 = String2_socket_AM2;
++		break;
++	case 3:		/* G34 */
++		str = String1_socket_G34;
++		str2 = String2_socket_G34;
++		str2_checkNC = 0;
++		break;
++	case 5:		/* C32 */
++		str = String1_socket_C32;
++		str2 = String2_socket_C32;
++		break;
++	default:
++		goto done;
++	}
++
++	/* String1 */
++	for (i = 0; str[i].value; i++) {
++		if ((str[i].Pg == Pg) &&
++		    (str[i].NC == NC) &&
++		    (str[i].String == String1)) {
++			processor_name_string = str[i].value;
++			break;
++		}
++	}
++
++	if (!str[i].value)
++		goto done;
++
++	j = strcpymax(program_string, processor_name_string,
++		      sizeof(program_string));
++
++	/* Translate Model from 01-99 to ASCII and put it on the end.
++	 * Numbers less than 10 should include a leading zero, e.g., 09.*/
++	if (Model < 100 && j < sizeof(program_string) - 2) {
++		program_string[j++] = (Model / 10) + '0';
++		program_string[j++] = (Model % 10) + '0';
++	}
++
++	processor_name_string = unknown2;
++
++	/* String 2 */
++	for(i = 0; str2[i].value; i++) {
++		if ((str2[i].Pg == Pg) &&
++		    ((str2[i].NC == NC) || !str2_checkNC) &&
++		    (str2[i].String == String2)) {
++			processor_name_string = str2[i].value;
++			break;
++		}
++	}
++
++
++done:
++	strcpymax(&program_string[j], processor_name_string,
++		  sizeof(program_string) - j);
++
++	printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
++
++	for (i = 0; i < 6; i++) {
++		msr.lo = p_program_string[(2 * i) + 0];
++		msr.hi = p_program_string[(2 * i) + 1];
++		wrmsr_amd(0xC0010030 + i, msr);
++	}
++
++	return 0;
++}
+diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
+new file mode 100644
+index 0000000..46ccdbd
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
+@@ -0,0 +1,54 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ * Copyright (C) 2007 Advanced Micro Devices, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#include <cpu/cpu.h>
++#include <cpu/x86/msr.h>
++#include <cpu/amd/mtrr.h>
++
++#include <cbmem.h>
++
++#include "ram_calc.h"
++
++#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
++uint64_t get_uma_memory_size(uint64_t topmem)
++{
++	uint64_t uma_size = 0;
++	if (IS_ENABLED(CONFIG_GFXUMA)) {
++		/* refer to UMA Size Consideration in 780 BDG. */
++		if (topmem >= 0x40000000)	/* 1GB and above system memory */
++			uma_size = 0x10000000;	/* 256M recommended UMA */
++
++		else if (topmem >= 0x20000000)	/* 512M - 1023M system memory */
++			uma_size = 0x8000000;	/* 128M recommended UMA */
++
++		else if (topmem >= 0x10000000)	/* 256M - 511M system memory */
++			uma_size = 0x4000000;	/* 64M recommended UMA */
++	}
++
++	return uma_size;
++}
++
++void *cbmem_top(void)
++{
++	uint32_t topmem = rdmsr(TOP_MEM).lo;
++
++	return (void *) topmem - get_uma_memory_size(topmem);
++}
++#endif
+diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.h b/src/cpu/amd/family_10h-family_15h/ram_calc.h
+new file mode 100644
+index 0000000..61da328
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/ram_calc.h
+@@ -0,0 +1,25 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#ifndef _AMD_MODEL_10XXX_RAM_CALC_H_
++#define _AMD_MODEL_10XXX_RAM_CALC_H_
++
++uint64_t get_uma_memory_size(uint64_t topmem);
++
++#endif
+diff --git a/src/cpu/amd/family_10h-family_15h/update_microcode.c b/src/cpu/amd/family_10h-family_15h/update_microcode.c
+new file mode 100644
+index 0000000..51aca35
+--- /dev/null
++++ b/src/cpu/amd/family_10h-family_15h/update_microcode.c
+@@ -0,0 +1,71 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
++ * Copyright (C) 2007 Advanced Micro Devices, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.
++ */
++
++#include <stdint.h>
++#include <cpu/amd/microcode.h>
++
++struct id_mapping {
++        uint32_t orig_id;
++        uint16_t new_id;
++};
++
++static u16 get_equivalent_processor_rev_id(u32 orig_id) {
++	static const struct id_mapping id_mapping_table[] = {
++		{ 0x100f00, 0x1000 },
++		{ 0x100f01, 0x1000 },
++		{ 0x100f02, 0x1000 },
++		{ 0x100f20, 0x1020 },
++		{ 0x100f21, 0x1020 }, /* DR-B1 */
++		{ 0x100f2A, 0x1020 }, /* DR-BA */
++		{ 0x100f22, 0x1022 }, /* DR-B2 */
++		{ 0x100f23, 0x1022 }, /* DR-B3 */
++		{ 0x100f42, 0x1041 }, /* RB-C2 */
++		{ 0x100f43, 0x1043 }, /* RB-C3 */
++		{ 0x100f52, 0x1041 }, /* BL-C2 */
++		{ 0x100f62, 0x1062 }, /* DA-C2 */
++		{ 0x100f63, 0x1043 }, /* DA-C3 */
++		{ 0x100f81, 0x1081 }, /* HY-D1 */
++		{ 0x100fa0, 0x10A0 }, /* PH-E0 */
++
++		/* Array terminator */
++		{ 0xffffff, 0x0000 },
++	};
++
++	u32 new_id;
++	int i;
++
++	new_id = 0;
++
++	for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
++		if (id_mapping_table[i].orig_id == orig_id) {
++			new_id = id_mapping_table[i].new_id;
++			break;
++		}
++	}
++
++	return new_id;
++
++}
++
++void update_microcode(u32 cpu_deviceid)
++{
++	u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
++	amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
++}
+diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
+deleted file mode 100644
+index 7c47e27..0000000
+--- a/src/cpu/amd/model_10xxx/Kconfig
++++ /dev/null
+@@ -1,88 +0,0 @@
+-config CPU_AMD_MODEL_10XXX
+-	bool
+-	select ARCH_BOOTBLOCK_X86_32
+-	select ARCH_VERSTAGE_X86_32
+-	select ARCH_ROMSTAGE_X86_32
+-	select ARCH_RAMSTAGE_X86_32
+-	select SSE
+-	select SSE2
+-	select MMCONF_SUPPORT_DEFAULT
+-	select TSC_SYNC_LFENCE
+-	select UDELAY_LAPIC
+-	select HAVE_MONOTONIC_TIMER
+-	select SUPPORT_CPU_UCODE_IN_CBFS
+-	select CPU_MICROCODE_MULTIPLE_FILES
+-
+-if CPU_AMD_MODEL_10XXX
+-
+-config NUM_IPI_STARTS
+-	int
+-	default 1
+-
+-config CPU_ADDR_BITS
+-	int
+-	default 48
+-
+-config DCACHE_RAM_BASE
+-	hex
+-	default 0xc4000
+-
+-config DCACHE_RAM_SIZE
+-	hex
+-	default 0x0c000
+-
+-config DCACHE_BSP_STACK_SIZE
+-	hex
+-	default 0x2000
+-
+-config DCACHE_BSP_STACK_SLUSH
+-	hex
+-	default 0x1000
+-
+-config DCACHE_AP_STACK_SIZE
+-	hex
+-	default 0x400
+-
+-config UDELAY_IO
+-	bool
+-	default n
+-
+-config SET_FIDVID
+-	bool
+-	default y
+-
+-config MAX_PHYSICAL_CPUS
+-	int
+-	default 1
+-
+-config LIFT_BSP_APIC_ID
+-	bool
+-	default n
+-
+-if SET_FIDVID
+-config SET_FIDVID_DEBUG
+-	bool
+-	default y
+-
+-config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+-	bool
+-	default y
+-
+-config SET_FIDVID_CORE0_ONLY
+-	bool
+-	default n
+-
+-# 0: all cores
+-# 1: core 0 only
+-# 2: all but core 0
+-config SET_FIDVID_CORE_RANGE
+-	int
+-	default 0
+-
+-endif	# SET_FIDVID
+-
+-config UDELAY_LAPIC_FIXED_FSB
+-	int
+-	default 200
+-
+-endif	# CPU_AMD_MODEL_10XXX
+diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
+deleted file mode 100644
+index 5a81ab8..0000000
+--- a/src/cpu/amd/model_10xxx/Makefile.inc
++++ /dev/null
+@@ -1,14 +0,0 @@
+-romstage-y += ../../x86/mtrr/earlymtrr.c
+-ramstage-y += model_10xxx_init.c
+-ramstage-y += processor_name.c
+-
+-romstage-y += update_microcode.c
+-romstage-y += ram_calc.c
+-ramstage-y += ram_calc.c
+-ramstage-y += monotonic_timer.c
+-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
+-
+-# Microcode for Family 10h, 11h, 12h, and 14h
+-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
+-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
+-microcode_amd.bin-type := microcode
+diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+deleted file mode 100644
+index 6fd1a7e..0000000
+--- a/src/cpu/amd/model_10xxx/defaults.h
++++ /dev/null
+@@ -1,479 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2008 Advanced Micro Devices, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#include <northbridge/amd/amdmct/amddefs.h>
+-#include <cpu/amd/mtrr.h>
+-
+-/*
+- * Default MSR and errata settings.
+- */
+-static const struct {
+-	u32 msr;
+-	u32 revision;
+-	u32 platform;
+-	u32 data_lo;
+-	u32 data_hi;
+-	u32 mask_lo;
+-	u32 mask_hi;
+-} fam10_msr_default[] = {
+-	{ TOP_MEM2, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000000,
+-	  0xFFFFFFFF, 0xFFFFFFFF },
+-
+-	{ SYSCFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  3 << 21, 0x00000000,
+-	  3 << 21, 0x00000000 },	/* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
+-
+-	{ HWCR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  1 << 4, 0x00000000,
+-	  1 << 4, 0x00000000 },		/* [INVD_WBINVD]=1 */
+-
+-	{ MC4_CTL_MASK, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0xF << 19, 0x00000000,
+-	  0xF << 19, 0x00000000 },	/* [RtryHt[0..3]]=1 */
+-
+-	{ DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR,
+-	  0x00000000, 0x00000004,
+-	  0x00000000, 0x0000000C },	/* [REQ_CTR] = 1 for Server */
+-
+-	{ DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR,
+-	  0x00000000, 0x00000000,
+-	  0x00000000, 0x00000C00 },	/* Erratum 326 */
+-
+-	{ NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
+-	  0x00000000, 1 << 22,
+-	  0x00000000, 1 << 22 },	/* [ApicInitIDLo]=1 */
+-
+-	{ BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL,
+-	  1 << 29, 0x00000000,
+-	  1 << 29, 0x00000000 },	/* For Bx Smash1GPages=1 */
+-
+-	{ DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  1 << 24, 0x00000000,
+-	  1 << 24, 0x00000000 },	/* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
+-
+-	{ LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
+-	  0 << 1, 0x00000000,
+-	  1 << 1, 0x00000000 },		/* IDX_MATCH_ALL=0 */
+-
+-	{ BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
+-	  1 << 21, 0x00000000,
+-	  1 << 21, 0x00000000 },	/* Erratum #254 DR B1 BU_CFG[21]=1 */
+-
+-	{ BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
+-	  1 << 23, 0x00000000,
+-	  1 << 23, 0x00000000 },	/* Erratum #309 BU_CFG[23]=1 */
+-
+-	/* CPUID_EXT_FEATURES */
+-	{ CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
+-	  1 << 28, 0x00000000,
+-	  1 << 28, 0x00000000 },	/* [HyperThreadFeatEn]=1 */
+-
+-	{ CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC,
+-	  0x00000000, 1 << (33-32),
+-	  0x00000000, 1 << (33-32) },	/* [ExtendedFeatEn]=1 */
+-
+-	{ BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
+-	  0x00000000, 1 << (35-32),
+-	  0x00000000, 1 << (35-32) },	/* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */
+-
+-	{ OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
+-	  0x00000004, 0x00000000,
+-	  0x00000004, 0x00000000},	/* B0 or Above, OSVW_ID_Length is 0004h */
+-
+-	{ OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
+-	  0x0000000C, 0x00000000,
+-	  0x0000000C, 0x00000000},	/* Cx and Dx multiple-link processor */
+-
+-	{ BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL,
+-	  0x00000000, 1 << (50-32),
+-	  0x00000000, 1 << (50-32)},	/* D0 or Above, RdMmExtCfgQwEn*/
+-
+-	{ CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
+-	  0x00000000, 1 << (51 - 32),
+-	  0x00000000, 1 << (51 - 32)},	/* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
+-};
+-
+-
+-/*
+- * Default PCI and errata settings.
+- */
+-static const struct {
+-	u8  function;
+-	u16 offset;
+-	u32 revision;
+-	u32 platform;
+-	u32 data;
+-	u32 mask;
+-} fam10_pci_default[] = {
+-
+-	/* Function 0 - HT Config */
+-
+-	{ 0, 0x68, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x004E4800, 0x006E6800 },	/* [19:17] for 8bit APIC config,
+-	  [14:13] BufPriRel = 2h [11] RspPassPW set,
+-	  [22:21] DsNpReqLmt = 10b */
+-
+-	/* Errata 281 Workaround */
+-	{ 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
+-	  AMD_PTYPE_SVR, 0x00200000, 0x00600000 },	/* [22:21] DsNpReqLmt0 = 01b */
+-
+-	{ 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+-
+-	{ 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+-
+-	{ 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+-
+-	{ 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+-
+-	/* Link Global Retry Control Register */
+-	{ 0, 0x150, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00073900, 0x00073F00 },
+-
+-	/*  Errata 351
+-	 * System software should program the Link Extended Control Registers[LS2En]
+-	 * (F0x[18C:170][8]) to 0b for all links. System software should also
+-	 * program Link Global Extended Control Register[ForceFullT0]
+-	 * (F0x16C[15:13]) to 000b */
+-
+-	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0x00000100 },
+-
+-	/* Link Global Extended Control Register */
+-	{ 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000014, 0x0000003F },	/* [15:13] ForceFullT0 = 0b,
+-								 * Set T0Time 14h per BKDG */
+-
+-
+-	/* Function 1 - Map Init */
+-
+-	/* Before reading F1x114_x2 or F1x114_x3 software must
+-	 * initialize the registers or NB Array MCA errors may
+-	 * occur.  BIOS should initialize index 0h of F1x114_x2 and
+-	 * F1x114_x3 to prevent reads from F1x114 from generating NB
+-	 * Array MCA errors.  BKDG Doc #3116 Rev 1.07
+-	 */
+-
+-	{ 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x20000000, 0xFFFFFFFF },	/* Select extended MMIO Base */
+-
+-	{ 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0xFFFFFFFF },	/* Clear map  */
+-
+-	{ 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x30000000, 0xFFFFFFFF },	/* Select extended MMIO Base */
+-
+-	{ 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000000, 0xFFFFFFFF },	/* Clear map  */
+-
+-	/* Function 2 - DRAM Controller */
+-
+-	/* Function 3 - Misc. Control */
+-	{ 3, 0x40, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000100, 0x00000100 },	/* [8] MstrAbrtEn */
+-
+-	{ 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x4A30005C, 0x4A30005C },	/* [30] SyncOnDramAdrParErrEn = 1,
+-					   [27] NbMcaToMstCpuEn = 1,
+-					   [25] DisPciCfgCpuErrRsp = 1,
+-					   [21] SyncOnAnyErrEn = 1,
+-					   [20] SyncOnWDTEn = 1,
+-					   [6] CpuErrDis = 1,
+-					   [4] SyncPktPropDis = 1,
+-					   [3] SyncPktGenDis = 1,
+-					   [2] SyncOnUcEccEn = 1 */
+-
+-	/* XBAR buffer settings */
+-	{ 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00018052, 0x700780F7 },
+-
+-	/* Errata 281 Workaround */
+-	{ 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1),
+-	  AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
+-
+-	{ 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
+-	  0x60018051, 0x700780F7 },
+-
+-	{ 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00041153, 0x777777F7 },
+-
+-	{ 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
+-	  0x61221151, 0x777777F7 },
+-
+-	{ 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
+-	  0x00080101, 0x000F7777 },
+-
+-	{ 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00090914, 0x707FFF1F },
+-
+-	/* Errata 281 Workaround */
+-	{ 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
+-	 AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
+-
+-	{ 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
+-	  0x00070814, 0x007FFF1F },
+-
+-	{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00800756, 0x00F3FFFF },
+-
+-	{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
+-	  0x00C37756, 0x00F3FFFF },
+-
+-	{ 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
+-	  0x00000036, 0x000000FF },
+-
+-	/* Errata 281 Workaround */
+-	{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
+-	 AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
+-	 	/* [3:0] RspTok = 0001b */
+-
+-	{ 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
+-	  0x8000052A, 0xD5FFFFFF },
+-
+-	/* ACPI Power State Control Reg1 */
+-	{ 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0xE6002200, 0xFFFFFFFF },
+-
+-	/* ACPI Power State Control Reg2 */
+-	{ 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0xA0E641E6, 0xFFFFFFFF },
+-
+-	{ 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
+-	  0x00000080, 0x00000080 },	/* [7] PSIVidEnable */
+-
+-	{ 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
+-	  0x00002800, 0x000003800 },	/* [13:11] PllLockTime = 5 */
+-
+-	{ 3, 0xA0, (AMD_FAM10_ALL & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
+-	  0x00000800, 0x000003800 },	/* [13:11] PllLockTime = 1 */
+-
+-	/* Reported Temp Control Register */
+-	{ 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000080, 0x00000080 },	/* [7] TempSlewDnEn = 1 */
+-
+-	/* Clock Power/Timing Control 0 Register */
+-	{ 3, 0xD4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0xC0000F00, 0xF0000F00 },	/*  [31] NbClkDivApplyAll = 1,
+-		[30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
+-
+-	/* Clock Power/Timing Control 1 Register */
+-	{ 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x03000016, 0x0F000077 },	/* [6:4] VSRampTime = 1,
+-		[2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */
+-
+-
+-	/* Clock Power/Timing Control 2 Register */
+-	{ 3, 0xDC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00005000, 0x00007000 },	/* [14:12] NbsynPtrAdj = 5 */
+-
+-
+-	/* Extended NB MCA Config Register */
+-	{ 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x007003E2, 0x007003E2 },	/* [22:20] = SyncFloodOn_Err = 7,
+-					   [9] SyncOnUncNbAryEn = 1 ,
+-					   [8] SyncOnProtEn = 1,
+-					   [7] SyncFloodOnTgtAbtErr = 1,
+-					   [6] SyncFloodOnDatErr = 1,
+-					   [5] DisPciCfgCpuMstAbtRsp = 1,
+-					   [1] SyncFloodOnUsPwDataErr = 1 */
+-
+-	/* errata 346 - Fam10 C2, C3
+-	 *  System software should set F3x188[22] to 1b. */
+-	{ 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
+-	  0x00400000, 0x00400000 },
+-
+-	/* L3 Control Register */
+-	{ 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00001000, 0x00001000 },	/* [12] = L3PrivReplEn */
+-
+-	/* IBS Control Register */
+-	{ 3, 0x1CC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+-	  0x00000100, 0x00000100 },	/* [8] = LvtOffsetVal */
+-};
+-
+-
+-/*
+- * Default HyperTransport Phy and errata settings.
+- */
+-static const struct {
+-	u16 htreg;	/* HT Phy Register index */
+-	u32 revision;
+-	u32 platform;
+-	u32 linktype;
+-	u32 data;
+-	u32 mask;
+-} fam10_htphy_default[] = {
+-
+-	/* Errata 344 - Fam10 C2/C3, D0/D1
+-	 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
+-	{ 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-
+-	{ 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-
+-	/* Errata 354 - Fam10 C2, C3
+-	 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
+-	{ 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-
+-	{ 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-	{ 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00000040, 0x00000040 },
+-
+-	/* Errata 327 - Fam10 C2/C3, D0/D1
+-	 * BIOS should set the Link Phy Impedance Register[RttCtl]
+-	 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
+-	 * Link Phy Impedance Register[RttIndex]
+-	 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
+-	{ 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x40040000, 0xe01F0000 },
+-	{ 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x40040000, 0xe01F0000 },
+-
+-	{ 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00004000, 0x00006000 },	/* HT_PHY_DLL_REG */
+-
+-	{ 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00004000, 0x00006000 },	/* HT_PHY_DLL_REG */
+-
+-	{ 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00004400, 0x00006400 },	/* HT_PHY_DLL_REG */
+-
+-	{ 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x00004400, 0x00006400 },	/* HT_PHY_DLL_REG */
+-
+-	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+-	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
+-					   completeness */
+-
+-	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+-	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
+-					   completeness */
+-
+-	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
+-	  0x0000006D, 0x000000FF },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
+-
+-	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
+-	  0x0000006D, 0x000000FF }, 	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
+-
+-	/* Link Phy Receiver Loop Filter Registers */
+-	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+-	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
+-					   [21:14] LfcMin = 10h */
+-
+-	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+-	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
+-					   [21:14] LfcMin = 10h */
+-
+-	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
+-	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
+-					   [21:14] LfcMin = 08h */
+-
+-	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
+-	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
+-					   [21:14] LfcMin = 08h */
+-
+-	{ 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+-	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
+-								   [20:16] RttIndex = 04h */
+-};
+diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
+deleted file mode 100644
+index 99ffcc8..0000000
+--- a/src/cpu/amd/model_10xxx/fidvid.c
++++ /dev/null
+@@ -1,1049 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-/*
+- * This file initializes the CPU cores for voltage and frequency settings
+- * in the different power states.
+- */
+-/*
+-
+-checklist (functions are in this file if no source file named)
+-Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
+-
+-2.4.2.6 Requirements for p-states
+-
+-1.- F3x[84:80] According to table 100 : prep_fid_change
+-
+-2.- COF/VID :
+-     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
+-               fixPsNbVidBeforeWR(...)
+-     2.4.2.9.1 Step 8 enable_fid_change
+-               We do this for all nodes, I don't understand BKDG 100% on
+-               whether this is or isn't meant by "on the local
+-               processor". Must be OK.
+-     2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
+-     2.4.2.9.1 Steps 11-12 init_fidvid_stage2
+-     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
+-               needs specific circuitry.
+-
+-3.-  2.4.2.7 dualPlaneOnly(dev)
+-
+-4.-  2.4.2.8 applyBoostFIDOffset(dev)
+-
+-5.-  enableNbPState1(dev)
+-
+-6.- 2.4.1.7
+-    a) UpdateSinglePlaneNbVid()
+-    b) setVSRamp(), called from  prep_fid_change
+-    c) prep_fid_change
+-    d) improperly, for lack of voltage regulator details?,
+-        F3xA0[PsiVidEn] in defaults.h
+-        F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
+-
+-7.- TODO (Core Performance Boost is only available in revision E cpus, and we
+-          don't seem to support those yet, at least they don't have any
+-          constant in amddefs.h )
+-
+-8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
+-    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
+-    if the warm reset is issued by coreboot to update NbFid. So it is required
+-    or not ? How can I tell who issued warm reset ?
+-    Coreboot transitions to P0 instead, which is not recommended, and does
+-    not follow 2.4.2.15.2 to do so.
+-
+-9.- TODO Requires information on current delivery capability
+-    (depends on mainboard and maybe power supply ?). One might use a config
+-    option with the maximum number of Amperes that the board can deliver to CPU.
+-
+-10.- [Multiprocessor] TODO 2.4.2.12
+-     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
+-     but not sure this is what is meant by "Determine the valid set of
+-     P-states based on enabled P-states indicated
+-     in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
+-
+-11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
+-
+-12.- generate ACPI for p-states.
+-     generated in powernow_acpi.c amd_generate_powernow()
+-
+-"must also be completed"
+-
+-a.-  PllLockTime set in ruleset in defaults.h
+-     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
+-     any two enabled P-states", but since it does not say "only if"
+-     I guess it is safe to do it always.
+-
+-b.-  prep_fid_change(...)
+-
+- */
+-
+-#if CONFIG_SET_FIDVID
+-
+-#include <northbridge/amd/amdht/AsPsDefs.h>
+-
+-static inline void print_debug_fv(const char *str, u32 val)
+-{
+-#if CONFIG_SET_FIDVID_DEBUG
+-	printk(BIOS_DEBUG, "%s%x\n", str, val);
+-#endif
+-}
+-
+-static inline void print_debug_fv_8(const char *str, u8 val)
+-{
+-#if CONFIG_SET_FIDVID_DEBUG
+-	printk(BIOS_DEBUG, "%s%02x\n", str, val);
+-#endif
+-}
+-
+-static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
+-{
+-#if CONFIG_SET_FIDVID_DEBUG
+-	printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
+-#endif
+-}
+-
+-struct fidvid_st {
+-	u32 common_fid;
+-};
+-
+-static void enable_fid_change(u8 fid)
+-{
+-	u32 dword;
+-	u32 nodes;
+-	device_t dev;
+-	int i;
+-
+-	nodes = get_nodes();
+-
+-	for (i = 0; i < nodes; i++) {
+-		dev = NODE_PCI(i, 3);
+-		dword = pci_read_config32(dev, 0xd4);
+-		dword &= ~0x1F;
+-		dword |= (u32) fid & 0x1F;
+-		dword |= 1 << 5;	// enable
+-		pci_write_config32(dev, 0xd4, dword);
+-		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
+-		       dword);
+-	}
+-}
+-
+-static void applyBoostFIDOffset(  device_t dev ) {
+-  // BKDG 2.4.2.8
+-  // revision E only, but E is apparently not supported yet, therefore untested
+-  if ((cpuid_edx(0x80000007) & CPB_MASK)
+-      &&  ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) {
+-      u32 core =  get_node_core_id_x().coreid;
+-      u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
+-      msr_t msr =  rdmsr(PS_REG_BASE);
+-      u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
+-      cpuFid = cpuFid + asymetricBoostThisCore;
+-      msr.lo &=   ~PS_CPU_FID_MASK;
+-      msr.lo |= cpuFid ;
+-      wrmsr(PS_REG_BASE , msr);
+-
+-  }
+-}
+-
+-static void enableNbPState1( device_t dev ) {
+-  u32 cpuRev =  mctGetLogicalCPUID(0xFF);
+-  if (cpuRev & AMD_FAM10_C3) {
+-    u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
+-    if ( nbPState){
+-      u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
+-      u32 i;
+-      for (i = nbPState; i < NM_PS_REG; i++) {
+-         msr_t msr =  rdmsr(PS_REG_BASE + i);
+-         if (msr.hi &  PS_EN_MASK ) {
+-            msr.hi |= NB_DID_M_ON;
+-            msr.lo &= NB_VID_MASK_OFF;
+-	    msr.lo |= ( nbVid1 << NB_VID_POS);
+-	    wrmsr(PS_REG_BASE + i, msr);
+-	 }
+-      }
+-    }
+-  }
+-}
+-
+-static u8 setPStateMaxVal( device_t dev ) {
+-      u8 i,maxpstate=0;
+-      for (i = 0; i < NM_PS_REG; i++) {
+-         msr_t msr =  rdmsr(PS_REG_BASE + i);
+-         if (msr.hi & PS_IDD_VALUE_MASK) {
+-	   msr.hi |= PS_EN_MASK ;
+-	     wrmsr(PS_REG_BASE + i, msr);
+-	 }
+-         if (msr.hi & PS_EN_MASK) {
+-	   maxpstate = i;
+-	 }
+-      }
+-      //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
+-      u32 reg = pci_read_config32(dev, CPTC2);
+-      reg &= PS_MAX_VAL_MASK;
+-      reg |= (maxpstate << PS_MAX_VAL_POS);
+-      pci_write_config32(dev, CPTC2,reg);
+-      return maxpstate;
+-}
+-
+-static void dualPlaneOnly(  device_t dev ) {
+-  // BKDG 2.4.2.7
+-
+-  u32 cpuRev =  mctGetLogicalCPUID(0xFF);
+-  if ((mctGetProcessorPackageType() ==  AMD_PKGTYPE_AM3_2r2)
+-      && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E
+-    if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK)
+-	 && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){
+-      if (cpuid_edx(0x80000007) & CPB_MASK) {
+-          // revision E only, but E is apparently not supported yet, therefore untested
+-         msr_t minPstate = rdmsr(0xC0010065);
+-         wrmsr(0xC0010065, rdmsr(0xC0010068) );
+-         wrmsr(0xC0010068,minPstate);
+-      } else {
+-	 msr_t msr;
+-         msr.lo=0; msr.hi=0;
+-         wrmsr(0xC0010064, rdmsr(0xC0010068) );
+-         wrmsr(0xC0010068, msr );
+-      }
+-
+-      //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
+-      u8 maxpstate = setPStateMaxVal(dev);
+-
+-      u32 reg = pci_read_config32(dev, HTC_REG);
+-      reg &= HTC_PS_LMT_MASK;
+-      reg |= (maxpstate << PS_LIMIT_POS);
+-      pci_write_config32(dev, HTC_REG,reg);
+-
+-    }
+-  }
+-}
+-
+-static int vidTo100uV(u8 vid)
+-{// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV
+- // BKDG #31116 rev 3.48 2.4.1.6
+-  int voltage;
+-  if (vid >= 0x7c) {
+-    voltage = 0;
+-  } else {
+-    voltage = (15500 - (125*vid));
+-  }
+-  return voltage;
+-}
+-
+-static void setVSRamp(device_t dev) {
+-	/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSRampTime]
+-         * If this field accepts 8 values between 10 and 500 us why
+-         * does page 324 say "BIOS should set this field to 001b."
+-         * (20 us) ?
+-         * Shouldn't it depend on the voltage regulators, mainboard
+-         * or something ?
+-         */
+-        u32 dword;
+-	dword = pci_read_config32(dev, 0xd8);
+-	dword &= VSRAMP_MASK;
+-	dword |= VSRAMP_VALUE;
+-	pci_write_config32(dev, 0xd8, dword);
+-}
+-
+-static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
+-{
+-	u8 pviModeFlag;
+-	u8 highVoltageVid, lowVoltageVid, bValue;
+-	u16 minimumSlamTime;
+-	u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 };	/* Reg settings scaled by 100 */
+-	u32 dtemp;
+-	msr_t msr;
+-
+-	/* This function calculates the VsSlamTime using the range of possible
+-	 * voltages instead of a hardcoded 200us.
+-         * Note: his function is called only from prep_fid_change,
+-         * and that from init_cpus.c finalize_node_setup()
+-         * (after set AMD MSRs and init ht )
+-	 */
+-
+-        /* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSSlamTime] */
+-	/* Calculate Slam Time
+-	 * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV
+-	 * In our case, we will scale the values by 100 to avoid
+-	 * decimals.
+-	 */
+-
+-	/* Determine if this is a PVI or SVI system */
+-	dtemp = pci_read_config32(dev, 0xA0);
+-
+-	if (dtemp & PVI_MODE)
+-		pviModeFlag = 1;
+-	else
+-		pviModeFlag = 0;
+-
+-	/* Get P0's voltage */
+-        /* MSRC001_00[68:64] are not programmed yet when called from
+-	   prep_fid_change, one might use F4x1[F0:E0] instead, but
+-	   theoretically MSRC001_00[68:64] are equal to them after
+-	   reset. */
+-	msr = rdmsr(0xC0010064);
+-	highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
+-        if (!(msr.hi & 0x80000000)) {
+-  	    printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");
+-            highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0)
+-                                     >> PS_CPU_VID_SHFT) & 0x7F);
+-	}
+-
+-	/* If SVI, we only care about CPU VID.
+-	 * If PVI, determine the higher voltage b/t NB and CPU
+-	 */
+-	if (pviModeFlag) {
+-		bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
+-		if (highVoltageVid > bValue)
+-			highVoltageVid = bValue;
+-	}
+-
+-	/* Get PSmax's index */
+-	msr = rdmsr(0xC0010061);
+-	bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
+-
+-	/* Get PSmax's VID */
+-	msr = rdmsr(0xC0010064 + bValue);
+-	lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
+-        if (!(msr.hi & 0x80000000)) {
+-	    printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue);
+-            lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4))
+-                                     >> PS_CPU_VID_SHFT) & 0x7F);
+-	}
+-
+-	/* If SVI, we only care about CPU VID.
+-	 * If PVI, determine the higher voltage b/t NB and CPU
+-         * BKDG 2.4.1.7 (a)
+- 	 */
+-	if (pviModeFlag) {
+-		bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
+-		if (lowVoltageVid > bValue)
+-			lowVoltageVid = bValue;
+-	}
+-
+-	/* Get AltVID */
+-	dtemp = pci_read_config32(dev, 0xDC);
+-	bValue = (u8) (dtemp & BIT_MASK_7);
+-
+-	/* Use the VID with the lowest voltage (higher VID) */
+-	if (lowVoltageVid < bValue)
+-		lowVoltageVid = bValue;
+-
+-        u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB;
+-	minimumSlamTime =  (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */
+-
+-
+-	/* Now round up to nearest register setting.
+-	 * Note that if we don't find a value, we
+-	 * will fall through to a value of 7
+-	 */
+-	for (bValue = 0; bValue < 7; bValue++) {
+-		if (minimumSlamTime <= vSlamTimes[bValue])
+-			break;
+-	}
+-
+-	/* Apply the value */
+-	dtemp = pci_read_config32(dev, 0xD8);
+-	dtemp &= VSSLAM_MASK;
+-	dtemp |= bValue;
+-	pci_write_config32(dev, 0xd8, dtemp);
+-}
+-
+-static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
+-        u8 link0isGen3 = 0;
+-        u8 offset;
+-        if (AMD_CpuFindCapability(node, 0, &offset)) {
+-	  link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
+-	}
+-        /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
+-           S1g3 in link Gen3 mode, but I don't know how to tell
+-           package S1g3 from S1g4 */
+-	if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
+-           && link0isGen3) {
+-	  return 5 ; /* divide clk by 128*/
+-        } else {
+-	  return 4 ; /* divide clk by 16 */
+-        }
+-}
+-
+-
+-static u32 power_up_down(int node, u8 procPkg) {
+-       u32 dword=0;
+-        /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
+-        u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2)
+-                             || (procPkg == AMD_PKGTYPE_S1gX)
+-                             || (procPkg == AMD_PKGTYPE_ASB2));
+-
+-        if (singleLinkFlag) {
+-	  /*
+-           * PowerStepUp=01000b - 50nS
+-	   * PowerStepDown=01000b - 50ns
+-	   */
+-	  dword |= PW_STP_UP50 | PW_STP_DN50;
+-	} else {
+-          u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
+-          u32 isocEn = 0;
+-          int j;
+-	  for(j=0 ; (j<4) && (!isocEn) ; j++ ) {
+-	    u8 offset;
+-	    if (AMD_CpuFindCapability(node, j, &offset)) {
+-	      isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
+-	    }
+-          }
+-
+-          if (dispRefModeEn || isocEn) {
+-        	dword |= PW_STP_UP50 | PW_STP_DN50 ;
+-          } else {
+-		/* get number of cores for PowerStepUp & PowerStepDown in server
+-		   1 core - 400nS  - 0000b
+-		   2 cores - 200nS - 0010b
+-		   3 cores - 133nS -> 100nS - 0011b
+-		   4 cores - 100nS - 0011b
+-		 */
+-		switch (get_core_num_in_bsp(node)) {
+-		case 0:
+-			dword |= PW_STP_UP400 | PW_STP_DN400;
+-			break;
+-		case 1:
+-		case 2:
+-			dword |= PW_STP_UP200 | PW_STP_DN200;
+-			break;
+-		case 3:
+-			dword |= PW_STP_UP100 | PW_STP_DN100;
+-			break;
+-		default:
+-			dword |= PW_STP_UP100 | PW_STP_DN100;
+-			break;
+-		}
+-	  }
+-	}
+-        return dword;
+-}
+-
+-static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
+-       	device_t dev = NODE_PCI(node, 3);
+-
+-	/* Program fields in Clock Power/Control register0 (F3xD4) */
+-
+-	/* set F3xD4 Clock Power/Timing Control 0 Register
+-	 * NbClkDidApplyAll=1b
+-	 * NbClkDid=100b or 101b
+-	 * PowerStepUp= "platform dependent"
+-	 * PowerStepDown= "platform dependent"
+-	 * LinkPllLink=01b
+-	 * ClkRampHystCtl=HW default
+-         * ClkRampHystSel=1111b
+-	 */
+-        u32 dword= pci_read_config32(dev, 0xd4);
+-	dword &= CPTC0_MASK;
+-        dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL;
+-        dword |= (nb_clk_did(node,cpuRev,procPkg) <<  NB_CLKDID_SHIFT);
+-
+-        dword |= power_up_down(node, procPkg);
+-
+-	pci_write_config32(dev, 0xd4, dword);
+-
+-}
+-
+-static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
+-	/* check PVI/SVI */
+-	u32 dword = pci_read_config32(dev, 0xa0);
+-
+-	/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xA0[VSSlamVidMod] */
+-	/* PllLockTime and PsiVidEn set in ruleset in defaults.h */
+-	if (dword & PVI_MODE) {	/* PVI */
+-		/* set slamVidMode to 0 for PVI */
+-		dword &= VID_SLAM_OFF ;
+-	} else {	/* SVI */
+-		/* set slamVidMode to 1 for SVI */
+-		dword |= VID_SLAM_ON;
+-	}
+-        /* set the rest of A0 since we're at it... */
+-
+-	if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
+-		dword |= NB_PSTATE_FORCE_ON;
+-	} // else should we clear it ?
+-
+-
+-        if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
+-		dword |= BP_INS_TRI_EN_ON ;
+-	}
+-
+-	   /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
+-        #if CONFIG_SVI_HIGH_FREQ
+-	if (cpuRev & AMD_FAM10_C3) {
+-		dword |= SVI_HIGH_FREQ_ON;
+-	}
+-	#endif
+-	pci_write_config32(dev, 0xa0, dword);
+-}
+-
+-static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
+-	/* Note the following settings are additional from the ported
+-	 * function setFidVidRegs()
+-	 */
+-        /* adjust FIFO between nb and core clocks to max allowed
+-           values (min latency) */
+-	u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK;
+-        u8 nbSynPtrAdj;
+-	if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) )
+-	    || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0)))  {
+-	  nbSynPtrAdj = 5;
+-	} else {
+-          nbSynPtrAdj = 6;
+-	}
+-
+-	u32 dword = pci_read_config32(dev, 0xDc);
+-        dword &= ~ NB_SYN_PTR_ADJ_MASK;
+-	dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS;
+-        /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */
+-	pci_write_config32(dev, 0xdc, dword);
+-}
+-
+-static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
+-                /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
+-        u32 dword;
+-	u32 c1= 1;
+-        if (cpuRev & (AMD_DR_Bx)) {
+-            // will coreboot ever enable cache scrubbing ?
+-            // if it does, will it be enough to check the current state
+-            // or should we configure for what we'll set up later ?
+-            dword = pci_read_config32(dev, 0x58);
+-            u32 scrubbingCache = dword &
+-	                        ( (0x1F << 16) // DCacheScrub
+-		 	          | (0x1F << 8) ); // L2Scrub
+- 	    if (scrubbingCache) {
+-	        c1 = 0x80;
+-	    } else {
+-	        c1 = 0xA0;
+-	    }
+-	} else { // rev C or later
+-	    // same doubt as cache scrubbing: ok to check current state ?
+-            dword = pci_read_config32(dev, 0xDC);
+-            u32 cacheFlushOnHalt = dword & (7 << 16);
+-            if (!cacheFlushOnHalt) {
+-       	       c1 = 0x80;
+-       	    }
+-       	}
+-       	dword = (c1 << 24) | (0xE641E6);
+-	pci_write_config32(dev, 0x84, dword);
+-
+-
+-        /* FIXME: BKDG Table 100 says if the link is at a Gen1
+-frequency and the chipset does not support a 10us minimum LDTSTOP
+-assertion time, then { If ASB2 && SVI then smaf001 = F6h else
+-smaf001=87h. } else ...  I hardly know what it means or how to check
+-it from here, so I bluntly assume it is false and code here the else,
+-which is easier  */
+-
+-        u32 smaf001 = 0xE6;
+-        if (cpuRev & AMD_DR_Bx ) {
+-	    smaf001 = 0xA6;
+-        } else {
+-            #if CONFIG_SVI_HIGH_FREQ
+-                if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
+-		       smaf001 = 0xF6;
+-                }
+-            #endif
+-        }
+-        u32 fidvidChange = 0;
+-        if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX))
+-		    || (cpuRev & AMD_RB_C3) ) {
+-                       fidvidChange=0x0B;
+-        }
+-	dword = (0xE6 << 24) | (fidvidChange << 16)
+-                        | (smaf001 << 8) | 0x81;
+-	pci_write_config32(dev, 0x80, dword);
+-}
+-
+-static void prep_fid_change(void)
+-{
+-        u32 dword;
+-	u32 nodes;
+-	device_t dev;
+-	int i;
+-
+-	/* This needs to be run before any Pstate changes are requested */
+-
+-	nodes = get_nodes();
+-
+-	for (i = 0; i < nodes; i++) {
+-		printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i);
+-		dev = NODE_PCI(i, 3);
+-                u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
+-	        u8 procPkg =  mctGetProcessorPackageType();
+-
+-		setVSRamp(dev);
+-		/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSSlamTime] */
+-		/* Figure out the value for VsSlamTime and program it */
+-		recalculateVsSlamTimeSettingOnCorePre(dev);
+-
+-		config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
+-
+-                config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
+-		config_nb_syn_ptr_adj(dev,cpuRev);
+-
+-		config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
+-
+-		dword = pci_read_config32(dev, 0x80);
+-		printk(BIOS_DEBUG, "  F3x80: %08x\n", dword);
+-		dword = pci_read_config32(dev, 0x84);
+-		printk(BIOS_DEBUG, "  F3x84: %08x\n", dword);
+-		dword = pci_read_config32(dev, 0xD4);
+-		printk(BIOS_DEBUG, "  F3xD4: %08x\n", dword);
+-		dword = pci_read_config32(dev, 0xD8);
+-		printk(BIOS_DEBUG, "  F3xD8: %08x\n", dword);
+-		dword = pci_read_config32(dev, 0xDC);
+-		printk(BIOS_DEBUG, "  F3xDC: %08x\n", dword);
+-	}
+-}
+-
+-static void waitCurrentPstate(u32 target_pstate){
+-  msr_t initial_msr = rdmsr(TSC_MSR);
+-  msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
+-  msr_t tsc_msr;
+-  u8 timedout ;
+-
+-  /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
+-   * P1 that is a copy of P0, therefore has the same NB DID but the
+-   * TSC will count twice per tick, so we have to wait for twice the
+-   * count to achieve the desired timeout. But I'm likely to
+-   * misunderstand this...
+-   */
+-  u32 corrected_timeout = (    (pstate_msr.lo==1)
+-			    && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
+-                          WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT  ;
+-  msr_t timeout;
+-
+-  timeout.lo = initial_msr.lo + corrected_timeout ;
+-  timeout.hi = initial_msr.hi;
+-  if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
+-     timeout.hi++;
+-  }
+-
+-  // assuming TSC ticks at 1.25 ns per tick (800 MHz)
+-  do {
+-      pstate_msr = rdmsr(CUR_PSTATE_MSR);
+-      tsc_msr = rdmsr(TSC_MSR);
+-      timedout = (tsc_msr.hi > timeout.hi)
+-        	|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
+-  } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
+-
+-  if (pstate_msr.lo != target_pstate) {
+-    msr_t limit_msr = rdmsr(0xc0010061);
+-    printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo);
+-
+-    do { // should we just go on instead ?
+-      pstate_msr = rdmsr(CUR_PSTATE_MSR);
+-    } while ( pstate_msr.lo != target_pstate  ) ;
+-  }
+-}
+-
+-static void set_pstate(u32 nonBoostedPState) {
+-  	msr_t msr;
+-
+-	// Transition P0 for calling core.
+-	msr = rdmsr(0xC0010062);
+-
+-	msr.lo = nonBoostedPState;
+-	wrmsr(0xC0010062, msr);
+-
+-	/* Wait for P0 to set. */
+-        waitCurrentPstate(nonBoostedPState);
+-}
+-
+-
+-
+-
+-static void UpdateSinglePlaneNbVid(void)
+-{
+-	u32 nbVid, cpuVid;
+-	u8 i;
+-	msr_t msr;
+-
+-	/* copy higher voltage (lower VID) of NBVID & CPUVID to both */
+-	for (i = 0; i < 5; i++) {
+-		msr = rdmsr(PS_REG_BASE + i);
+-		nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
+-		cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
+-
+-		if (nbVid != cpuVid) {
+-			if (nbVid > cpuVid)
+-				nbVid = cpuVid;
+-
+-			msr.lo = msr.lo & PS_BOTH_VID_OFF;
+-			msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
+-			msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
+-			wrmsr(PS_REG_BASE + i, msr);
+-		}
+-	}
+-}
+-
+-static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
+- {
+- 	msr_t msr;
+- 	u8 startup_pstate;
+-
+- 	/* This function sets NbVid before the warm reset.
+- 	 *       Get StartupPstate from MSRC001_0071.
+-	 *       Read Pstate register pointed by [StartupPstate].
+- 	 *       and copy its content to P0 and P1 registers.
+- 	 *       Copy newNbVid to P0[NbVid].
+- 	 *       transition to P1 on all cores,
+- 	 *       then transition to P0 on core 0.
+- 	 *       Wait for MSRC001_0063[CurPstate] = 000b on core 0.
+-         * see BKDG rev 3.48  2.4.2.9.1 BIOS NB COF and VID Configuration
+-         *                              for SVI and Single-Plane PVI Systems
+- 	 */
+-
+- 	msr = rdmsr(0xc0010071);
+-	startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
+-
+-	/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for
+-	 * this node in P0.  Then transition to P1 for corex and P0
+-	 * for core0.  These setting will be cleared by the warm reset
+-	 */
+-	msr = rdmsr(0xC0010064 + startup_pstate);
+-	wrmsr(0xC0010065, msr);
+-	wrmsr(0xC0010064, msr);
+-
+-        /* missing step 2 from BDKG , F3xDC[PstateMaxVal] =
+-         * max(1,F3xDC[PstateMaxVal] ) because it would take
+-         * synchronization between cores and we don't think
+-         * PstatMaxVal is going to be 0 on cold reset anyway ?
+-	 */
+-        if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) {
+-  	   printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
+-	};
+-
+-	msr.lo &= ~0xFE000000;	// clear nbvid
+-	msr.lo |= (newNbVid << 25);
+-	wrmsr(0xC0010064, msr);
+-
+-	if (pviMode) { /* single plane*/
+-	  UpdateSinglePlaneNbVid();
+-        }
+-
+-	// Transition to P1 for all APs and P0 for core0.
+-        set_pstate(1);
+-
+-	if (coreid == 0) {
+-             set_pstate(0);
+- 	}
+-
+-	/* missing step 7 (restore PstateMax to 0 if needed) because
+-	 * we skipped step 2
+-	 */
+-
+-}
+-
+-static u32 needs_NB_COF_VID_update(void)
+-{
+-	u8 nb_cof_vid_update;
+-	u8 nodes;
+-	u8 i;
+-
+-	/* If any node has nb_cof_vid_update set all nodes need an update. */
+-	nodes = get_nodes();
+-	nb_cof_vid_update = 0;
+-	for (i = 0; i < nodes; i++) {
+-                u32 cpuRev = mctGetLogicalCPUID(i) ;
+-                u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D));
+-		if (nbCofVidUpdateDefined
+-                    && (pci_read_config32(NODE_PCI(i, 3), 0x1FC)
+-                        & NB_COF_VID_UPDATE_MASK)) {
+-			nb_cof_vid_update = 1;
+-			break;
+-		}
+-	}
+-	return nb_cof_vid_update;
+-}
+-
+-static u32 init_fidvid_core(u32 nodeid, u32 coreid)
+-{
+-	device_t dev;
+-	u32 vid_max;
+-	u32 fid_max = 0;
+-	u8 nb_cof_vid_update = needs_NB_COF_VID_update();
+-	u8 pvimode;
+-	u32 reg1fc;
+-
+-	/* Steps 1-6 of BIOS NB COF and VID Configuration
+-	 * for SVI and Single-Plane PVI Systems. BKDG 2.4.2.9 #31116 rev 3.48
+-	 */
+-
+-	dev = NODE_PCI(nodeid, 3);
+-	pvimode = pci_read_config32(dev, PW_CTL_MISC) & PVI_MODE;
+-	reg1fc = pci_read_config32(dev, 0x1FC);
+-
+-	if (nb_cof_vid_update) {
+-                vid_max = (reg1fc &  SINGLE_PLANE_NB_VID_MASK ) >>  SINGLE_PLANE_NB_VID_SHIFT ;
+-	        fid_max = (reg1fc &  SINGLE_PLANE_NB_FID_MASK ) >>  SINGLE_PLANE_NB_FID_SHIFT ;
+-
+-	        if (!pvimode) { /* SVI, dual power plane */
+-         		vid_max = vid_max - ((reg1fc &  DUAL_PLANE_NB_VID_OFF_MASK ) >>  DUAL_PLANE_NB_VID_SHIFT );
+-			fid_max = fid_max +  ((reg1fc &  DUAL_PLANE_NB_FID_OFF_MASK ) >>  DUAL_PLANE_NB_FID_SHIFT );
+-		}
+-		/* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
+-		fixPsNbVidBeforeWR(vid_max, coreid,dev,pvimode);
+-
+-		/* fid setup is handled by the BSP at the end. */
+-
+-	} else {	/* ! nb_cof_vid_update */
+-		/* Use max values */
+-		if (pvimode)
+-			UpdateSinglePlaneNbVid();
+-	}
+-
+-	return ((nb_cof_vid_update << 16) | (fid_max << 8));
+-
+-}
+-
+-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
+-{
+-	u32 send;
+-
+-	printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
+-
+-        send = init_fidvid_core(nodeid,coreid);
+-	send |= (apicid << 24);	// ap apicid
+-
+-	// Send signal to BSP about this AP max fid
+-	// This also indicates this AP is ready for warm reset (if required).
+-	lapic_write(LAPIC_MSG_REG, send | F10_APSTATE_RESET);
+-}
+-
+-static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
+-{
+-	u32 fidmax;
+-	u32 fidmax_new;
+-
+-	fidmax = (fid_packed >> 8) & 0xFF;
+-
+-	fidmax_new = (fid_packed_new >> 8) & 0xFF;
+-
+-	if (fidmax > fidmax_new) {
+-		fidmax = fidmax_new;
+-	}
+-
+-	fid_packed &= 0xFF << 16;
+-	fid_packed |= (fidmax << 8);
+-	fid_packed |= fid_packed_new & (0xFF << 16);	// set nb_cof_vid_update
+-
+-	return fid_packed;
+-}
+-
+-static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
+-{
+-	u32 readback = 0;
+-	u32 timeout = 1;
+-
+-	struct fidvid_st *fvp = gp;
+-	int loop;
+-
+-	print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
+-
+-	loop = 100000;
+-	while (--loop > 0) {
+-		if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
+-			continue;
+-		if ((readback & 0x3f) == 1) {
+-			timeout = 0;
+-			break;	/* target ap is in stage 1 */
+-		}
+-	}
+-
+-	if (timeout) {
+-		printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
+-		       __func__, ap_apicid);
+-		return;
+-	}
+-
+-	print_debug_fv("\treadback = ", readback);
+-
+-	fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
+-
+-	print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
+-
+-}
+-
+-static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
+-{
+-	msr_t msr;
+-	u8 i;
+-	u8 StartupPstate;
+-
+-	/* BKDG 2.4.2.9.1 11-12
+-         * This function copies newNbVid to NbVid bits in P-state
+-	 * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of
+-	 * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in
+-	 * P-state Registers[4:0] if its IddValue!=0 in case of
+-	 * NbVidUpdatedAll=1. Then transition to StartPstate.
+-	 */
+-
+-	/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
+-	for (i = 0; i < 5; i++) {
+-		msr = rdmsr(0xC0010064 + i);
+-		/*  NbDid (bit 22 of P-state Reg) == 0  or NbVidUpdatedAll = 1 */
+-		if (   (msr.hi & PS_IDD_VALUE_MASK)
+-                    && (msr.hi & PS_EN_MASK)
+-                    &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) {
+-			msr.lo &= PS_NB_VID_M_OFF;
+-			msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT;
+-			wrmsr(0xC0010064 + i, msr);
+-		}
+-	}
+-
+-        /* Not documented. Would overwrite Nb_Vids just copied
+-         * should we just update cpu_vid or nothing at all ?
+-	 */
+-	if (pviMode) { //single plane
+-            UpdateSinglePlaneNbVid();
+-	}
+-	/* For each core in the system, transition all cores to StartupPstate */
+-	msr = rdmsr(0xC0010071);
+-	StartupPstate = msr.hi & 0x07;
+-
+-	/* Set and wait for StartupPstate to set. */
+-        set_pstate(StartupPstate);
+-
+-}
+-
+-static void finalPstateChange(void)
+-{
+-	/* Enable P0 on all cores for best performance.
+-	 * Linux can slow them down later if need be.
+-	 * It is safe since they will be in C1 halt
+-	 * most of the time anyway.
+-	 */
+-	set_pstate(0);
+-}
+-
+-static void init_fidvid_stage2(u32 apicid, u32 nodeid)
+-{
+-	msr_t msr;
+-	device_t dev;
+-	u32 reg1fc;
+-	u32 dtemp;
+-	u32 nbvid;
+-	u8 nb_cof_vid_update = needs_NB_COF_VID_update();
+-	u8 NbVidUpdateAll;
+-	u8 pvimode;
+-
+-	/* After warm reset finish the fid/vid setup for all cores. */
+-
+-	/* If any node has nb_cof_vid_update set all nodes need an update. */
+-
+-	dev = NODE_PCI(nodeid, 3);
+-	pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
+-	reg1fc = pci_read_config32(dev, 0x1FC);
+-	nbvid = (reg1fc >> 7) & 0x7F;
+-	NbVidUpdateAll = (reg1fc >> 1) & 1;
+-
+-	if (nb_cof_vid_update) {
+-		if (!pvimode) {	/* SVI */
+-			nbvid = nbvid - ((reg1fc >> 17) & 0x1F);
+-		}
+-		/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
+-		fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode);
+- 	} else {		/* !nb_cof_vid_update */
+-		if (pvimode)
+-			UpdateSinglePlaneNbVid();
+-	}
+-	dtemp = pci_read_config32(dev, 0xA0);
+-	dtemp &= PLLLOCK_OFF;
+-	dtemp |= PLLLOCK_DFT_L;
+-	pci_write_config32(dev, 0xA0, dtemp);
+-
+-        dualPlaneOnly(dev);
+-        applyBoostFIDOffset(dev);
+-        enableNbPState1(dev);
+-
+-	finalPstateChange();
+-
+-	/* Set TSC to tick at the P0 ndfid rate */
+-	msr = rdmsr(HWCR);
+-	msr.lo |= 1 << 24;
+-	wrmsr(HWCR, msr);
+-}
+-
+-
+-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
+-struct ap_apicid_st {
+-	u32 num;
+-	// it could use 256 bytes for 64 node quad core system
+-	u8 apicid[NODE_NUMS * 4];
+-};
+-
+-static void store_ap_apicid(unsigned ap_apicid, void *gp)
+-{
+-	struct ap_apicid_st *p = gp;
+-
+-	p->apicid[p->num++] = ap_apicid;
+-
+-}
+-#endif
+-
+-
+-static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
+-{
+-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
+-	struct ap_apicid_st ap_apicidx;
+-	u32 i;
+-#endif
+-	struct fidvid_st fv;
+-
+-	printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
+-
+-	/* Steps 1-6 of BIOS NB COF and VID Configuration
+-	 * for SVI and Single-Plane PVI Systems.
+-	 */
+-
+-	fv.common_fid = init_fidvid_core(0,0);
+-
+-	print_debug_fv("BSP fid = ", fv.common_fid);
+-
+-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY
+-	/* For all APs (We know the APIC ID of all APs even when the APIC ID
+-	   is lifted) remote read from AP LAPIC_MSG_REG about max fid.
+-	   Then calculate the common max fid that can be used for all
+-	   APs and BSP */
+-	ap_apicidx.num = 0;
+-
+-	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
+-
+-	for (i = 0; i < ap_apicidx.num; i++) {
+-		init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
+-	}
+-#else
+-	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
+-#endif
+-
+-	print_debug_fv("common_fid = ", fv.common_fid);
+-
+-	if (fv.common_fid & (1 << 16)) {	/* check nb_cof_vid_update */
+-
+-		// Enable the common fid and other settings.
+-		enable_fid_change((fv.common_fid >> 8) & 0x1F);
+-
+-		// nbfid change need warm reset, so reset at first
+-		return 1;
+-	}
+-
+-	return 0;		// No FID/VID changes. Don't reset
+-}
+-#endif
+diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
+deleted file mode 100644
+index 8de6d25..0000000
+--- a/src/cpu/amd/model_10xxx/init_cpus.c
++++ /dev/null
+@@ -1,968 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#include "cpu/amd/car/post_cache_as_ram.c"
+-#include "defaults.h"
+-#include <stdlib.h>
+-#include <cpu/x86/lapic.h>
+-#include <cpu/x86/mtrr.h>
+-#include <northbridge/amd/amdfam10/amdfam10.h>
+-#include <northbridge/amd/amdht/AsPsDefs.h>
+-#include <northbridge/amd/amdht/porting.h>
+-
+-#include <northbridge/amd/amdfam10/raminit_amdmct.c>
+-#include <reset.h>
+-
+-static void prep_fid_change(void);
+-static void init_fidvid_stage2(u32 apicid, u32 nodeid);
+-void cpuSetAMDMSR(void);
+-
+-#if CONFIG_PCI_IO_CFG_EXT
+-static void set_EnableCf8ExtCfg(void)
+-{
+-	// set the NB_CFG[46]=1;
+-	msr_t msr;
+-	msr = rdmsr(NB_CFG_MSR);
+-	// EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
+-	msr.hi |= (1 << (46 - 32));
+-	wrmsr(NB_CFG_MSR, msr);
+-}
+-#else
+-static void set_EnableCf8ExtCfg(void) { }
+-#endif
+-
+-
+-typedef void (*process_ap_t) (u32 apicid, void *gp);
+-
+-//core_range = 0 : all cores
+-//core range = 1 : core 0 only
+-//core range = 2 : cores other than core0
+-
+-static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
+-			void *gp)
+-{
+-	// here assume the OS don't change our apicid
+-	u32 ap_apicid;
+-
+-	u32 nodes;
+-	u32 siblings;
+-	u32 disable_siblings;
+-	u32 cores_found;
+-	u32 nb_cfg_54;
+-	int i, j;
+-	u32 ApicIdCoreIdSize;
+-	uint8_t rev_gte_d = 0;
+-	uint8_t dual_node = 0;
+-	uint32_t f3xe8;
+-
+-	/* get_nodes define in ht_wrapper.c */
+-	nodes = get_nodes();
+-
+-	if (!CONFIG_LOGICAL_CPUS ||
+-	    read_option(multi_core, 0) != 0) {	// 0 means multi core
+-		disable_siblings = 1;
+-	} else {
+-		disable_siblings = 0;
+-	}
+-
+-	/* Assume that all node are same stepping, otherwise we can use use
+-	   nb_cfg_54 from bsp for all nodes */
+-	nb_cfg_54 = read_nb_cfg_54();
+-	f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
+-
+-	if (cpuid_eax(0x80000001) >= 0x8)
+-		/* Revision D or later */
+-		rev_gte_d = 1;
+-
+-	if (rev_gte_d)
+-		 /* Check for dual node capability */
+-		if (f3xe8 & 0x20000000)
+-			dual_node = 1;
+-
+-	ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf);
+-	if (ApicIdCoreIdSize) {
+-		siblings = ((1 << ApicIdCoreIdSize) - 1);
+-	} else {
+-		siblings = 3;	//quad core
+-	}
+-
+-	for (i = 0; i < nodes; i++) {
+-		cores_found = get_core_num_in_bsp(i);
+-		if (siblings > cores_found)
+-			siblings = cores_found;
+-
+-		u32 jstart, jend;
+-
+-		if (core_range == 2) {
+-			jstart = 1;
+-		} else {
+-			jstart = 0;
+-		}
+-
+-		if (disable_siblings || (core_range == 1)) {
+-			jend = 0;
+-		} else {
+-			jend = cores_found;
+-		}
+-
+-		for (j = jstart; j <= jend; j++) {
+-			if (dual_node) {
+-				ap_apicid = 0;
+-				if (nb_cfg_54) {
+-					ap_apicid |= ((i >> 1) & 0x3) << 4;			/* Node ID */
+-					ap_apicid |= ((i & 0x1) * (siblings + 1)) + j;		/* Core ID */
+-				} else {
+-					ap_apicid |= i & 0x3;					/* Node ID */
+-					ap_apicid |= (((i & 0x1) * (siblings + 1)) + j) << 4;	/* Core ID */
+-				}
+-			} else {
+-				ap_apicid =
+-				i * (nb_cfg_54 ? (siblings + 1) : 1) +
+-				j * (nb_cfg_54 ? 1 : 64);
+-			}
+-
+-
+-#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
+-#if !CONFIG_LIFT_BSP_APIC_ID
+-			if ((i != 0) || (j != 0))	/* except bsp */
+-#endif
+-				ap_apicid += CONFIG_APIC_ID_OFFSET;
+-#endif
+-
+-			if (ap_apicid == bsp_apicid)
+-				continue;
+-
+-			process_ap(ap_apicid, gp);
+-
+-		}
+-	}
+-}
+-
+-static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
+-{
+-	int timeout;
+-	u32 status;
+-	int result;
+-	lapic_wait_icr_idle();
+-	lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+-	lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+-
+-/* Extra busy check compared to lapic.h */
+-	timeout = 0;
+-	do {
+-		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
+-	} while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
+-
+-	timeout = 0;
+-	do {
+-		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
+-	} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
+-
+-	result = -1;
+-
+-	if (status == LAPIC_ICR_RR_VALID) {
+-		*pvalue = lapic_read(LAPIC_RRR);
+-		result = 0;
+-	}
+-	return result;
+-}
+-
+-#if CONFIG_SET_FIDVID
+-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
+-#endif
+-
+-static inline __attribute__ ((always_inline))
+-void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
+-				const char *str)
+-{
+-	printk(BIOS_DEBUG,
+-	       "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str,
+-	       apicid, id.nodeid, id.coreid);
+-}
+-
+-static u32 wait_cpu_state(u32 apicid, u32 state)
+-{
+-	u32 readback = 0;
+-	u32 timeout = 1;
+-	int loop = 4000000;
+-	while (--loop > 0) {
+-		if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0)
+-			continue;
+-		if ((readback & 0x3f) == state || (readback & 0x3f) == F10_APSTATE_RESET) {
+-			timeout = 0;
+-			break;	//target cpu is in stage started
+-		}
+-	}
+-	if (timeout) {
+-		if (readback) {
+-			timeout = readback;
+-		}
+-	}
+-
+-	return timeout;
+-}
+-
+-static void wait_ap_started(u32 ap_apicid, void *gp)
+-{
+-	u32 timeout;
+-	timeout = wait_cpu_state(ap_apicid, F10_APSTATE_STARTED);
+-	printk(BIOS_DEBUG, "* AP %02x", ap_apicid);
+-	if (timeout) {
+-		printk(BIOS_DEBUG, " timed out:%08x\n", timeout);
+-	} else {
+-		printk(BIOS_DEBUG, "started\n");
+-	}
+-}
+-
+-void wait_all_other_cores_started(u32 bsp_apicid)
+-{
+-	// all aps other than core0
+-	printk(BIOS_DEBUG, "started ap apicid: ");
+-	for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0);
+-	printk(BIOS_DEBUG, "\n");
+-}
+-
+-void allow_all_aps_stop(u32 bsp_apicid)
+-{
+-	/* Called by the BSP to indicate AP can stop */
+-
+-	/* FIXME Do APs use this? */
+-
+-	// allow aps to stop use 6 bits for state
+-	lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED);
+-}
+-
+-static void enable_apic_ext_id(u32 node)
+-{
+-	u32 val;
+-
+-	val = pci_read_config32(NODE_HT(node), 0x68);
+-	val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
+-	pci_write_config32(NODE_HT(node), 0x68, val);
+-}
+-
+-static void STOP_CAR_AND_CPU(void)
+-{
+-	msr_t msr;
+-
+-	/* Disable L2 IC to L3 connection (Only for CAR) */
+-	msr = rdmsr(BU_CFG2);
+-	msr.lo &= ~(1 << ClLinesToNbDis);
+-	wrmsr(BU_CFG2, msr);
+-
+-	disable_cache_as_ram();	// inline
+-	/* stop all cores except node0/core0 the bsp .... */
+-	stop_this_cpu();
+-}
+-
+-static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
+-{
+-	u32 bsp_apicid = 0;
+-	u32 apicid;
+-	struct node_core_id id;
+-
+-	/* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */
+-	uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE;
+-	uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH;
+-	uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE;
+-	uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size;
+-	void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);
+-	if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
+-		printk(BIOS_WARNING,
+-			"sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n",
+-			sysinfo, sysinfo + 1, lower_stack_region_boundary);
+-
+-	/*
+-	 * already set early mtrr in cache_as_ram.inc
+-	 */
+-
+-	/* that is from initial apicid, we need nodeid and coreid
+-	   later */
+-	id = get_node_core_id_x();
+-
+-	/* NB_CFG MSR is shared between cores, so we need make sure
+-	   core0 is done at first --- use wait_all_core0_started  */
+-	if (id.coreid == 0) {
+-		set_apicid_cpuid_lo();	/* only set it on core0 */
+-		set_EnableCf8ExtCfg();	/* only set it on core0 */
+-#if CONFIG_ENABLE_APIC_EXT_ID
+-		enable_apic_ext_id(id.nodeid);
+-#endif
+-	}
+-
+-	enable_lapic();
+-
+-#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
+-	u32 initial_apicid = get_initial_apicid();
+-
+-#if !CONFIG_LIFT_BSP_APIC_ID
+-	if (initial_apicid != 0)	// other than bsp
+-#endif
+-	{
+-		/* use initial apic id to lift it */
+-		u32 dword = lapic_read(LAPIC_ID);
+-		dword &= ~(0xff << 24);
+-		dword |=
+-		    (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
+-
+-		lapic_write(LAPIC_ID, dword);
+-	}
+-#if CONFIG_LIFT_BSP_APIC_ID
+-	bsp_apicid += CONFIG_APIC_ID_OFFSET;
+-#endif
+-
+-#endif
+-
+-	/* get the apicid, it may be lifted already */
+-	apicid = lapicid();
+-
+-	// show our apicid, nodeid, and coreid
+-	if (id.coreid == 0) {
+-		if (id.nodeid != 0)	//all core0 except bsp
+-			print_apicid_nodeid_coreid(apicid, id, " core0: ");
+-	} else {		//all other cores
+-		print_apicid_nodeid_coreid(apicid, id, " corex: ");
+-	}
+-
+-	if (cpu_init_detectedx) {
+-		print_apicid_nodeid_coreid(apicid, id,
+-					   "\n\n\nINIT detected from ");
+-		printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n");
+-		soft_reset();
+-	}
+-
+-	if (id.coreid == 0) {
+-		if (!(warm_reset_detect(id.nodeid)))	//FIXME: INIT is checked above but check for more resets?
+-			distinguish_cpu_resets(id.nodeid);	// Also indicates we are started
+-	}
+-	// Mark the core as started.
+-	lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED);
+-
+-	if (apicid != bsp_apicid) {
+-		/* Setup each AP's cores MSRs.
+-		 * This happens after HTinit.
+-		 * The BSP runs this code in it's own path.
+-		 */
+-		update_microcode(cpuid_eax(1));
+-
+-		cpuSetAMDMSR();
+-
+-#if CONFIG_SET_FIDVID
+-#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY
+-		// Run on all AP for proper FID/VID setup.
+-		if (id.coreid == 0)	// only need set fid for core0
+-#endif
+-		{
+-			// check warm(bios) reset to call stage2 otherwise do stage1
+-			if (warm_reset_detect(id.nodeid)) {
+-				printk(BIOS_DEBUG,
+-				       "init_fidvid_stage2 apicid: %02x\n",
+-				       apicid);
+-				init_fidvid_stage2(apicid, id.nodeid);
+-			} else {
+-				printk(BIOS_DEBUG,
+-				       "init_fidvid_ap(stage1) apicid: %02x\n",
+-				       apicid);
+-				init_fidvid_ap(apicid, id.nodeid, id.coreid);
+-			}
+-		}
+-#endif
+-
+-		/* AP is ready, configure MTRRs and go to sleep */
+-		set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
+-
+-		STOP_CAR_AND_CPU();
+-
+-		printk(BIOS_DEBUG,
+-		       "\nAP %02x should be halted but you are reading this....\n",
+-		       apicid);
+-	}
+-
+-	return bsp_apicid;
+-}
+-
+-static u32 is_core0_started(u32 nodeid)
+-{
+-	u32 htic;
+-	device_t device;
+-	device = NODE_PCI(nodeid, 0);
+-	htic = pci_read_config32(device, HT_INIT_CONTROL);
+-	htic &= HTIC_ColdR_Detect;
+-	return htic;
+-}
+-
+-void wait_all_core0_started(void)
+-{
+-	/* When core0 is started, it will distingush_cpu_resets
+-	 * So wait for that to finish */
+-	u32 i;
+-	u32 nodes = get_nodes();
+-
+-	printk(BIOS_DEBUG, "core0 started: ");
+-	for (i = 1; i < nodes; i++) {	// skip bsp, because it is running on bsp
+-		while (!is_core0_started(i)) {
+-		}
+-		printk(BIOS_DEBUG, " %02x", i);
+-	}
+-	printk(BIOS_DEBUG, "\n");
+-}
+-
+-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+-/**
+- * void start_node(u32 node)
+- *
+- *  start the core0 in node, so it can generate HT packet to feature code.
+- *
+- * This function starts the AP nodes core0s. wait_all_core0_started() in
+- * romstage.c waits for all the AP to be finished before continuing
+- * system init.
+- */
+-static void start_node(u8 node)
+-{
+-	u32 val;
+-
+-	/* Enable routing table */
+-	printk(BIOS_DEBUG, "Start node %02x", node);
+-
+-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+-	/* For FAM10 support, we need to set Dram base/limit for the new node */
+-	pci_write_config32(NODE_MP(node), 0x44, 0);
+-	pci_write_config32(NODE_MP(node), 0x40, 3);
+-#endif
+-
+-	/* Allow APs to make requests (ROM fetch) */
+-	val = pci_read_config32(NODE_HT(node), 0x6c);
+-	val &= ~(1 << 1);
+-	pci_write_config32(NODE_HT(node), 0x6c, val);
+-
+-	printk(BIOS_DEBUG, " done.\n");
+-}
+-
+-/**
+- * static void setup_remote_node(u32 node)
+- *
+- * Copy the BSP Address Map to each AP.
+- */
+-static void setup_remote_node(u8 node)
+-{
+-	/* There registers can be used with F1x114_x Address Map at the
+-	   same time, So must set them even 32 node */
+-	static const u16 pci_reg[] = {
+-		/* DRAM Base/Limits Registers */
+-		0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
+-		0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
+-		0x144, 0x14c, 0x154, 0x15c, 0x164, 0x16c, 0x174, 0x17c,
+-		0x140, 0x148, 0x150, 0x158, 0x160, 0x168, 0x170, 0x178,
+-		/* MMIO Base/Limits Registers */
+-		0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
+-		0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
+-		/* IO Base/Limits Registers */
+-		0xc4, 0xcc, 0xd4, 0xdc,
+-		0xc0, 0xc8, 0xd0, 0xd8,
+-		/* Configuration Map Registers */
+-		0xe0, 0xe4, 0xe8, 0xec,
+-	};
+-	u16 i;
+-
+-	printk(BIOS_DEBUG, "setup_remote_node: %02x", node);
+-
+-	/* copy the default resource map from node 0 */
+-	for (i = 0; i < ARRAY_SIZE(pci_reg); i++) {
+-		u32 value;
+-		u16 reg;
+-		reg = pci_reg[i];
+-		value = pci_read_config32(NODE_MP(0), reg);
+-		pci_write_config32(NODE_MP(node), reg, value);
+-
+-	}
+-	printk(BIOS_DEBUG, " done\n");
+-}
+-#endif				/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
+-
+-static void AMD_Errata281(u8 node, u32 revision, u32 platform)
+-{
+-	/* Workaround for Transaction Scheduling Conflict in
+-	 * Northbridge Cross Bar.  Implement XCS Token adjustment
+-	 * for ganged links.  Also, perform fix up for the mixed
+-	 * revision case.
+-	 */
+-
+-	u32 reg, val;
+-	u8 i;
+-	u8 mixed = 0;
+-	u8 nodes = get_nodes();
+-
+-	if (platform & AMD_PTYPE_SVR) {
+-		/* For each node we need to check for a "broken" node */
+-		if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) {
+-			for (i = 0; i < nodes; i++) {
+-				if (mctGetLogicalCPUID(i) &
+-				    (AMD_DR_B0 | AMD_DR_B1)) {
+-					mixed = 1;
+-					break;
+-				}
+-			}
+-		}
+-
+-		if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) {
+-
+-			/* F0X68[22:21] DsNpReqLmt0 = 01b */
+-			val = pci_read_config32(NODE_PCI(node, 0), 0x68);
+-			val &= ~0x00600000;
+-			val |= 0x00200000;
+-			pci_write_config32(NODE_PCI(node, 0), 0x68, val);
+-
+-			/* F3X6C */
+-			val = pci_read_config32(NODE_PCI(node, 3), 0x6C);
+-			val &= ~0x700780F7;
+-			val |= 0x00010094;
+-			pci_write_config32(NODE_PCI(node, 3), 0x6C, val);
+-
+-			/* F3X7C */
+-			val = pci_read_config32(NODE_PCI(node, 3), 0x7C);
+-			val &= ~0x707FFF1F;
+-			val |= 0x00144514;
+-			pci_write_config32(NODE_PCI(node, 3), 0x7C, val);
+-
+-			/* F3X144[3:0] RspTok = 0001b */
+-			val = pci_read_config32(NODE_PCI(node, 3), 0x144);
+-			val &= ~0x0000000F;
+-			val |= 0x00000001;
+-			pci_write_config32(NODE_PCI(node, 3), 0x144, val);
+-
+-			for (i = 0; i < 3; i++) {
+-				reg = 0x148 + (i * 4);
+-				val = pci_read_config32(NODE_PCI(node, 3), reg);
+-				val &= ~0x000000FF;
+-				val |= 0x000000DB;
+-				pci_write_config32(NODE_PCI(node, 3), reg, val);
+-			}
+-		}
+-	}
+-}
+-
+-static void AMD_Errata298(void)
+-{
+-	/* Workaround for L2 Eviction May Occur during operation to
+-	 * set Accessed or dirty bit.
+-	 */
+-
+-	msr_t msr;
+-	u8 i;
+-	u8 affectedRev = 0;
+-	u8 nodes = get_nodes();
+-
+-	/* For each core we need to check for a "broken" node */
+-	for (i = 0; i < nodes; i++) {
+-		if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) {
+-			affectedRev = 1;
+-			break;
+-		}
+-	}
+-
+-	if (affectedRev) {
+-		msr = rdmsr(HWCR);
+-		msr.lo |= 0x08;	/* Set TlbCacheDis bit[3] */
+-		wrmsr(HWCR, msr);
+-
+-		msr = rdmsr(BU_CFG);
+-		msr.lo |= 0x02;	/* Set TlbForceMemTypeUc bit[1] */
+-		wrmsr(BU_CFG, msr);
+-
+-		msr = rdmsr(OSVW_ID_Length);
+-		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
+-		wrmsr(OSVW_ID_Length, msr);
+-
+-		msr = rdmsr(OSVW_Status);
+-		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
+-		wrmsr(OSVW_Status, msr);
+-	}
+-
+-	if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) {
+-		msr = rdmsr(OSVW_ID_Length);
+-		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
+-		wrmsr(OSVW_ID_Length, msr);
+-
+-	}
+-}
+-
+-static u32 get_platform_type(void)
+-{
+-	u32 ret = 0;
+-
+-	switch (SYSTEM_TYPE) {
+-	case 1:
+-		ret |= AMD_PTYPE_DSK;
+-		break;
+-	case 2:
+-		ret |= AMD_PTYPE_MOB;
+-		break;
+-	case 0:
+-		ret |= AMD_PTYPE_SVR;
+-		break;
+-	default:
+-		break;
+-	}
+-
+-	/* FIXME: add UMA support. */
+-
+-	/* All Fam10 are multi core */
+-	ret |= AMD_PTYPE_MC;
+-
+-	return ret;
+-}
+-
+-static void AMD_SetupPSIVID_d(u32 platform_type, u8 node)
+-{
+-	u32 dword;
+-	int i;
+-	msr_t msr;
+-
+-	if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) {
+-
+-		/* The following code sets the PSIVID to the lowest support P state
+-		 * assuming that the VID for the lowest power state is below
+-		 * the VDD voltage regulator threshold. (This also assumes that there
+-		 * is a Pstate lower than P0)
+-		 */
+-
+-		for (i = 4; i >= 0; i--) {
+-			msr = rdmsr(PS_REG_BASE + i);
+-			/*  Pstate valid? */
+-			if (msr.hi & PS_EN_MASK) {
+-				dword = pci_read_config32(NODE_PCI(i, 3), 0xA0);
+-				dword &= ~0x7F;
+-				dword |= (msr.lo >> 9) & 0x7F;
+-				pci_write_config32(NODE_PCI(i, 3), 0xA0, dword);
+-				break;
+-			}
+-		}
+-	}
+-}
+-
+-/**
+- * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links.
+- *  HT Phy operations are not valid on links that aren't present, so this
+- *  prevents invalid accesses.
+- *
+- * Returns the offset of the link register.
+- */
+-static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
+-{
+-	u32 reg;
+-	u32 val;
+-
+-	/* get start of CPU HT Host Capabilities */
+-	val = pci_read_config32(NODE_PCI(node, 0), 0x34);
+-	val &= 0xFF;		//reg offset of first link
+-
+-	cap_count++;
+-
+-	/* Traverse through the capabilities. */
+-	do {
+-		reg = pci_read_config32(NODE_PCI(node, 0), val);
+-		/* Is the capability block a HyperTransport capability block? */
+-		if ((reg & 0xFF) == 0x08) {
+-			/* Is the HT capability block an HT Host Capability? */
+-			if ((reg & 0xE0000000) == (1 << 29))
+-				cap_count--;
+-		}
+-
+-		if (cap_count)
+-			val = (reg >> 8) & 0xFF;	//update reg offset
+-	} while (cap_count && val);
+-
+-	*offset = (u8) val;
+-
+-	/* If requested capability found val != 0 */
+-	if (!cap_count)
+-		return TRUE;
+-	else
+-		return FALSE;
+-}
+-
+-/**
+- * AMD_checkLinkType - Compare desired link characteristics using a logical
+- *     link type mask.
+- *
+- * Returns the link characteristic mask.
+- */
+-static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
+-{
+-	u32 val;
+-	u32 linktype = 0;
+-
+-	/* Check connect, init and coherency */
+-	val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18);
+-	val &= 0x1F;
+-
+-	if (val == 3)
+-		linktype |= HTPHY_LINKTYPE_COHERENT;
+-
+-	if (val == 7)
+-		linktype |= HTPHY_LINKTYPE_NONCOHERENT;
+-
+-	if (linktype) {
+-		/* Check gen3 */
+-		val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08);
+-
+-		if (((val >> 8) & 0x0F) > 6)
+-			linktype |= HTPHY_LINKTYPE_HT3;
+-		else
+-			linktype |= HTPHY_LINKTYPE_HT1;
+-
+-		/* Check ganged */
+-		val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170);
+-
+-		if (val & 1)
+-			linktype |= HTPHY_LINKTYPE_GANGED;
+-		else
+-			linktype |= HTPHY_LINKTYPE_UNGANGED;
+-	}
+-	return linktype;
+-}
+-
+-/**
+- * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update
+- *   a phy setting for that link.
+- */
+-static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry)
+-{
+-	u32 phyReg;
+-	u32 phyBase;
+-	u32 val;
+-
+-	/* Determine this link's portal */
+-	if (link > 3)
+-		link -= 4;
+-
+-	phyBase = ((u32) link << 3) | 0x180;
+-
+-	/* Get the portal control register's initial value
+-	 * and update it to access the desired phy register
+-	 */
+-	phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase);
+-
+-	if (fam10_htphy_default[entry].htreg > 0x1FF) {
+-		phyReg &= ~HTPHY_DIRECT_OFFSET_MASK;
+-		phyReg |= HTPHY_DIRECT_MAP;
+-	} else {
+-		phyReg &= ~HTPHY_OFFSET_MASK;
+-	}
+-
+-	/* Now get the current phy register data
+-	 * LinkPhyDone = 0, LinkPhyWrite = 0 is a read
+-	 */
+-	phyReg |= fam10_htphy_default[entry].htreg;
+-	pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
+-
+-	do {
+-		val = pci_read_config32(NODE_PCI(node, 4), phyBase);
+-	} while (!(val & HTPHY_IS_COMPLETE_MASK));
+-
+-	/* Now we have the phy register data, apply the change */
+-	val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4);
+-	val &= ~fam10_htphy_default[entry].mask;
+-	val |= fam10_htphy_default[entry].data;
+-	pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val);
+-
+-	/* write it through the portal to the phy
+-	 * LinkPhyDone = 0, LinkPhyWrite = 1 is a write
+-	 */
+-	phyReg |= HTPHY_WRITE_CMD;
+-	pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
+-
+-	do {
+-		val = pci_read_config32(NODE_PCI(node, 4), phyBase);
+-	} while (!(val & HTPHY_IS_COMPLETE_MASK));
+-}
+-
+-void cpuSetAMDMSR(void)
+-{
+-	/* This routine loads the CPU with default settings in fam10_msr_default
+-	 * table . It must be run after Cache-As-RAM has been enabled, and
+-	 * Hypertransport initialization has taken place.  Also note
+-	 * that it is run on the current processor only, and only for the current
+-	 * processor core.
+-	 */
+-	msr_t msr;
+-	u8 i;
+-	u32 revision, platform;
+-
+-	printk(BIOS_DEBUG, "cpuSetAMDMSR ");
+-
+-	revision = mctGetLogicalCPUID(0xFF);
+-	platform = get_platform_type();
+-
+-	for (i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
+-		if ((fam10_msr_default[i].revision & revision) &&
+-		    (fam10_msr_default[i].platform & platform)) {
+-			msr = rdmsr(fam10_msr_default[i].msr);
+-			msr.hi &= ~fam10_msr_default[i].mask_hi;
+-			msr.hi |= fam10_msr_default[i].data_hi;
+-			msr.lo &= ~fam10_msr_default[i].mask_lo;
+-			msr.lo |= fam10_msr_default[i].data_lo;
+-			wrmsr(fam10_msr_default[i].msr, msr);
+-		}
+-	}
+-	AMD_Errata298();
+-
+-	printk(BIOS_DEBUG, " done\n");
+-}
+-
+-static void cpuSetAMDPCI(u8 node)
+-{
+-	/* This routine loads the CPU with default settings in fam10_pci_default
+-	 * table . It must be run after Cache-As-RAM has been enabled, and
+-	 * Hypertransport initialization has taken place.  Also note
+-	 * that it is run for the first core on each node
+-	 */
+-	u8 i, j;
+-	u32 revision, platform;
+-	u32 val;
+-	u8 offset;
+-
+-	printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
+-
+-	revision = mctGetLogicalCPUID(node);
+-	platform = get_platform_type();
+-
+-	AMD_SetupPSIVID_d(platform, node);	/* Set PSIVID offset which is not table driven */
+-
+-	for (i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
+-		if ((fam10_pci_default[i].revision & revision) &&
+-		    (fam10_pci_default[i].platform & platform)) {
+-			val = pci_read_config32(NODE_PCI(node,
+-							 fam10_pci_default[i].
+-							 function),
+-						fam10_pci_default[i].offset);
+-			val &= ~fam10_pci_default[i].mask;
+-			val |= fam10_pci_default[i].data;
+-			pci_write_config32(NODE_PCI(node,
+-						    fam10_pci_default[i].
+-						    function),
+-					   fam10_pci_default[i].offset, val);
+-		}
+-	}
+-
+-	for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
+-		if ((fam10_htphy_default[i].revision & revision) &&
+-		    (fam10_htphy_default[i].platform & platform)) {
+-			/* HT Phy settings either apply to both sublinks or have
+-			 * separate registers for sublink zero and one, so there
+-			 * will be two table entries. So, here we only loop
+-			 * through the sublink zeros in function zero.
+-			 */
+-			for (j = 0; j < 4; j++) {
+-				if (AMD_CpuFindCapability(node, j, &offset)) {
+-					if (AMD_checkLinkType(node, j, offset)
+-					    & fam10_htphy_default[i].linktype) {
+-						AMD_SetHtPhyRegister(node, j,
+-								     i);
+-					}
+-				} else {
+-					/* No more capabilities,
+-					 * link not present
+-					 */
+-					break;
+-				}
+-			}
+-		}
+-	}
+-
+-	/* FIXME: add UMA support and programXbarToSriReg(); */
+-
+-	AMD_Errata281(node, revision, platform);
+-
+-	/* FIXME: if the dct phy doesn't init correct it needs to reset.
+-	   if (revision & (AMD_DR_B2 | AMD_DR_B3))
+-	   dctPhyDiag(); */
+-
+-	printk(BIOS_DEBUG, " done\n");
+-}
+-
+-#ifdef UNUSED_CODE
+-static void cpuInitializeMCA(void)
+-{
+-	/* Clears Machine Check Architecture (MCA) registers, which power on
+-	 * containing unknown data, on currently running processor.
+-	 * This routine should only be executed on initial power on (cold boot),
+-	 * not across a warm reset because valid data is present at that time.
+-	 */
+-
+-	msr_t msr;
+-	u32 reg;
+-	u8 i;
+-
+-	if (cpuid_edx(1) & 0x4080) {	/* MCE and MCA (edx[7] and edx[14]) */
+-		msr = rdmsr(MCG_CAP);
+-		if (msr.lo & MCG_CTL_P) {	/* MCG_CTL_P bit is set? */
+-			msr.lo &= 0xFF;
+-			msr.lo--;
+-			msr.lo <<= 2;	/* multiply the count by 4 */
+-			reg = MC0_STA + msr.lo;
+-			msr.lo = msr.hi = 0;
+-			for (i = 0; i < 4; i++) {
+-				wrmsr(reg, msr);
+-				reg -= 4;	/* Touch status regs for each bank */
+-			}
+-		}
+-	}
+-}
+-#endif
+-
+-/**
+- * finalize_node_setup()
+- *
+- * Do any additional post HT init
+- *
+- */
+-static void finalize_node_setup(struct sys_info *sysinfo)
+-{
+-	u8 i;
+-	u8 nodes = get_nodes();
+-	u32 reg;
+-
+-	/* read Node0 F0_0x64 bit [8:10] to find out SbLink # */
+-	reg = pci_read_config32(NODE_HT(0), 0x64);
+-	sysinfo->sblk = (reg >> 8) & 7;
+-	sysinfo->sbbusn = 0;
+-	sysinfo->nodes = nodes;
+-	sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
+-
+-	for (i = 0; i < nodes; i++) {
+-		cpuSetAMDPCI(i);
+-	}
+-
+-#if CONFIG_SET_FIDVID
+-	// Prep each node for FID/VID setup.
+-	prep_fid_change();
+-#endif
+-
+-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+-	/* Skip the BSP, start at node 1 */
+-	for (i = 1; i < nodes; i++) {
+-		setup_remote_node(i);
+-		start_node(i);
+-	}
+-#endif
+-}
+-
+-#include "fidvid.c"
+diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
+deleted file mode 100644
+index b942c1a..0000000
+--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
++++ /dev/null
+@@ -1,165 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#include <console/console.h>
+-#include <cpu/x86/msr.h>
+-#include <cpu/amd/mtrr.h>
+-#include <device/device.h>
+-#include <device/pci.h>
+-#include <string.h>
+-#include <cpu/x86/msr.h>
+-#include <cpu/x86/smm.h>
+-#include <cpu/x86/pae.h>
+-#include <pc80/mc146818rtc.h>
+-#include <cpu/x86/lapic.h>
+-#include "northbridge/amd/amdfam10/amdfam10.h"
+-#include <cpu/amd/model_10xxx_rev.h>
+-#include <cpu/cpu.h>
+-#include <cpu/x86/cache.h>
+-#include <cpu/x86/mtrr.h>
+-#include <cpu/amd/multicore.h>
+-#include <cpu/amd/model_10xxx_msr.h>
+-
+-#define MCI_STATUS 0x401
+-
+-static void model_10xxx_init(device_t dev)
+-{
+-	u8 i;
+-	msr_t msr;
+-	struct node_core_id id;
+-#if CONFIG_LOGICAL_CPUS
+-	u32 siblings;
+-#endif
+-
+-	id = get_node_core_id(read_nb_cfg_54());	/* nb_cfg_54 can not be set */
+-	printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
+-
+-	/* Turn on caching if we haven't already */
+-	x86_enable_cache();
+-	amd_setup_mtrrs();
+-	x86_mtrr_check();
+-
+-	disable_cache();
+-
+-	/* zero the machine check error status registers */
+-	msr.lo = 0;
+-	msr.hi = 0;
+-	for (i = 0; i < 5; i++) {
+-		wrmsr(MCI_STATUS + (i * 4), msr);
+-	}
+-
+-	enable_cache();
+-
+-	/* Enable the local cpu apics */
+-	setup_lapic();
+-
+-	/* Set the processor name string */
+-	init_processor_name();
+-
+-#if CONFIG_LOGICAL_CPUS
+-	siblings = cpuid_ecx(0x80000008) & 0xff;
+-
+-	if (siblings > 0) {
+-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+-		msr.lo |= 1 << 28;
+-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+-
+-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+-		msr.hi |= 1 << (33 - 32);
+-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+-	}
+-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+-#endif
+-
+-	/* DisableCf8ExtCfg */
+-	msr = rdmsr(NB_CFG_MSR);
+-	msr.hi &= ~(1 << (46 - 32));
+-	wrmsr(NB_CFG_MSR, msr);
+-
+-	msr = rdmsr(BU_CFG2_MSR);
+-	/* Clear ClLinesToNbDis */
+-	msr.lo &= ~(1 << 15);
+-	/* Clear bit 35 as per Erratum 343 */
+-	msr.hi &= ~(1 << (35-32));
+-	wrmsr(BU_CFG2_MSR, msr);
+-
+-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+-		printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
+-
+-		/* Set SMM base address for this CPU */
+-		msr = rdmsr(SMM_BASE_MSR);
+-		msr.lo = SMM_BASE - (lapicid() * 0x400);
+-		wrmsr(SMM_BASE_MSR, msr);
+-
+-		/* Enable the SMM memory window */
+-		msr = rdmsr(SMM_MASK_MSR);
+-		msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
+-		wrmsr(SMM_MASK_MSR, msr);
+-	} else {
+-		printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
+-
+-		/* Set SMM base address for this CPU */
+-		msr = rdmsr(SMM_BASE_MSR);
+-		msr.lo = SMM_BASE - (lapicid() * 0x400);
+-		wrmsr(SMM_BASE_MSR, msr);
+-
+-		/* Disable the SMM memory window */
+-		msr.hi = 0x0;
+-		msr.lo = 0x0;
+-		wrmsr(SMM_MASK_MSR, msr);
+-	}
+-
+-	/* Set SMMLOCK to avoid exploits messing with SMM */
+-	msr = rdmsr(HWCR_MSR);
+-	msr.lo |= (1 << 0);
+-	wrmsr(HWCR_MSR, msr);
+-
+-}
+-
+-static struct device_operations cpu_dev_ops = {
+-	.init = model_10xxx_init,
+-};
+-
+-static struct cpu_device_id cpu_table[] = {
+-//AMD_GH_SUPPORT
+-	{ X86_VENDOR_AMD, 0x100f00 },		/* SH-F0 L1 */
+-	{ X86_VENDOR_AMD, 0x100f10 },		/* M2 */
+-	{ X86_VENDOR_AMD, 0x100f20 },		/* S1g1 */
+-	{ X86_VENDOR_AMD, 0x100f21 },
+-	{ X86_VENDOR_AMD, 0x100f2A },
+-	{ X86_VENDOR_AMD, 0x100f22 },
+-	{ X86_VENDOR_AMD, 0x100f23 },
+-	{ X86_VENDOR_AMD, 0x100f40 },		/* RB-C0 */
+-	{ X86_VENDOR_AMD, 0x100F42 },           /* RB-C2 */
+-	{ X86_VENDOR_AMD, 0x100F43 },           /* RB-C3 */
+-	{ X86_VENDOR_AMD, 0x100F52 },           /* BL-C2 */
+-	{ X86_VENDOR_AMD, 0x100F62 },           /* DA-C2 */
+-	{ X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
+-	{ X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
+-	{ X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
+-	{ X86_VENDOR_AMD, 0x100F91 },           /* HY-D1 */
+-	{ X86_VENDOR_AMD, 0x100FA0 },           /* PH-E0 */
+-	{ 0, 0 },
+-};
+-
+-static const struct cpu_driver model_10xxx __cpu_driver = {
+-	.ops      = &cpu_dev_ops,
+-	.id_table = cpu_table,
+-};
+diff --git a/src/cpu/amd/model_10xxx/monotonic_timer.c b/src/cpu/amd/model_10xxx/monotonic_timer.c
+deleted file mode 100644
+index 8c02fd1..0000000
+--- a/src/cpu/amd/model_10xxx/monotonic_timer.c
++++ /dev/null
+@@ -1,98 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- * Copyright (C) 2013 Google, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-#include <stdint.h>
+-#include <arch/cpu.h>
+-#include <cpu/x86/msr.h>
+-#include <timer.h>
+-#include <device/pci.h>
+-#include <device/pci_ids.h>
+-
+-#include <northbridge/amd/amdht/AsPsDefs.h>
+-#include <cpu/amd/model_10xxx_msr.h>
+-
+-static struct monotonic_counter {
+-	int initialized;
+-	uint32_t core_frequency;
+-	struct mono_time time;
+-	uint64_t last_value;
+-} mono_counter;
+-
+-static inline uint64_t read_counter_msr(void)
+-{
+-	msr_t counter_msr;
+-
+-	counter_msr = rdmsr(TSC_MSR);
+-
+-	return ((uint64_t)counter_msr.hi << 32) | (uint64_t)counter_msr.lo;
+-}
+-
+-static void init_timer(void)
+-{
+-	uint8_t model;
+-	uint32_t cpuid_fms;
+-	uint8_t cpufid;
+-	uint8_t cpudid;
+-	uint8_t boost_capable = 0;
+-
+-	/* Get CPU model */
+-	cpuid_fms = cpuid_eax(0x80000001);
+-	model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4);
+-
+-	/* Get boost capability */
+-	if ((model == 0x8) || (model == 0x9)) {	/* revision D */
+-		boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2;
+-	}
+-
+-	/* Set up TSC (BKDG v3.62 section 2.9.4)*/
+-	msr_t msr = rdmsr(HWCR_MSR);
+-	msr.lo |= 0x1000000;
+-	wrmsr(HWCR_MSR, msr);
+-
+-	/* Get core Pstate 0 frequency in MHz */
+-	msr = rdmsr(0xC0010064 + boost_capable);
+-	cpufid = (msr.lo & 0x3f);
+-	cpudid = (msr.lo & 0x1c0) >> 6;
+-	mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+-
+-	mono_counter.last_value = read_counter_msr();
+-	mono_counter.initialized = 1;
+-}
+-
+-void timer_monotonic_get(struct mono_time *mt)
+-{
+-	uint64_t current_tick;
+-	uint32_t usecs_elapsed = 0;
+-
+-	if (!mono_counter.initialized)
+-		init_timer();
+-
+-	current_tick = read_counter_msr();
+-	if (mono_counter.core_frequency != 0)
+-		usecs_elapsed = (current_tick - mono_counter.last_value) / mono_counter.core_frequency;
+-
+-	/* Update current time and tick values only if a full tick occurred. */
+-	if (usecs_elapsed) {
+-		mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
+-		mono_counter.last_value = current_tick;
+-	}
+-
+-	/* Save result. */
+-	*mt = mono_counter.time;
+-}
+diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c
+deleted file mode 100644
+index 98ef08a..0000000
+--- a/src/cpu/amd/model_10xxx/powernow_acpi.c
++++ /dev/null
+@@ -1,311 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
+- * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#include <console/console.h>
+-#include <stdint.h>
+-#include <cpu/x86/msr.h>
+-#include <arch/acpigen.h>
+-#include <cpu/amd/powernow.h>
+-#include <device/pci.h>
+-#include <device/pci_ids.h>
+-#include <cpu/x86/msr.h>
+-#include <cpu/amd/mtrr.h>
+-#include <cpu/amd/amdfam10_sysconf.h>
+-#include <arch/cpu.h>
+-#include <northbridge/amd/amdht/AsPsDefs.h>
+-#include <northbridge/amd/amdmct/mct/mct.h>
+-#include <northbridge/amd/amdmct/amddefs.h>
+-
+-static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power,
+-				u32 *pstate_latency, u32 *pstate_control,
+-				u32 *pstate_status, int coreID,
+-				u32 pcontrol_blk, u8 plen, u8 onlyBSP,
+-				uint8_t single_link)
+-{
+-	int i;
+-	struct cpuid_result cpuid1;
+-
+-	if ((onlyBSP) && (coreID != 0)) {
+-	    plen = 0;
+-	    pcontrol_blk = 0;
+-	}
+-
+-	acpigen_write_processor(coreID, pcontrol_blk, plen);
+-	acpigen_write_empty_PCT();
+-	acpigen_write_name("_PSS");
+-
+-	/* add later to total sum */
+-	acpigen_write_package(pstate_num);
+-
+-	for (i = 0;i < pstate_num; i++)
+-		acpigen_write_PSS_package(pstate_feq[i],
+-					  pstate_power[i],
+-					  pstate_latency[i],
+-					  pstate_latency[i],
+-					  pstate_control[i],
+-					  pstate_status[i]);
+-
+-	/* update the package size */
+-	acpigen_pop_len();
+-
+-	/* Write PPC object */
+-	acpigen_write_PPC(pstate_num);
+-
+-	/* Write PSD indicating coordination type */
+-	if ((single_link) && (mctGetLogicalCPUID(0) & AMD_DR_GT_Bx)) {
+-		/* Revision C or greater single-link processor */
+-		cpuid1 = cpuid(0x80000008);
+-		acpigen_write_PSD_package(0, (cpuid1.ecx & 0xff) + 1, SW_ALL);
+-	}
+-	else {
+-		/* Find the local APIC ID for the specified core ID */
+-		struct device* cpu;
+-		int cpu_index = 0;
+-		for (cpu = all_devices; cpu; cpu = cpu->next) {
+-			if ((cpu->path.type != DEVICE_PATH_APIC) ||
+-				(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
+-				continue;
+-			if (!cpu->enabled)
+-				continue;
+-			if (cpu_index == coreID)
+-				break;
+-			cpu_index++;
+-		}
+-
+-		if (cpu)
+-			acpigen_write_PSD_package(cpu->path.apic.apic_id, 1, SW_ANY);
+-	}
+-
+-	/* patch the whole Processor token length */
+-	acpigen_pop_len();
+-}
+-
+-/*
+-* For details of this algorithm, please refer to the BDKG 3.62 page 69
+-*
+-* WARNING: The core count algorithm below assumes that all processors
+-* are identical, with the same number of active cores.  While the BKDG
+-* states the BIOS must enforce this coreboot does not currently do so.
+-* As a result it is possible that this code may break if an illegal
+-* processor combination is installed.  If it does break please fix the
+-* code in the proper locations!
+-*/
+-void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
+-{
+-	u8 processor_brand[49];
+-	u32 *v;
+-	struct cpuid_result cpuid1;
+-
+-	u16 Pstate_feq[10];
+-	u32 Pstate_power[10];
+-	u32 Pstate_latency[10];
+-	u32 Pstate_control[10];
+-	u32 Pstate_status[10];
+-	u8 Pstate_num;
+-	u8 cmp_cap;
+-	u8 index;
+-	msr_t msr;
+-
+-	/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
+-	cpuid1 = cpuid(0x80000002);
+-	v = (u32 *) processor_brand;
+-	v[0] = cpuid1.eax;
+-	v[1] = cpuid1.ebx;
+-	v[2] = cpuid1.ecx;
+-	v[3] = cpuid1.edx;
+-	cpuid1 = cpuid(0x80000003);
+-	v[4] = cpuid1.eax;
+-	v[5] = cpuid1.ebx;
+-	v[6] = cpuid1.ecx;
+-	v[7] = cpuid1.edx;
+-	cpuid1 = cpuid(0x80000004);
+-	v[8] = cpuid1.eax;
+-	v[9] = cpuid1.ebx;
+-	v[10] = cpuid1.ecx;
+-	v[11] = cpuid1.edx;
+-	processor_brand[48] = 0;
+-	printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
+-
+-	uint32_t dtemp;
+-	uint8_t node_index;
+-	uint8_t node_count;
+-	uint8_t cores_per_node;
+-	uint8_t total_core_count;
+-
+-	/*
+-	 * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
+-	 * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
+-	 * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore
+-	 */
+-	printk(BIOS_INFO, "Pstates algorithm ...\n");
+-	/* Get number of cores */
+-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8);
+-	cmp_cap = (dtemp & 0x3000) >> 12;
+-	if (mctGetLogicalCPUID(0) & AMD_FAM10_REV_D)	/* revision D */
+-		cmp_cap |= (dtemp & 0x8000) >> 13;
+-	/* Get number of nodes */
+-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
+-	node_count = ((dtemp & 0x70) >> 4) + 1;
+-	cores_per_node = cmp_cap + 1;
+-
+-	/* Compute total number of cores installed in system */
+-	total_core_count = cores_per_node * node_count;
+-
+-	Pstate_num = 0;
+-
+-	/* See if the CPUID(0x80000007) returned EDX[7]==1b */
+-	cpuid1 = cpuid(0x80000007);
+-	if ((cpuid1.edx & 0x80) != 0x80) {
+-		printk(BIOS_INFO, "No valid set of P-states\n");
+-		return;
+-	}
+-
+-	uint8_t pviModeFlag;
+-	uint8_t Pstate_max;
+-	uint8_t cpufid;
+-	uint8_t cpudid;
+-	uint8_t cpuvid;
+-	uint8_t cpuidd;
+-	uint8_t cpuidv;
+-	uint8_t power_step_up;
+-	uint8_t power_step_down;
+-	uint8_t pll_lock_time;
+-	uint32_t expanded_cpuidv;
+-	uint32_t core_frequency;
+-	uint32_t core_power;
+-	uint32_t core_latency;
+-	uint32_t core_voltage;	/* multiplied by 10000 */
+-	uint8_t single_link;
+-
+-	/* Determine if this is a PVI or SVI system */
+-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
+-
+-	if (dtemp & PVI_MODE)
+-		pviModeFlag = 1;
+-	else
+-		pviModeFlag = 0;
+-
+-	/* Get PSmax's index */
+-	msr = rdmsr(0xC0010061);
+-	Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
+-
+-	/* Determine if all enabled Pstates have the same fidvid */
+-	uint8_t i;
+-	uint8_t cpufid_prev = (rdmsr(0xC0010064).lo & 0x3f);
+-	uint8_t all_enabled_cores_have_same_cpufid = 1;
+-	for (i = 1; i < Pstate_max; i++) {
+-		cpufid = rdmsr(0xC0010064 + i).lo & 0x3f;
+-		if (cpufid != cpufid_prev) {
+-			all_enabled_cores_have_same_cpufid = 0;
+-			break;
+-		}
+-	}
+-
+-	/* Populate tables with all Pstate information */
+-	for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) {
+-		/* Get power state information */
+-		msr = rdmsr(0xC0010064 + Pstate_num);
+-		cpufid = (msr.lo & 0x3f);
+-		cpudid = (msr.lo & 0x1c0) >> 6;
+-		cpuvid = (msr.lo & 0xfe00) >> 9;
+-		cpuidd = (msr.hi & 0xff);
+-		cpuidv = (msr.hi & 0x300) >> 8;
+-		core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+-		if (pviModeFlag) {
+-			if (cpuvid >= 0x20) {
+-				core_voltage = 7625 - (((cpuvid - 0x20) * 10000) / 80);
+-			}
+-			else {
+-				core_voltage = 15500 - ((cpuvid * 10000) / 40);
+-			}
+-		}
+-		else {
+-			cpuvid = cpuvid & 0x7f;
+-			if (cpuvid >= 0x7c)
+-				core_voltage = 0;
+-			else
+-				core_voltage = 15500 - ((cpuvid * 10000) / 80);
+-		}
+-		switch (cpuidv) {
+-			case 0x0:
+-				expanded_cpuidv = 1;
+-				break;
+-			case 0x1:
+-				expanded_cpuidv = 10;
+-				break;
+-			case 0x2:
+-				expanded_cpuidv = 100;
+-				break;
+-			case 0x3:
+-				expanded_cpuidv = 1000;
+-				break;
+-			default:
+-				printk(BIOS_ERR, "%s:%s:%d: Invalid cpuidv, "
+-					"not generating pstate tables.\n",
+-					__FILE__, __func__, __LINE__);
+-				return;
+-		}
+-		core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
+-
+-		/* Calculate transition latency */
+-		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xD4);
+-		power_step_up = (dtemp & 0xf000000) >> 24;
+-		power_step_down = (dtemp & 0xf00000) >> 20;
+-		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
+-		pll_lock_time = (dtemp & 0x3800) >> 11;
+-		if (all_enabled_cores_have_same_cpufid)
+-			core_latency = ((12 * power_step_down) + power_step_up) / 1000;
+-		else
+-			core_latency = (12 * (power_step_down + power_step_up) / 1000)
+-						 + pll_lock_time;
+-
+-		Pstate_feq[Pstate_num] = core_frequency;
+-		Pstate_power[Pstate_num] = core_power;
+-		Pstate_latency[Pstate_num] = core_latency;
+-		Pstate_control[Pstate_num] = Pstate_num;
+-		Pstate_status[Pstate_num] = Pstate_num;
+-	}
+-
+-	/* Print Pstate frequency, power, and latency */
+-	for (index = 0; index < Pstate_num; index++) {
+-		printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
+-			    Pstate_feq[index]);
+-		printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
+-			    Pstate_power[index]);
+-		printk(BIOS_INFO, "Pstate_latency[%d] = %dus\n", index,
+-			    Pstate_latency[index]);
+-	}
+-
+-	char pscope[] = "\\_PR";
+-
+-	acpigen_write_scope(pscope);
+-	for (index = 0; index < total_core_count; index++) {
+-		/* Determine if this is a single-link processor */
+-		node_index = 0x18 + (index / cores_per_node);
+-		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80);
+-		single_link = !!(((dtemp & 0xff00) >> 8) == 0);
+-
+-		write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power,
+-				Pstate_latency, Pstate_control, Pstate_status,
+-				index, pcontrol_blk, plen, onlyBSP, single_link);
+-	}
+-	acpigen_pop_len();
+-}
+diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c
+deleted file mode 100644
+index 12c45c9..0000000
+--- a/src/cpu/amd/model_10xxx/processor_name.c
++++ /dev/null
+@@ -1,323 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+- * Copyright (C) 2008 Peter Stuge
+- * Copyright (C) 2010 Marc Jones <marcj303@gmail.com>
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-/*
+- * This code sets the Processor Name String for AMD64 CPUs.
+- *
+- * Revision Guide for AMD Family 10h Processors
+- * Publication # 41322 Revision: 3.17 Issue Date: February 2008
+- */
+-
+-#include <console/console.h>
+-#include <string.h>
+-#include <cpu/x86/msr.h>
+-#include <cpu/amd/mtrr.h>
+-#include <cpu/cpu.h>
+-#include <cpu/amd/model_10xxx_rev.h>
+-
+-/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
+- * If you change these names your BIOS will _NOT_ pass the AMD validation and
+- * your mainboard will not be posted on the AMD Recommended Motherboard Website
+- */
+-
+-struct str_s {
+-	u8 Pg;
+-	u8 NC;
+-	u8 String;
+-	char const *value;
+-};
+-
+-
+-static const struct str_s String1_socket_F[] = {
+-	{0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 83"},
+-	{0x00, 0x01, 0x01, "Dual-Core AMD Opteron(tm) Processor 23"},
+-	{0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 83"},
+-	{0x00, 0x03, 0x01, "Quad-Core AMD Opteron(tm) Processor 23"},
+-	{0x00, 0x05, 0x00, "Six-Core AMD Opteron(tm) Processor 84"},
+-	{0x00, 0x05, 0x01, "Six-Core AMD Opteron(tm) Processor 24"},
+-	{0x00, 0x03, 0x02, "Embedded AMD Opteron(tm) Processor 83"},
+-	{0x00, 0x03, 0x03, "Embedded AMD Opteron(tm) Processor 23"},
+-	{0x00, 0x03, 0x04, "Embedded AMD Opteron(tm) Processor 13"},
+-	{0x00, 0x03, 0x05, "AMD Phenom(tm) FX-"},
+-	{0x01, 0x01, 0x01, "Embedded AMD Opteron(tm) Processor"},
+-	{0, 0, 0, NULL}
+-};
+-
+-static const struct str_s String2_socket_F[] = {
+-	{0x00, 0xFF, 0x02, " EE"},
+-	{0x00, 0xFF, 0x0A, " SE"},
+-	{0x00, 0xFF, 0x0B, " HE"},
+-	{0x00, 0xFF, 0x0C, " EE"},
+-	{0x00, 0xFF, 0x0D, " Quad-Core Processor"},
+-	{0x00, 0xFF, 0x0F, ""},
+-	{0x01, 0x01, 0x01, "GF HE"},
+-	{0, 0, 0, NULL}
+-};
+-
+-
+-static const struct str_s String1_socket_AM2[] = {
+-	{0x00, 0x00, 0x00, "AMD Athlon(tm) Processor LE-"},
+-	{0x00, 0x00, 0x01, "AMD Sempron(tm) Processor LE-"},
+-	{0x00, 0x00, 0x02, "AMD Sempron(tm) 1"},
+-	{0x00, 0x00, 0x03, "AMD Athlon(tm) II 1"},
+-	{0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 13"},
+-	{0x00, 0x01, 0x01, "AMD Athlon(tm)"},
+-	{0x00, 0x01, 0x03, "AMD Athlon(tm) II X2 2"},
+-	{0x00, 0x01, 0x04, "AMD Athlon(tm) II X2 B"},
+-	{0x00, 0x01, 0x05, "AMD Athlon(tm) II X2"},
+-	{0x00, 0x01, 0x07, "AMD Phenom(tm) II X2 5"},
+-	{0x00, 0x01, 0x0A, "AMD Phenom(tm) II X2"},
+-	{0x00, 0x01, 0x0B, "AMD Phenom(tm) II X2 B"},
+-	{0x00, 0x02, 0x00, "AMD Phenom(tm)"},
+-	{0x00, 0x02, 0x03, "AMD Phenom(tm) II X3 B"},
+-	{0x00, 0x02, 0x04, "AMD Phenom(tm) II X3"},
+-	{0x00, 0x02, 0x07, "AMD Athlon(tm) II X3 4"},
+-	{0x00, 0x02, 0x08, "AMD Phenom(tm) II X3 7"},
+-	{0x00, 0x02, 0x0A, "AMD Athlon(tm) II X3"},
+-	{0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 13"},
+-	{0x00, 0x03, 0x01, "AMD Phenom(tm) FX-"},
+-	{0x00, 0x03, 0x02, "AMD Phenom(tm)"},
+-	{0x00, 0x03, 0x03, "AMD Phenom(tm) II X4 9"},
+-	{0x00, 0x03, 0x04, "AMD Phenom(tm) II X4 8"},
+-	{0x00, 0x03, 0x07, "AMD Phenom(tm) II X4 B"},
+-	{0x00, 0x03, 0x08, "AMD Phenom(tm) II X4"},
+-	{0x00, 0x03, 0x0A, "AMD Athlon(tm) II X4 6"},
+-	{0x00, 0x03, 0x0F, "AMD Athlon(tm) II X4"},
+-	{0, 0, 0, NULL}
+-};
+-
+-static const struct str_s String2_socket_AM2[] = {
+-	{0x00, 0x00, 0x00, "00"},
+-	{0x00, 0x00, 0x01, "10"},
+-	{0x00, 0x00, 0x02, "20"},
+-	{0x00, 0x00, 0x03, "30"},
+-	{0x00, 0x00, 0x04, "40"},
+-	{0x00, 0x00, 0x05, "50"},
+-	{0x00, 0x00, 0x06, "60"},
+-	{0x00, 0x00, 0x07, "70"},
+-	{0x00, 0x00, 0x08, "80"},
+-	{0x00, 0x00, 0x09, "90"},
+-	{0x00, 0x00, 0x09, " Processor"},
+-	{0x00, 0x00, 0x09, "u Processor"},
+-	{0x00, 0x01, 0x00, "00 Dual-Core Processor"},
+-	{0x00, 0x01, 0x01, "00e Dual-Core Processor"},
+-	{0x00, 0x01, 0x02, "00B Dual-Core Processor"},
+-	{0x00, 0x01, 0x03, "50 Dual-Core Processor"},
+-	{0x00, 0x01, 0x04, "50e Dual-Core Processor"},
+-	{0x00, 0x01, 0x05, "50B Dual-Core Processor"},
+-	{0x00, 0x01, 0x06, " Processor"},
+-	{0x00, 0x01, 0x07, "e Processor"},
+-	{0x00, 0x01, 0x09, "0 Processor"},
+-	{0x00, 0x01, 0x0A, "0e Processor"},
+-	{0x00, 0x01, 0x0B, "u Processor"},
+-	{0x00, 0x02, 0x00, "00 Triple-Core Processor"},
+-	{0x00, 0x02, 0x01, "00e Triple-Core Processor"},
+-	{0x00, 0x02, 0x02, "00B Triple-Core Processor"},
+-	{0x00, 0x02, 0x03, "50 Triple-Core Processor"},
+-	{0x00, 0x02, 0x04, "50e Triple-Core Processor"},
+-	{0x00, 0x02, 0x05, "50B Triple-Core Processor"},
+-	{0x00, 0x02, 0x06, " Processor"},
+-	{0x00, 0x02, 0x07, "e Processor"},
+-	{0x00, 0x02, 0x09, "0e Processor"},
+-	{0x00, 0x02, 0x0A, "0 Processor"},
+-	{0x00, 0x03, 0x00, "00 Quad-Core Processor"},
+-	{0x00, 0x03, 0x01, "00e Quad-Core Processor"},
+-	{0x00, 0x03, 0x02, "00B Quad-Core Processor"},
+-	{0x00, 0x03, 0x03, "50 Quad-Core Processor"},
+-	{0x00, 0x03, 0x04, "50e Quad-Core Processor"},
+-	{0x00, 0x03, 0x05, "50B Quad-Core Processor"},
+-	{0x00, 0x03, 0x06, " Processor"},
+-	{0x00, 0x03, 0x07, "e Processor"},
+-	{0x00, 0x03, 0x09, "0e Processor"},
+-	{0x00, 0x03, 0x0A, " SE"},
+-	{0x00, 0x03, 0x0B, " HE"},
+-	{0x00, 0x03, 0x0C, " EE"},
+-	{0x00, 0x03, 0x0D, " Quad-Core Processor"},
+-	{0x00, 0x03, 0x0E, "0 Processor"},
+-	{0x00, 0xFF, 0x0F, ""},
+-	{0, 0, 0, NULL}
+-};
+-
+-static const struct str_s String1_socket_G34[] = {
+-	{0x00, 0x07, 0x00, "AMD Opteron(tm) Processor 61"},
+-	{0x00, 0x0B, 0x00, "AMD Opteron(tm) Processor 61"},
+-	{0x01, 0x07, 0x01, "Embedded AMD Opteron(tm) Processor "},
+-	{0, 0, 0, NULL}
+-};
+-
+-static const struct str_s String2_socket_G34[] = {
+-	{0x00, 0x07, 0x00, " HE"},
+-	{0x00, 0x07, 0x01, " SE"},
+-	{0x00, 0x0B, 0x00, " HE"},
+-	{0x00, 0x0B, 0x01, " SE"},
+-	{0x00, 0x0B, 0x0F, ""},
+-	{0x01, 0x07, 0x01, " QS"},
+-	{0x01, 0x07, 0x02, " KS"},
+-	{0, 0, 0, NULL}
+-};
+-
+-static const struct str_s String1_socket_C32[] = {
+-	{0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"},
+-	{0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"},
+-	{0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "},
+-	{0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "},
+-	{0, 0, 0, NULL}
+-};
+-
+-static const struct str_s String2_socket_C32[] = {
+-	{0x00, 0x03, 0x00, " HE"},
+-	{0x00, 0x03, 0x01, " EE"},
+-	{0x00, 0x05, 0x00, " HE"},
+-	{0x00, 0x05, 0x01, " EE"},
+-	{0x01, 0x03, 0x01, "QS HE"},
+-	{0x01, 0x03, 0x02, "LE HE"},
+-	{0x01, 0x05, 0x01, "KX HE"},
+-	{0x01, 0x05, 0x02, "GL EE"},
+-	{0, 0, 0, NULL}
+-};
+-
+-const char *unknown = "AMD Processor model unknown";
+-const char *unknown2 = " type unknown";
+-const char *sample = "AMD Engineering Sample";
+-const char *thermal = "AMD Thermal Test Kit";
+-
+-
+-static int strcpymax(char *dst, const char *src, int buflen)
+-{
+-	int i;
+-	for (i = 0; i < buflen && src[i]; i++)
+-		dst[i] = src[i];
+-	if (i >= buflen)
+-		i--;
+-	dst[i] = 0;
+-	return i;
+-}
+-
+-
+-int init_processor_name(void)
+-{
+-	/* variable names taken from fam10 revision guide for clarity */
+-	u32 BrandId;	/* CPUID Fn8000_0001_EBX */
+-	u8 String1;	/* BrandID[14:11] */
+-	u8 String2;	/* BrandID[3:0] */
+-	u8 Model;	/* BrandID[10:4] */
+-	u8 Pg;		/* BrandID[15] */
+-	u8 PkgTyp;	/* BrandID[31:28] */
+-	u8 NC;		/* CPUID Fn8000_0008_ECX */
+-	const char *processor_name_string = unknown;
+-	char program_string[48];
+-	u32 *p_program_string = (u32 *)program_string;
+-	msr_t msr;
+-	int i, j = 0, str2_checkNC = 1;
+-	const struct str_s *str, *str2;
+-
+-
+-	/* Find out which CPU brand it is */
+-	BrandId = cpuid_ebx(0x80000001);
+-	String1 = (u8)((BrandId >> 11) & 0x0F);
+-	String2 = (u8)((BrandId >> 0) & 0x0F);
+-	Model = (u8)((BrandId >> 4) & 0x7F);
+-	Pg = (u8)((BrandId >> 15) & 0x01);
+-	PkgTyp = (u8)((BrandId >> 28) & 0x0F);
+-	NC = (u8)(cpuid_ecx(0x80000008) & 0xFF);
+-
+-	/* null the string */
+-	memset(program_string, 0, sizeof(program_string));
+-
+-	if (!Model) {
+-		processor_name_string = Pg ? thermal : sample;
+-		goto done;
+-	}
+-
+-	switch (PkgTyp) {
+-	case 0:		/* F1207 */
+-		str = String1_socket_F;
+-		str2 = String2_socket_F;
+-		str2_checkNC = 0;
+-		break;
+-	case 1:		/* AM2 */
+-		str = String1_socket_AM2;
+-		str2 = String2_socket_AM2;
+-		break;
+-	case 3:		/* G34 */
+-		str = String1_socket_G34;
+-		str2 = String2_socket_G34;
+-		str2_checkNC = 0;
+-		break;
+-	case 5:		/* C32 */
+-		str = String1_socket_C32;
+-		str2 = String2_socket_C32;
+-		break;
+-	default:
+-		goto done;
+-	}
+-
+-	/* String1 */
+-	for (i = 0; str[i].value; i++) {
+-		if ((str[i].Pg == Pg) &&
+-		    (str[i].NC == NC) &&
+-		    (str[i].String == String1)) {
+-			processor_name_string = str[i].value;
+-			break;
+-		}
+-	}
+-
+-	if (!str[i].value)
+-		goto done;
+-
+-	j = strcpymax(program_string, processor_name_string,
+-		      sizeof(program_string));
+-
+-	/* Translate Model from 01-99 to ASCII and put it on the end.
+-	 * Numbers less than 10 should include a leading zero, e.g., 09.*/
+-	if (Model < 100 && j < sizeof(program_string) - 2) {
+-		program_string[j++] = (Model / 10) + '0';
+-		program_string[j++] = (Model % 10) + '0';
+-	}
+-
+-	processor_name_string = unknown2;
+-
+-	/* String 2 */
+-	for(i = 0; str2[i].value; i++) {
+-		if ((str2[i].Pg == Pg) &&
+-		    ((str2[i].NC == NC) || !str2_checkNC) &&
+-		    (str2[i].String == String2)) {
+-			processor_name_string = str2[i].value;
+-			break;
+-		}
+-	}
+-
+-
+-done:
+-	strcpymax(&program_string[j], processor_name_string,
+-		  sizeof(program_string) - j);
+-
+-	printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
+-
+-	for (i = 0; i < 6; i++) {
+-		msr.lo = p_program_string[(2 * i) + 0];
+-		msr.hi = p_program_string[(2 * i) + 1];
+-		wrmsr_amd(0xC0010030 + i, msr);
+-	}
+-
+-	return 0;
+-}
+diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c
+deleted file mode 100644
+index 46ccdbd..0000000
+--- a/src/cpu/amd/model_10xxx/ram_calc.c
++++ /dev/null
+@@ -1,54 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#include <cpu/cpu.h>
+-#include <cpu/x86/msr.h>
+-#include <cpu/amd/mtrr.h>
+-
+-#include <cbmem.h>
+-
+-#include "ram_calc.h"
+-
+-#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+-uint64_t get_uma_memory_size(uint64_t topmem)
+-{
+-	uint64_t uma_size = 0;
+-	if (IS_ENABLED(CONFIG_GFXUMA)) {
+-		/* refer to UMA Size Consideration in 780 BDG. */
+-		if (topmem >= 0x40000000)	/* 1GB and above system memory */
+-			uma_size = 0x10000000;	/* 256M recommended UMA */
+-
+-		else if (topmem >= 0x20000000)	/* 512M - 1023M system memory */
+-			uma_size = 0x8000000;	/* 128M recommended UMA */
+-
+-		else if (topmem >= 0x10000000)	/* 256M - 511M system memory */
+-			uma_size = 0x4000000;	/* 64M recommended UMA */
+-	}
+-
+-	return uma_size;
+-}
+-
+-void *cbmem_top(void)
+-{
+-	uint32_t topmem = rdmsr(TOP_MEM).lo;
+-
+-	return (void *) topmem - get_uma_memory_size(topmem);
+-}
+-#endif
+diff --git a/src/cpu/amd/model_10xxx/ram_calc.h b/src/cpu/amd/model_10xxx/ram_calc.h
+deleted file mode 100644
+index 61da328..0000000
+--- a/src/cpu/amd/model_10xxx/ram_calc.h
++++ /dev/null
+@@ -1,25 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#ifndef _AMD_MODEL_10XXX_RAM_CALC_H_
+-#define _AMD_MODEL_10XXX_RAM_CALC_H_
+-
+-uint64_t get_uma_memory_size(uint64_t topmem);
+-
+-#endif
+diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
+deleted file mode 100644
+index 51aca35..0000000
+--- a/src/cpu/amd/model_10xxx/update_microcode.c
++++ /dev/null
+@@ -1,71 +0,0 @@
+-/*
+- * This file is part of the coreboot project.
+- *
+- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#include <stdint.h>
+-#include <cpu/amd/microcode.h>
+-
+-struct id_mapping {
+-        uint32_t orig_id;
+-        uint16_t new_id;
+-};
+-
+-static u16 get_equivalent_processor_rev_id(u32 orig_id) {
+-	static const struct id_mapping id_mapping_table[] = {
+-		{ 0x100f00, 0x1000 },
+-		{ 0x100f01, 0x1000 },
+-		{ 0x100f02, 0x1000 },
+-		{ 0x100f20, 0x1020 },
+-		{ 0x100f21, 0x1020 }, /* DR-B1 */
+-		{ 0x100f2A, 0x1020 }, /* DR-BA */
+-		{ 0x100f22, 0x1022 }, /* DR-B2 */
+-		{ 0x100f23, 0x1022 }, /* DR-B3 */
+-		{ 0x100f42, 0x1041 }, /* RB-C2 */
+-		{ 0x100f43, 0x1043 }, /* RB-C3 */
+-		{ 0x100f52, 0x1041 }, /* BL-C2 */
+-		{ 0x100f62, 0x1062 }, /* DA-C2 */
+-		{ 0x100f63, 0x1043 }, /* DA-C3 */
+-		{ 0x100f81, 0x1081 }, /* HY-D1 */
+-		{ 0x100fa0, 0x10A0 }, /* PH-E0 */
+-
+-		/* Array terminator */
+-		{ 0xffffff, 0x0000 },
+-	};
+-
+-	u32 new_id;
+-	int i;
+-
+-	new_id = 0;
+-
+-	for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
+-		if (id_mapping_table[i].orig_id == orig_id) {
+-			new_id = id_mapping_table[i].new_id;
+-			break;
+-		}
+-	}
+-
+-	return new_id;
+-
+-}
+-
+-void update_microcode(u32 cpu_deviceid)
+-{
+-	u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
+-	amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
+-}
+diff --git a/src/cpu/amd/socket_AM2r2/Makefile.inc b/src/cpu/amd/socket_AM2r2/Makefile.inc
+index 3675af4..6917441 100644
+--- a/src/cpu/amd/socket_AM2r2/Makefile.inc
++++ b/src/cpu/amd/socket_AM2r2/Makefile.inc
+@@ -1,4 +1,4 @@
+-subdirs-y += ../model_10xxx
++subdirs-y += ../family_10h-family_15h
+ subdirs-y += ../quadcore
+ subdirs-y += ../mtrr
+ subdirs-y += ../microcode
+diff --git a/src/cpu/amd/socket_AM3/Makefile.inc b/src/cpu/amd/socket_AM3/Makefile.inc
+index 3675af4..6917441 100644
+--- a/src/cpu/amd/socket_AM3/Makefile.inc
++++ b/src/cpu/amd/socket_AM3/Makefile.inc
+@@ -1,4 +1,4 @@
+-subdirs-y += ../model_10xxx
++subdirs-y += ../family_10h-family_15h
+ subdirs-y += ../quadcore
+ subdirs-y += ../mtrr
+ subdirs-y += ../microcode
+diff --git a/src/cpu/amd/socket_ASB2/Makefile.inc b/src/cpu/amd/socket_ASB2/Makefile.inc
+index 3675af4..6917441 100644
+--- a/src/cpu/amd/socket_ASB2/Makefile.inc
++++ b/src/cpu/amd/socket_ASB2/Makefile.inc
+@@ -1,4 +1,4 @@
+-subdirs-y += ../model_10xxx
++subdirs-y += ../family_10h-family_15h
+ subdirs-y += ../quadcore
+ subdirs-y += ../mtrr
+ subdirs-y += ../microcode
+diff --git a/src/cpu/amd/socket_C32/Makefile.inc b/src/cpu/amd/socket_C32/Makefile.inc
+index 3675af4..6917441 100644
+--- a/src/cpu/amd/socket_C32/Makefile.inc
++++ b/src/cpu/amd/socket_C32/Makefile.inc
+@@ -1,4 +1,4 @@
+-subdirs-y += ../model_10xxx
++subdirs-y += ../family_10h-family_15h
+ subdirs-y += ../quadcore
+ subdirs-y += ../mtrr
+ subdirs-y += ../microcode
+diff --git a/src/cpu/amd/socket_F_1207/Makefile.inc b/src/cpu/amd/socket_F_1207/Makefile.inc
+index b74862e..ece8d9a 100644
+--- a/src/cpu/amd/socket_F_1207/Makefile.inc
++++ b/src/cpu/amd/socket_F_1207/Makefile.inc
+@@ -1,4 +1,4 @@
+-subdirs-y += ../model_10xxx
++subdirs-y += ../family_10h-family_15h
+ subdirs-y += ../quadcore
+ subdirs-y += ../mtrr
+ subdirs-y += ../microcode
+diff --git a/src/cpu/amd/socket_G34/Makefile.inc b/src/cpu/amd/socket_G34/Makefile.inc
+index a8e1333..de33cd3 100644
+--- a/src/cpu/amd/socket_G34/Makefile.inc
++++ b/src/cpu/amd/socket_G34/Makefile.inc
+@@ -1,5 +1,5 @@
+ ramstage-y += socket_G34.c
+-subdirs-y += ../model_10xxx
++subdirs-y += ../family_10h-family_15h
+ subdirs-y += ../quadcore
+ subdirs-y += ../mtrr
+ subdirs-y += ../microcode
+diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
+index dfda22e..4c2b38a 100644
+--- a/src/mainboard/advansus/a785e-i/romstage.c
++++ b/src/mainboard/advansus/a785e-i/romstage.c
+@@ -68,7 +68,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "resourcemap.c"
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include "spd.h"
+ #include <reset.h>
+diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
+index 9e2e904..e2bd351 100644
+--- a/src/mainboard/amd/bimini_fam10/romstage.c
++++ b/src/mainboard/amd/bimini_fam10/romstage.c
+@@ -65,7 +65,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
+index c01ccf0..74bc9d5 100644
+--- a/src/mainboard/amd/mahogany_fam10/romstage.c
++++ b/src/mainboard/amd/mahogany_fam10/romstage.c
+@@ -68,7 +68,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+index 3d7c168..20d46e6 100644
+--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
++++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+@@ -87,7 +87,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ static const u8 spd_addr[] = {
+diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
+index 924345d..89100b1 100644
+--- a/src/mainboard/amd/tilapia_fam10/romstage.c
++++ b/src/mainboard/amd/tilapia_fam10/romstage.c
+@@ -67,7 +67,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
+index b35473c..5d1f5a6 100644
+--- a/src/mainboard/asus/kfsn4-dre/romstage.c
++++ b/src/mainboard/asus/kfsn4-dre/romstage.c
+@@ -74,7 +74,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
+ #include "southbridge/nvidia/ck804/early_setup_car.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
+diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
+index 18e7c16..a3f3310 100644
+--- a/src/mainboard/asus/kgpe-d16/romstage.c
++++ b/src/mainboard/asus/kgpe-d16/romstage.c
+@@ -66,7 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
+ 
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ /*
+diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
+index bcff9e4..82f30d9 100644
+--- a/src/mainboard/asus/m4a78-em/romstage.c
++++ b/src/mainboard/asus/m4a78-em/romstage.c
+@@ -68,7 +68,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
+index e49c9b9..780bf81 100644
+--- a/src/mainboard/asus/m4a785-m/romstage.c
++++ b/src/mainboard/asus/m4a785-m/romstage.c
+@@ -68,7 +68,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
+index 35e9e94..38761a6 100644
+--- a/src/mainboard/asus/m5a88-v/romstage.c
++++ b/src/mainboard/asus/m5a88-v/romstage.c
+@@ -66,7 +66,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "resourcemap.c"
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include "spd.h"
+ #include <reset.h>
+diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
+index bace1d0..764a5c6 100644
+--- a/src/mainboard/avalue/eax-785e/romstage.c
++++ b/src/mainboard/avalue/eax-785e/romstage.c
+@@ -69,7 +69,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "resourcemap.c"
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include "spd.h"
+ #include <reset.h>
+diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
+index 8ac24f9..db4e449 100644
+--- a/src/mainboard/gigabyte/ma785gm/romstage.c
++++ b/src/mainboard/gigabyte/ma785gm/romstage.c
+@@ -64,7 +64,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
+index cd9b790..4ce7c58 100644
+--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
++++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
+@@ -64,7 +64,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
+index 6cb4227..d2a0b95 100644
+--- a/src/mainboard/gigabyte/ma78gm/romstage.c
++++ b/src/mainboard/gigabyte/ma78gm/romstage.c
+@@ -68,7 +68,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
+index 62fd6cb..97e60d5 100644
+--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
++++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
+@@ -78,7 +78,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ static const u8 spd_addr[] = {
+diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
+index 6df828b..edbae3a 100644
+--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
++++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
+@@ -67,7 +67,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
+index ac66ada..16bb089 100644
+--- a/src/mainboard/jetway/pa78vm5/romstage.c
++++ b/src/mainboard/jetway/pa78vm5/romstage.c
+@@ -72,7 +72,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
+index b8fca64..4ea3306 100644
+--- a/src/mainboard/msi/ms9652_fam10/romstage.c
++++ b/src/mainboard/msi/ms9652_fam10/romstage.c
+@@ -74,7 +74,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
+ #include "southbridge/nvidia/mcp55/early_setup_car.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ static void sio_setup(void)
+diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+index d94d917..c224dbc 100644
+--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+@@ -66,7 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
+ #include "southbridge/nvidia/mcp55/early_setup_car.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ static void sio_setup(void)
+diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
+index c79c2b1..0f9445b 100644
+--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
+@@ -73,7 +73,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
+ #include "southbridge/nvidia/mcp55/early_setup_car.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ static void sio_setup(void)
+diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
+index b3174ae..4ea14fe 100644
+--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
+@@ -65,7 +65,7 @@ static int spd_read_byte(u32 device, u32 address)
+ #include "resourcemap.c"
+ #include "cpu/amd/quadcore/quadcore.c"
+ #include <cpu/amd/microcode.h>
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ #include <spd.h>
+ 
+diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
+index 1049014..0030619 100644
+--- a/src/mainboard/tyan/s2912_fam10/romstage.c
++++ b/src/mainboard/tyan/s2912_fam10/romstage.c
+@@ -74,7 +74,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
+ #include "southbridge/nvidia/mcp55/early_setup_car.c"
+ #include <cpu/amd/microcode.h>
+ 
+-#include "cpu/amd/model_10xxx/init_cpus.c"
++#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+ #include "northbridge/amd/amdfam10/early_ht.c"
+ 
+ static void sio_setup(void)
+diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
+index 3b302e8..adcfdf0 100644
+--- a/src/northbridge/amd/amdfam10/northbridge.c
++++ b/src/northbridge/amd/amdfam10/northbridge.c
+@@ -34,7 +34,7 @@
+ #include <cpu/x86/lapic.h>
+ #include <cpu/amd/mtrr.h>
+ #include <cpu/amd/amdfam10_sysconf.h>
+-#include <cpu/amd/model_10xxx/ram_calc.h>
++#include <cpu/amd/family_10h-family_15h/ram_calc.h>
+ 
+ #if CONFIG_LOGICAL_CPUS
+ #include <cpu/amd/multicore.h>
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0036-cpu-amd-Add-initial-AMD-Family-15h-support.patch b/resources/libreboot/patch/kgpe-d16/0033-cpu-amd-Add-initial-AMD-Family-15h-support.patch
index 3fa3153..75aa195 100644
--- a/resources/libreboot/patch/kgpe-d16/0036-cpu-amd-Add-initial-AMD-Family-15h-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0033-cpu-amd-Add-initial-AMD-Family-15h-support.patch
@@ -1,67 +1,95 @@
-From ea0ded12622a5307ea596201fb25f64ec622a5f4 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Mon, 1 Jun 2015 04:04:42 -0500
-Subject: [PATCH 036/146] cpu/amd: Add initial AMD Family 15h support
+From db769f9a54ca4b8a1872c031f29aae31f412e2a2 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 16 Oct 2015 13:51:51 -0500
+Subject: [PATCH 033/139] cpu/amd: Add initial AMD Family 15h support
 
 TEST: Booted ASUS KGPE-D16 with single Opteron 6380
  * Unbuffered DDR3 DIMMs tested and working
  * Suspend to RAM (S3) tested and working
+
+Conflicts:
+
+	src/cpu/amd/car/disable_cache_as_ram.c
+
+Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/car/cache_as_ram.inc                |  130 +-
- src/cpu/amd/car/disable_cache_as_ram.c          |   87 +-
- src/cpu/amd/model_10xxx/defaults.h              |  266 +-
- src/cpu/amd/model_10xxx/fidvid.c                |  235 +-
- src/cpu/amd/model_10xxx/init_cpus.c             |  232 +-
- src/cpu/amd/model_10xxx/model_10xxx_init.c      |   92 +-
- src/cpu/amd/model_10xxx/powernow_acpi.c         |   50 +-
- src/cpu/amd/model_10xxx/processor_name.c        |  194 +-
- src/cpu/amd/model_10xxx/update_microcode.c      |    6 +
- src/cpu/amd/quadcore/quadcore.c                 |  109 +-
- src/cpu/amd/quadcore/quadcore_id.c              |   43 +-
- src/include/cpu/amd/model_10xxx_msr.h           |    7 +
- src/northbridge/amd/amdfam10/Kconfig            |    2 +-
- src/northbridge/amd/amdfam10/Makefile.inc       |    2 +
- src/northbridge/amd/amdfam10/amdfam10.h         |    6 +-
- src/northbridge/amd/amdfam10/amdfam10_util.c    |   13 +-
- src/northbridge/amd/amdfam10/link_control.c     |   86 +
- src/northbridge/amd/amdfam10/misc_control.c     |    6 +
- src/northbridge/amd/amdfam10/nb_control.c       |   85 +
- src/northbridge/amd/amdfam10/northbridge.c      |  241 +-
- src/northbridge/amd/amdfam10/raminit_amdmct.c   |  304 ++-
- src/northbridge/amd/amdht/h3ncmn.c              |  171 +-
- src/northbridge/amd/amdht/ht_wrapper.c          |   43 +-
- src/northbridge/amd/amdmct/amddefs.h            |   78 +-
- src/northbridge/amd/amdmct/mct/mct_d.c          |    4 +-
- src/northbridge/amd/amdmct/mct/mct_d.h          |   20 +-
- src/northbridge/amd/amdmct/mct/mctpro_d.c       |   21 +-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c     | 3199 +++++++++++++++++++----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h     |  124 +-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h |    9 +
- src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c  |   21 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c  |   27 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c  | 1087 +++++++-
- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c  |   55 +-
- src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c    |    7 +-
- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c    |  105 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c   |    2 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c    |   24 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c    |  585 ++++-
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c    | 1342 ++++++++--
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c  |   10 +-
- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c   |   20 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c     |  255 +-
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c   | 1007 +++++--
- src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c  |   69 +-
- src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h    |   46 +-
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c   |  652 +++--
- src/northbridge/amd/amdmct/wrappers/mcti.h      |   14 +-
- src/northbridge/amd/amdmct/wrappers/mcti_d.c    |   42 +-
- 49 files changed, 9183 insertions(+), 2052 deletions(-)
+ src/cpu/amd/car/cache_as_ram.inc                   |  130 +-
+ src/cpu/amd/car/disable_cache_as_ram.c             |   77 +-
+ src/cpu/amd/family_10h-family_15h/defaults.h       |  266 +-
+ src/cpu/amd/family_10h-family_15h/fidvid.c         |  235 +-
+ src/cpu/amd/family_10h-family_15h/init_cpus.c      |  232 +-
+ .../amd/family_10h-family_15h/model_10xxx_init.c   |   92 +-
+ src/cpu/amd/family_10h-family_15h/powernow_acpi.c  |   50 +-
+ src/cpu/amd/family_10h-family_15h/processor_name.c |  194 +-
+ .../amd/family_10h-family_15h/update_microcode.c   |    6 +
+ src/cpu/amd/quadcore/quadcore.c                    |  109 +-
+ src/cpu/amd/quadcore/quadcore_id.c                 |   43 +-
+ src/include/cpu/amd/model_10xxx_msr.h              |    7 +
+ src/mainboard/advansus/a785e-i/romstage.c          |    2 +-
+ src/mainboard/amd/bimini_fam10/romstage.c          |    2 +-
+ src/mainboard/amd/mahogany_fam10/romstage.c        |    2 +-
+ .../amd/serengeti_cheetah_fam10/romstage.c         |    2 +-
+ src/mainboard/amd/tilapia_fam10/romstage.c         |    2 +-
+ src/mainboard/asus/kfsn4-dre/romstage.c            |    2 +-
+ src/mainboard/asus/m4a78-em/romstage.c             |    2 +-
+ src/mainboard/asus/m4a785-m/romstage.c             |    2 +-
+ src/mainboard/asus/m5a88-v/romstage.c              |    2 +-
+ src/mainboard/avalue/eax-785e/romstage.c           |    2 +-
+ src/mainboard/gigabyte/ma785gm/romstage.c          |    2 +-
+ src/mainboard/gigabyte/ma785gmt/romstage.c         |    2 +-
+ src/mainboard/gigabyte/ma78gm/romstage.c           |    2 +-
+ src/mainboard/hp/dl165_g6_fam10/romstage.c         |    2 +-
+ src/mainboard/iei/kino-780am2-fam10/romstage.c     |    2 +-
+ src/mainboard/jetway/pa78vm5/romstage.c            |    2 +-
+ src/mainboard/msi/ms9652_fam10/romstage.c          |    2 +-
+ src/mainboard/supermicro/h8dmr_fam10/romstage.c    |    2 +-
+ src/mainboard/supermicro/h8qme_fam10/romstage.c    |    2 +-
+ src/mainboard/supermicro/h8scm_fam10/romstage.c    |    2 +-
+ src/mainboard/tyan/s2912_fam10/romstage.c          |    2 +-
+ src/northbridge/amd/amdfam10/Kconfig               |    2 +-
+ src/northbridge/amd/amdfam10/Makefile.inc          |    2 +
+ src/northbridge/amd/amdfam10/amdfam10.h            |    6 +-
+ src/northbridge/amd/amdfam10/amdfam10_util.c       |   13 +-
+ src/northbridge/amd/amdfam10/link_control.c        |   86 +
+ src/northbridge/amd/amdfam10/misc_control.c        |    7 +
+ src/northbridge/amd/amdfam10/nb_control.c          |   85 +
+ src/northbridge/amd/amdfam10/northbridge.c         |  233 +-
+ src/northbridge/amd/amdfam10/raminit_amdmct.c      |  304 +-
+ src/northbridge/amd/amdht/h3ncmn.c                 |  171 +-
+ src/northbridge/amd/amdht/ht_wrapper.c             |   43 +-
+ src/northbridge/amd/amdmct/amddefs.h               |   78 +-
+ src/northbridge/amd/amdmct/mct/mct_d.c             |    4 +-
+ src/northbridge/amd/amdmct/mct/mct_d.h             |   20 +-
+ src/northbridge/amd/amdmct/mct/mctpro_d.c          |   21 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c        | 3187 ++++++++++++++++----
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h        |  124 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h    |    9 +
+ src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c     |   21 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c     |   27 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c     | 1087 ++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c     |   55 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c       |    7 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c       |  105 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctproc.c      |    2 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctrci.c       |   24 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c       |  585 +++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c       | 1342 ++++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c     |   10 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c      |   20 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c        |  255 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c      | 1007 +++++--
+ src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c     |   69 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h       |   46 +-
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c      |  652 +++-
+ src/northbridge/amd/amdmct/wrappers/mcti.h         |   14 +-
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c       |   42 +-
+ 70 files changed, 9184 insertions(+), 2064 deletions(-)
  create mode 100644 src/northbridge/amd/amdfam10/link_control.c
  create mode 100644 src/northbridge/amd/amdfam10/nb_control.c
 
 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
-index 133daac..ec70f67 100644
+index 0b2bc60..6542906 100644
 --- a/src/cpu/amd/car/cache_as_ram.inc
 +++ b/src/cpu/amd/car/cache_as_ram.inc
 @@ -32,18 +32,23 @@
@@ -109,9 +137,9 @@ index 133daac..ec70f67 100644
 +	cvtsd2si %xmm4, %ebx
  
  	/* Check if cpu_init_detected. */
- 	movl	$MTRRdefType_MSR, %ecx
+ 	movl	$MTRR_DEF_TYPE_MSR, %ecx
  	rdmsr
- 	andl	$MTRRdefTypeEn, %eax
+ 	andl	$MTRR_DEF_TYPE_EN, %eax
  	movl	%eax, %ebx	/* We store the status. */
 +	cvtsi2sd %ebx, %xmm5
  
@@ -176,9 +204,9 @@ index 133daac..ec70f67 100644
 +	/* Busywait until the first core sets up the MTRRs */
 +check_init_detect_1:
 +	/* Check if cpu_init_detected. */
-+	movl	$MTRRdefType_MSR, %ecx
++	movl	$MTRR_DEF_TYPE_MSR, %ecx
 +	rdmsr
-+	andl	$MTRRdefTypeEn, %eax
++	andl	$MTRR_DEF_TYPE_EN, %eax
 +	cmp	$0x00000000, %eax
 +	je	check_init_detect_1	/* First core has not yet started */
 +
@@ -302,10 +330,10 @@ index 133daac..ec70f67 100644
  
  	/* We will not go back. */
 diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
-index d3a3812..8a2a0ca 100644
+index 5eccf79..5cab544 100644
 --- a/src/cpu/amd/car/disable_cache_as_ram.c
 +++ b/src/cpu/amd/car/disable_cache_as_ram.c
-@@ -19,46 +19,93 @@
+@@ -19,7 +19,7 @@
   * along with this program; if not, write to the Free Software
   * Foundation, Inc.
   *
@@ -314,18 +342,11 @@ index d3a3812..8a2a0ca 100644
   */
  
  #include <cpu/x86/cache.h>
+@@ -34,41 +34,78 @@ static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
+ 	return family;
+ }
  
 -static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
-+static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
-+{
-+	uint32_t family;
-+
-+	family = cpuid_eax(0x80000001);
-+	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-+
-+	return family;
-+}
-+
 +static inline __attribute__((always_inline)) void disable_cache_as_ram(uint8_t skip_sharedc_config)
  {
  	msr_t msr;
@@ -339,21 +360,21 @@ index d3a3812..8a2a0ca 100644
  
 -	msr.lo = 0;
 -	msr.hi = 0;
--	wrmsr(MTRRfix4K_C8000_MSR, msr);
+-	wrmsr(MTRR_FIX_4K_C8000, msr);
 +		msr.lo = 0;
 +		msr.hi = 0;
-+		wrmsr(MTRRfix4K_C8000_MSR, msr);
++		wrmsr(MTRR_FIX_4K_C8000, msr);
  #if CONFIG_DCACHE_RAM_SIZE > 0x8000
--	wrmsr(MTRRfix4K_C0000_MSR, msr);
-+		wrmsr(MTRRfix4K_C0000_MSR, msr);
+-	wrmsr(MTRR_FIX_4K_C0000, msr);
++		wrmsr(MTRR_FIX_4K_C0000, msr);
  #endif
  #if CONFIG_DCACHE_RAM_SIZE > 0x10000
--	wrmsr(MTRRfix4K_D0000_MSR, msr);
-+		wrmsr(MTRRfix4K_D0000_MSR, msr);
+-	wrmsr(MTRR_FIX_4K_D0000, msr);
++		wrmsr(MTRR_FIX_4K_D0000, msr);
  #endif
  #if CONFIG_DCACHE_RAM_SIZE > 0x18000
--	wrmsr(MTRRfix4K_D8000_MSR, msr);
-+		wrmsr(MTRRfix4K_D8000_MSR, msr);
+-	wrmsr(MTRR_FIX_4K_D8000, msr);
++		wrmsr(MTRR_FIX_4K_D8000, msr);
  #endif
 -	/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
 +		/* disable fixed mtrr from now on, it will be enabled by ramstage again */
@@ -365,7 +386,7 @@ index d3a3812..8a2a0ca 100644
 +		msr.hi = 0;
 +		msr.lo = (1 << 11);
 +
-+		wrmsr(MTRRdefType_MSR, msr);
++		wrmsr(MTRR_DEF_TYPE_MSR, msr);
 +
 +		enable_cache();
 +	}
@@ -397,7 +418,7 @@ index d3a3812..8a2a0ca 100644
 +			msr.lo &= ~(0x1 << 9);
 +			wrmsr(0xc0011021, msr);
  
--	wrmsr(MTRRdefType_MSR, msr);
+-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
 +			/* Erratum 714: SpecNbReqDis = 0 */
 +			msr = rdmsr(BU_CFG2_MSR);
 +			msr.lo &= ~(0x1 << 8);
@@ -419,10 +440,10 @@ index d3a3812..8a2a0ca 100644
 -	disable_cache_as_ram();
 +	disable_cache_as_ram(0);
  }
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index 6fd1a7e..24f87ba 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -2,6 +2,7 @@
   * This file is part of the coreboot project.
   *
@@ -935,10 +956,10 @@ index 6fd1a7e..24f87ba 100644
  	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
  								   [20:16] RttIndex = 04h */
  };
-diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
+diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
 index 99ffcc8..2e26645 100644
---- a/src/cpu/amd/model_10xxx/fidvid.c
-+++ b/src/cpu/amd/model_10xxx/fidvid.c
+--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
 @@ -44,7 +44,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
  
  3.-  2.4.2.7 dualPlaneOnly(dev)
@@ -1314,10 +1335,10 @@ index 99ffcc8..2e26645 100644
  
  	print_debug_fv("BSP fid = ", fv.common_fid);
  
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 index 8de6d25..aced850 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -30,9 +30,12 @@
  #include <northbridge/amd/amdfam10/raminit_amdmct.c>
  #include <reset.h>
@@ -1693,10 +1714,10 @@ index 8de6d25..aced850 100644
  static void cpuInitializeMCA(void)
  {
  	/* Clears Machine Check Architecture (MCA) registers, which power on
-diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
+diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
 index b942c1a..8a61f13 100644
---- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
-+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
+--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
++++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
 @@ -39,6 +39,23 @@
  
  #define MCI_STATUS 0x401
@@ -1834,10 +1855,10 @@ index b942c1a..8a61f13 100644
  	{ 0, 0 },
  };
  
-diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c
+diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
 index 98ef08a..84e5514 100644
---- a/src/cpu/amd/model_10xxx/powernow_acpi.c
-+++ b/src/cpu/amd/model_10xxx/powernow_acpi.c
+--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
++++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
 @@ -74,8 +74,7 @@ static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_p
  		/* Revision C or greater single-link processor */
  		cpuid1 = cpuid(0x80000008);
@@ -1950,10 +1971,10 @@ index 98ef08a..84e5514 100644
  			cpuvid = cpuvid & 0x7f;
  			if (cpuvid >= 0x7c)
  				core_voltage = 0;
-diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c
+diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c
 index 12c45c9..fbd0452 100644
---- a/src/cpu/amd/model_10xxx/processor_name.c
-+++ b/src/cpu/amd/model_10xxx/processor_name.c
+--- a/src/cpu/amd/family_10h-family_15h/processor_name.c
++++ b/src/cpu/amd/family_10h-family_15h/processor_name.c
 @@ -33,6 +33,10 @@
  #include <cpu/amd/mtrr.h>
  #include <cpu/cpu.h>
@@ -2182,10 +2203,10 @@ index 12c45c9..fbd0452 100644
  
  	printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
  
-diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
+diff --git a/src/cpu/amd/family_10h-family_15h/update_microcode.c b/src/cpu/amd/family_10h-family_15h/update_microcode.c
 index 51aca35..3b2f5dd 100644
---- a/src/cpu/amd/model_10xxx/update_microcode.c
-+++ b/src/cpu/amd/model_10xxx/update_microcode.c
+--- a/src/cpu/amd/family_10h-family_15h/update_microcode.c
++++ b/src/cpu/amd/family_10h-family_15h/update_microcode.c
 @@ -28,6 +28,7 @@ struct id_mapping {
  
  static u16 get_equivalent_processor_rev_id(u32 orig_id) {
@@ -2364,7 +2385,7 @@ index 9c21e94..8a9b5ed 100644
 -
  }
 diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
-index 778e96f..c0537b3 100644
+index c5921de..c0537b3 100644
 --- a/src/cpu/amd/quadcore/quadcore_id.c
 +++ b/src/cpu/amd/quadcore/quadcore_id.c
 @@ -43,9 +43,12 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
@@ -2418,7 +2439,7 @@ index 778e96f..c0537b3 100644
  		}
  	}
  
--	if (rev_gte_d) {
+-	if (rev_gte_d && dual_node) {
 +	if (fam15h && dual_node) {
 +		/* Coreboot expects each separate processor die to be on a different nodeid.
 +		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
@@ -2467,11 +2488,284 @@ index 6c7dece..7d78e2d 100644
  
  #define CPU_ID_FEATURES_MSR		0xC0011004
  #define CPU_ID_HYPER_EXT_FEATURES	0xC001100d
+diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
+index 4c2b38a..ab717fd 100644
+--- a/src/mainboard/advansus/a785e-i/romstage.c
++++ b/src/mainboard/advansus/a785e-i/romstage.c
+@@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
+index e2bd351..5e2cf82 100644
+--- a/src/mainboard/amd/bimini_fam10/romstage.c
++++ b/src/mainboard/amd/bimini_fam10/romstage.c
+@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
+index 74bc9d5..025a8bb 100644
+--- a/src/mainboard/amd/mahogany_fam10/romstage.c
++++ b/src/mainboard/amd/mahogany_fam10/romstage.c
+@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+index 20d46e6..5063439 100644
+--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
++++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+@@ -231,7 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
+index 89100b1..e37bc08 100644
+--- a/src/mainboard/amd/tilapia_fam10/romstage.c
++++ b/src/mainboard/amd/tilapia_fam10/romstage.c
+@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
+index 5d1f5a6..dd5c7dc 100644
+--- a/src/mainboard/asus/kfsn4-dre/romstage.c
++++ b/src/mainboard/asus/kfsn4-dre/romstage.c
+@@ -245,7 +245,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
+index 82f30d9..82b96bf 100644
+--- a/src/mainboard/asus/m4a78-em/romstage.c
++++ b/src/mainboard/asus/m4a78-em/romstage.c
+@@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
+index 780bf81..30975fa 100644
+--- a/src/mainboard/asus/m4a785-m/romstage.c
++++ b/src/mainboard/asus/m4a785-m/romstage.c
+@@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
+index 38761a6..4edaba2 100644
+--- a/src/mainboard/asus/m5a88-v/romstage.c
++++ b/src/mainboard/asus/m5a88-v/romstage.c
+@@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
+index 764a5c6..447012b 100644
+--- a/src/mainboard/avalue/eax-785e/romstage.c
++++ b/src/mainboard/avalue/eax-785e/romstage.c
+@@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
+index db4e449..444e59d 100644
+--- a/src/mainboard/gigabyte/ma785gm/romstage.c
++++ b/src/mainboard/gigabyte/ma785gm/romstage.c
+@@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
+index 4ce7c58..705d7c5 100644
+--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
++++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
+@@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
+index d2a0b95..5d21801 100644
+--- a/src/mainboard/gigabyte/ma78gm/romstage.c
++++ b/src/mainboard/gigabyte/ma78gm/romstage.c
+@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
+index 97e60d5..26c0bb9 100644
+--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
++++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
+@@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
+index edbae3a..321eea6 100644
+--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
++++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
+@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
+index 16bb089..93dd2ce 100644
+--- a/src/mainboard/jetway/pa78vm5/romstage.c
++++ b/src/mainboard/jetway/pa78vm5/romstage.c
+@@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
+index 4ea3306..5da971f 100644
+--- a/src/mainboard/msi/ms9652_fam10/romstage.c
++++ b/src/mainboard/msi/ms9652_fam10/romstage.c
+@@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+index c224dbc..1425546 100644
+--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
+index 0f9445b..4721eba 100644
+--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
+@@ -214,7 +214,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
+diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
+index 4ea14fe..858aca0 100644
+--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
+@@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	/* TODO: The Kernel must support 12 processor, otherwise the interrupt
+diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
+index 0030619..cdf51b1 100644
+--- a/src/mainboard/tyan/s2912_fam10/romstage.c
++++ b/src/mainboard/tyan/s2912_fam10/romstage.c
+@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	post_code(0x33);
+ 
+-	cpuSetAMDMSR();
++	cpuSetAMDMSR(0);
+ 	post_code(0x34);
+ 
+ 	amd_ht_init(sysinfo);
 diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
-index ff92fca..b84eabf 100644
+index ada5b9f..cb0d109 100644
 --- a/src/northbridge/amd/amdfam10/Kconfig
 +++ b/src/northbridge/amd/amdfam10/Kconfig
-@@ -92,7 +92,7 @@ endif
+@@ -96,7 +96,7 @@ endif
  if HAVE_ACPI_RESUME
  	config S3_DATA_SIZE
  		int
@@ -2520,7 +2814,7 @@ index a1e08a0..b724394 100644
  
  #ifdef __PRE_RAM__
 diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
-index 423bb73..a4045bdf 100644
+index 423bb73..a4045bd 100644
 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c
 +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
 @@ -34,14 +34,14 @@ u32 Get_NB32(u32 dev, u32 reg)
@@ -2652,10 +2946,18 @@ index 0000000..1091ef4
 +};
 \ No newline at end of file
 diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
-index 85c8838..8777e8f 100644
+index 90a4db1..8777e8f 100644
 --- a/src/northbridge/amd/amdfam10/misc_control.c
 +++ b/src/northbridge/amd/amdfam10/misc_control.c
-@@ -153,3 +153,9 @@ static const struct pci_driver mcf3_driver __pci_driver = {
+@@ -4,6 +4,7 @@
+  * Copyright (C) 2003 by Eric Biederman
+  * Copyright (C) Stefan Reinauer
+  * Copyright (C) 2007 Advanced Micro Devices, Inc.
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -152,3 +153,9 @@ static const struct pci_driver mcf3_driver __pci_driver = {
  	.vendor = PCI_VENDOR_ID_AMD,
  	.device = 0x1203,
  };
@@ -2758,10 +3060,10 @@ index 0000000..f95b6f8
 +};
 \ No newline at end of file
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index d0a0787..a29dad9 100644
+index adcfdf0..baf77d6 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -79,6 +79,21 @@ device_t get_node_pci(u32 nodeid, u32 fn)
+@@ -81,6 +81,21 @@ device_t get_node_pci(u32 nodeid, u32 fn)
  #endif
  }
  
@@ -2783,30 +3085,16 @@ index d0a0787..a29dad9 100644
  static void get_fx_devs(void)
  {
  	int i;
-@@ -195,24 +210,33 @@ static void amd_g34_fixup(struct bus *link, device_t dev)
- 	uint8_t rev_gte_d = 0;
- 	uint8_t dual_node = 0;
- 	uint32_t f3xe8;
--	
-+
- 	if (cpuid_eax(0x80000001) >= 0x8)
+@@ -202,7 +217,7 @@ static void amd_g34_fixup(struct bus *link, device_t dev)
  		/* Revision D or later */
  		rev_gte_d = 1;
--	
+ 
 -	if (rev_gte_d) {
-+
 +	if (rev_gte_d || is_fam15h()) {
  		f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
--	
-+
+ 
  		/* Check for dual node capability */
- 		if (f3xe8 & 0x20000000)
- 			dual_node = 1;
--	
-+
- 		if (dual_node) {
- 			/* Each G34 processor contains a defective HT link.
- 			* See the BKDG Rev 3.62 section 2.7.1.5 for details.
+@@ -215,6 +230,15 @@ static void amd_g34_fixup(struct bus *link, device_t dev)
  			*/
  			f3xe8 = pci_read_config32(get_node_pci(nodeid, 3), 0xe8);
  			uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30);
@@ -2822,7 +3110,7 @@ index d0a0787..a29dad9 100644
  			if (internal_node_number == 0) {
  				/* Node 0 */
  				if (link->link_num == 6)	/* Link 2 Sublink 1 */
-@@ -312,6 +336,46 @@ static void amdfam10_scan_chains(device_t dev)
+@@ -314,6 +338,46 @@ static void amdfam10_scan_chains(device_t dev)
  {
  	struct bus *link;
  
@@ -2858,7 +3146,7 @@ index d0a0787..a29dad9 100644
 +				link->link_num = 5;
 +			else if (link->link_num == 7)
 +				link->link_num = 6;
-+		
++
 +			current_link_number++;
 +			if (current_link_number > 3)
 +				current_link_number = 0;
@@ -2869,7 +3157,7 @@ index d0a0787..a29dad9 100644
  	/* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */
  	trim_ht_chain(dev);
  
-@@ -618,13 +682,21 @@ static const struct pci_driver mcf0_driver __pci_driver = {
+@@ -620,13 +684,21 @@ static const struct pci_driver mcf0_driver __pci_driver = {
  	.device = 0x1200,
  };
  
@@ -2892,7 +3180,7 @@ index d0a0787..a29dad9 100644
  	.enable_dev = 0,
  	.init = amdfam10_nb_init,
  };
-@@ -948,38 +1020,61 @@ static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *cur
+@@ -950,38 +1022,61 @@ static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *cur
  
  static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed)
  {
@@ -2984,8 +3272,8 @@ index d0a0787..a29dad9 100644
  	}
  }
  
-@@ -1073,6 +1168,8 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
- 				} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+@@ -1076,6 +1171,8 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
+ #if IS_ENABLED(CONFIG_DIMM_DDR3)
  					/* Find the maximum and minimum supported voltages */
  					uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot];
 +					uint8_t configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot];
@@ -2993,7 +3281,7 @@ index d0a0787..a29dad9 100644
  					if (supported_voltages & 0x8)
  						t->minimum_voltage = 1150;
  					else if (supported_voltages & 0x4)
-@@ -1091,7 +1188,14 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
+@@ -1094,7 +1191,14 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
  					else if (supported_voltages & 0x8)
  						t->maximum_voltage = 1150;
  
@@ -3006,10 +3294,10 @@ index d0a0787..a29dad9 100644
 +						t->configured_voltage = 1350;
 +					else if (configured_voltage & 0x1)
 +						t->configured_voltage = 1500;
+ #endif
  				}
  				t->memory_error_information_handle = 0xFFFE;	/* no error information handle available */
- 				single_len = t->length + smbios_string_table_len(t->eos);
-@@ -1229,12 +1333,14 @@ static void cpu_bus_scan(device_t dev)
+@@ -1233,12 +1337,14 @@ static void cpu_bus_scan(device_t dev)
  #if CONFIG_CBB
  	device_t pci_domain;
  #endif
@@ -3024,7 +3312,7 @@ index d0a0787..a29dad9 100644
  	unsigned ApicIdCoreIdSize;
  
  	nb_cfg_54 = 0;
-@@ -1321,14 +1427,23 @@ static void cpu_bus_scan(device_t dev)
+@@ -1325,14 +1431,23 @@ static void cpu_bus_scan(device_t dev)
  	/* Always use the devicetree node with lapic_id 0 for BSP. */
  	remap_bsp_lapic(cpu_bus);
  
@@ -3048,10 +3336,10 @@ index d0a0787..a29dad9 100644
  
  		busn = CONFIG_CBB;
  		devn = CONFIG_CDB+i;
-@@ -1368,7 +1483,16 @@ static void cpu_bus_scan(device_t dev)
+@@ -1372,7 +1487,16 @@ static void cpu_bus_scan(device_t dev)
  
  		f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
- 	
+ 
 -		if (cpuid_eax(0x80000001) >= 0x8)
 +		family = model = cpuid_eax(0x80000001);
 +		model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
@@ -3065,8 +3353,8 @@ index d0a0787..a29dad9 100644
 +		if ((model >= 0x8) || fam15h)
  			/* Revision D or later */
  			rev_gte_d = 1;
- 	
-@@ -1378,13 +1502,20 @@ static void cpu_bus_scan(device_t dev)
+ 
+@@ -1382,13 +1506,20 @@ static void cpu_bus_scan(device_t dev)
  				dual_node = 1;
  
  		cores_found = 0; // one core
@@ -3092,7 +3380,7 @@ index d0a0787..a29dad9 100644
  			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cdb_dev), cores_found);
  		}
  
-@@ -1404,15 +1535,24 @@ static void cpu_bus_scan(device_t dev)
+@@ -1408,15 +1539,24 @@ static void cpu_bus_scan(device_t dev)
  
  			if (dual_node) {
  				apic_id = 0;
@@ -3122,7 +3410,7 @@ index d0a0787..a29dad9 100644
  			}
  
  #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0)
-@@ -1422,6 +1562,9 @@ static void cpu_bus_scan(device_t dev)
+@@ -1426,6 +1566,9 @@ static void cpu_bus_scan(device_t dev)
  				}
  			}
  #endif
@@ -3132,7 +3420,7 @@ index d0a0787..a29dad9 100644
  			device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
  			if (cpu)
  				amd_cpu_topology(cpu, i, j);
-@@ -1478,6 +1621,6 @@ static void root_complex_enable_dev(struct device *dev)
+@@ -1484,6 +1627,6 @@ static void root_complex_enable_dev(struct device *dev)
  }
  
  struct chip_operations northbridge_amd_amdfam10_root_complex_ops = {
@@ -3141,10 +3429,10 @@ index d0a0787..a29dad9 100644
  	.enable_dev = root_complex_enable_dev,
  };
 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-index 9c2612c..4962c2a 100644
+index 5068e7a..cae228f 100644
 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
 +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-@@ -35,8 +35,120 @@ static  void print_tf(const char *func, const char *strval)
+@@ -44,8 +44,120 @@ static  void print_tf(const char *func, const char *strval)
  #endif
  }
  
@@ -3266,7 +3554,7 @@ index 9c2612c..4962c2a 100644
  	/* Return limited maximum RAM frequency */
  	if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
  		if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
-@@ -59,34 +171,178 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq
+@@ -68,34 +180,178 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq
  			}
  		}
  	} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
@@ -3465,7 +3753,7 @@ index 9c2612c..4962c2a 100644
  		}
  	}
  
-@@ -216,11 +472,13 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
+@@ -225,11 +481,13 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
  
  }
  
@@ -3708,10 +3996,10 @@ index 97f9db8..8f9177f 100644
  		Amdmemcpy((void *)nb, (const void *)&fam10, (u32) sizeof(cNorthBridge));
  	}
 diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
-index bafda10..0c6b474 100644
+index 389b1b1..c0ccc69 100644
 --- a/src/northbridge/amd/amdht/ht_wrapper.c
 +++ b/src/northbridge/amd/amdht/ht_wrapper.c
-@@ -172,16 +172,22 @@ static void amd_ht_fixup(struct sys_info *sysinfo) {
+@@ -174,16 +174,22 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
  	printk(BIOS_DEBUG, "amd_ht_fixup()\n");
  	if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) {
  		uint8_t rev_gte_d = 0;
@@ -3737,7 +4025,7 @@ index bafda10..0c6b474 100644
  			rev_gte_d = 1;
  
  		if (rev_gte_d) {
-@@ -193,7 +199,8 @@ static void amd_ht_fixup(struct sys_info *sysinfo) {
+@@ -195,7 +201,8 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
  
  			if (dual_node) {
  				/* Each G34 processor contains a defective HT link.
@@ -3747,7 +4035,7 @@ index bafda10..0c6b474 100644
  				*/
  				uint8_t node;
  				uint8_t node_count = get_nodes();
-@@ -203,46 +210,46 @@ static void amd_ht_fixup(struct sys_info *sysinfo) {
+@@ -205,46 +212,46 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
  					uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30);
  					printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number);
  					if (internal_node_number == 0) {
@@ -4116,7 +4404,7 @@ index c332357..fe56201 100644
  	tmp = pDCTstat->LogicalCPUID;
  	if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 303c6c7..c73cb26 100644
+index 12dfff1..74066b1 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -75,6 +75,8 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
@@ -4837,7 +5125,7 @@ index 303c6c7..c73cb26 100644
 +				/* 2 DIMMs detected */
 +				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 +				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+				
++
 +				if (MemClkFreq == 0x4) {
 +					/* DDR3-667 */
 +					calibration_code = 0x10222222;
@@ -4963,7 +5251,7 @@ index 303c6c7..c73cb26 100644
 +				/* 2 DIMMs detected */
 +				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 +				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+				
++
 +				if (MemClkFreq == 0x4) {
 +					/* DDR3-667 */
 +					calibration_code = 0x00390039;
@@ -5053,7 +5341,7 @@ index 303c6c7..c73cb26 100644
 +				/* 2 DIMMs detected */
 +				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 +				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+				
++
 +				if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
 +					|| (MemClkFreq == 0xa)) {
 +					/* DDR3-667 - DDR3-1066 */
@@ -5133,7 +5421,7 @@ index 303c6c7..c73cb26 100644
  static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  			struct DCTStatStruc *pDCTstatA)
  {
-@@ -277,41 +1224,75 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -277,10 +1224,26 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  restartinit:
  	mctInitMemGPIOs_A_D();		/* Set any required GPIOs*/
  	if (s3resume) {
@@ -5145,8 +5433,10 @@ index 303c6c7..c73cb26 100644
 +			mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat);
 +		}
 +
+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
  		restore_mct_information_from_nvram();
+ #endif
 +
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
 +		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -5158,26 +5448,14 @@ index 303c6c7..c73cb26 100644
  	} else {
  		NodesWmem = 0;
  		node_sys_base = 0;
- 		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
- 			struct DCTStatStruc *pDCTstat;
- 			pDCTstat = pDCTstatA + Node;
--	
-+
- 			/* Zero out data structures to avoid false detection of DIMMs */
- 			memset(pDCTstat, 0, sizeof(struct DCTStatStruc));
--	
-+
- 			/* Initialize data structures */
- 			pDCTstat->Node_ID = Node;
- 			pDCTstat->dev_host = PA_HOST(Node);
+@@ -297,15 +1260,15 @@ restartinit:
  			pDCTstat->dev_map = PA_MAP(Node);
  			pDCTstat->dev_dct = PA_DCT(Node);
  			pDCTstat->dev_nbmisc = PA_NBMISC(Node);
 +			pDCTstat->dev_link = PA_LINK(Node);
 +			pDCTstat->dev_nbctl = PA_NBCTL(Node);
  			pDCTstat->NodeSysBase = node_sys_base;
--	
-+
+ 
  			printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_init Node %d\n", Node);
  			mct_init(pMCTstat, pDCTstat);
  			mctNodeIDDebugPort_D();
@@ -5187,16 +5465,12 @@ index 303c6c7..c73cb26 100644
 -				clear_legacy_Mode(pMCTstat, pDCTstat);
 +			if (pDCTstat->NodePresent) {
  				pDCTstat->LogicalCPUID = mctGetLogicalCPUID_D(Node);
--	
-+
+ 
  				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_InitialMCT_D\n");
- 				mct_InitialMCT_D(pMCTstat, pDCTstat);
--	
-+
+@@ -314,6 +1277,26 @@ restartinit:
  				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctSMBhub_Init\n");
  				mctSMBhub_Init(Node);		/* Switch SMBUS crossbar to proper node*/
--	
-+
+ 
 +				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_preInitDCT\n");
 +				mct_preInitDCT(pMCTstat, pDCTstat);
 +			}
@@ -5204,8 +5478,10 @@ index 303c6c7..c73cb26 100644
 +			node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F;
 +		}
 +
++#if IS_ENABLED(DIMM_VOLTAGE_SET_SUPPORT)
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: DIMMSetVoltage\n");
 +		DIMMSetVoltages(pMCTstat, pDCTstatA);	/* Set the DIMM voltages (mainboard specific) */
++#endif
 +
 +		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
 +			struct DCTStatStruc *pDCTstat;
@@ -5218,7 +5494,7 @@ index 303c6c7..c73cb26 100644
  				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_initDCT\n");
  				mct_initDCT(pMCTstat, pDCTstat);
  				if (pDCTstat->ErrCode == SC_FatalErr) {
-@@ -319,17 +1300,12 @@ restartinit:
+@@ -321,20 +1304,13 @@ restartinit:
  				} else if (pDCTstat->ErrCode < SC_StopError) {
  					NodesWmem++;
  				}
@@ -5231,13 +5507,16 @@ index 303c6c7..c73cb26 100644
  			printk(BIOS_DEBUG, "No Nodes?!\n");
  			goto fatalexit;
  		}
--
+ 
+-#if IS_ENABLED(DIMM_VOLTAGE_SET_SUPPORT)
 -		printk(BIOS_DEBUG, "mctAutoInitMCT_D: DIMMSetVoltage\n");
 -		DIMMSetVoltages(pMCTstat, pDCTstatA);	/* Set the DIMM voltages (mainboard specific) */
- 	
+-#endif
+-
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n");
  		SyncDCTsReady_D(pMCTstat, pDCTstatA);	/* Make sure DCTs are ready for accesses.*/
-@@ -351,7 +1327,6 @@ restartinit:
+ 
+@@ -355,7 +1331,6 @@ restartinit:
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
  		mct_OtherTiming(pMCTstat, pDCTstatA);
  
@@ -5245,7 +5524,7 @@ index 303c6c7..c73cb26 100644
  		if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/
  			goto restartinit;
  		}
-@@ -365,6 +1340,14 @@ restartinit:
+@@ -369,6 +1344,14 @@ restartinit:
  			MCTMemClr_D(pMCTstat,pDCTstatA);
  		}
  
@@ -5260,7 +5539,7 @@ index 303c6c7..c73cb26 100644
  		mct_FinalMCT_D(pMCTstat, pDCTstatA);
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus);
  	}
-@@ -404,6 +1387,426 @@ static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
+@@ -408,6 +1391,425 @@ static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
  	return ret;
  }
  
@@ -5493,7 +5772,6 @@ index 303c6c7..c73cb26 100644
 +				continue;
 +
 +			read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg);
-+			
 +
 +			if (first_dimm) {
 +				memcpy(current_total_delay_1, current_total_delay_2, sizeof(current_total_delay_1));
@@ -5687,7 +5965,7 @@ index 303c6c7..c73cb26 100644
  static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstatA)
  {
-@@ -420,6 +1823,20 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -424,6 +1826,20 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  	mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
  	phyAssistedMemFnceTraining(pMCTstat, pDCTstatA);
  
@@ -5708,7 +5986,7 @@ index 303c6c7..c73cb26 100644
  	if (nv_DQSTrainCTL) {
  		mctHookBeforeAnyTraining(pMCTstat, pDCTstatA);
  		/* TODO: should be in mctHookBeforeAnyTraining */
-@@ -427,16 +1844,35 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -431,16 +1847,35 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  		_WRMSR(0x26D, 0x04040404, 0x04040404);
  		_WRMSR(0x26E, 0x04040404, 0x04040404);
  		_WRMSR(0x26F, 0x04040404, 0x04040404);
@@ -5723,14 +6001,11 @@ index 303c6c7..c73cb26 100644
  
 -		mct_TrainDQSPos_D(pMCTstat, pDCTstatA);
 +		mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass);
- 
--		/* Second Pass never used for Barcelona! */
--		/* TrainReceiverEn_D(pMCTstat, pDCTstatA, SecondPass); */
++
 +		if (is_fam15h()) {
 +			/* Receiver Enable Training Pass 2 */
 +			// TrainReceiverEn_D(pMCTstat, pDCTstatA, SecondPass);
- 
--		mctSetEccDQSRcvrEn_D(pMCTstat, pDCTstatA);
++
 +			/* TODO:
 +			 * Determine why running TrainReceiverEn_D in SecondPass
 +			 * mode yields less stable training values than when run
@@ -5740,9 +6015,12 @@ index 303c6c7..c73cb26 100644
 +		} else {
 +			TrainReceiverEn_D(pMCTstat, pDCTstatA, FirstPass);
 +		}
-+
+ 
+-		/* Second Pass never used for Barcelona! */
+-		/* TrainReceiverEn_D(pMCTstat, pDCTstatA, SecondPass); */
 +		mct_TrainDQSPos_D(pMCTstat, pDCTstatA);
-+
+ 
+-		mctSetEccDQSRcvrEn_D(pMCTstat, pDCTstatA);
 +		if (is_fam15h())
 +			exit_training_mode_fam15(pMCTstat, pDCTstatA);
 +		else
@@ -5750,7 +6028,7 @@ index 303c6c7..c73cb26 100644
  
  		/* FIXME - currently uses calculated value	TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */
  		mctHookAfterAnyTraining();
-@@ -472,7 +1908,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
+@@ -476,7 +1911,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
  			for (Channel = 0;Channel < 2; Channel++) {
  				/* there are four receiver pairs,
  				   loosely associated with chipselects.*/
@@ -5759,7 +6037,7 @@ index 303c6c7..c73cb26 100644
  				for (Receiver = 0; Receiver < 8; Receiver += 2) {
  					/* Set Receiver Enable Values */
  					mct_SetRcvrEnDly_D(pDCTstat,
-@@ -488,7 +1924,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
+@@ -492,7 +1927,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
  						txdqs = pDCTstat->CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane];
  						index = Table_DQSRcvEn_Offset[ByteLane >> 1];
  						index += (Receiver >> 1) * 3 + 0x10 + 0x20; /* Addl_Index */
@@ -5768,7 +6046,7 @@ index 303c6c7..c73cb26 100644
  						if (ByteLane & 1) { /* odd byte lane */
  							val &= ~(0xFF << 16);
  							val |= txdqs << 16;
-@@ -496,7 +1932,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
+@@ -500,7 +1935,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
  							val &= ~0xFF;
  							val |= txdqs;
  						}
@@ -5777,7 +6055,7 @@ index 303c6c7..c73cb26 100644
  					}
  				}
  			}
-@@ -506,7 +1942,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
+@@ -510,7 +1945,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
  
  			for (Channel = 0; Channel < 2; Channel++) {
  				u8 *p;
@@ -5786,7 +6064,7 @@ index 303c6c7..c73cb26 100644
  
  				/* NOTE:
  				 * when 400, 533, 667, it will support dimm0/1/2/3,
-@@ -521,7 +1957,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
+@@ -525,7 +1960,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
  					if (DIMM == 0) {
  						index = 0;	/* CHA Write Data Timing Low */
  					} else {
@@ -5795,7 +6073,7 @@ index 303c6c7..c73cb26 100644
  							index = 0x100 * DIMM;
  						} else {
  							break;
-@@ -530,23 +1966,23 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
+@@ -534,23 +1969,23 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
  					for (Dir = 0; Dir < 2; Dir++) {/* RD/WR */
  						p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir];
  						val = stream_to_int(p); /* CHA Read Data Timing High */
@@ -5825,7 +6103,7 @@ index 303c6c7..c73cb26 100644
  			}
  		}
  	}
-@@ -808,49 +2244,70 @@ finish:
+@@ -812,49 +2247,70 @@ finish:
  	return ret;
  }
  
@@ -5926,7 +6204,7 @@ index 303c6c7..c73cb26 100644
  	} else {
  		mct_EnDllShutdownSR(pMCTstat, pDCTstat, dct);
  	}
-@@ -872,20 +2329,24 @@ static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat,
+@@ -876,20 +2332,24 @@ static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat,
  		pDCTstat = pDCTstatA + Node;
  		mct_SyncDCTsReady(pDCTstat);
  	}
@@ -5962,7 +6240,7 @@ index 303c6c7..c73cb26 100644
  	/* wait 750us before any memory access can be made. */
  	mct_Wait(15000);
  }
-@@ -907,10 +2368,9 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
+@@ -911,10 +2371,9 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
  	 */
  	u32 val;
  	u32 dev;
@@ -5974,7 +6252,7 @@ index 303c6c7..c73cb26 100644
  	if (val & (1<<MemClkFreqVal)) {
  		mctHookBeforeDramInit();	/* generalized Hook */
  		if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)))
-@@ -925,23 +2385,23 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat,
+@@ -929,23 +2388,23 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat,
  {
  	u32 reg_end;
  	u32 dev = pDCTstat->dev_dct;
@@ -6003,7 +6281,7 @@ index 303c6c7..c73cb26 100644
  		val = 0;
  		reg += 4;
  	}
-@@ -960,6 +2420,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -964,6 +2423,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  	u16 Trp, Trrd, Trcd, Tras, Trc;
  	u8 Trfc[4];
  	u16 Tfaw;
@@ -6011,7 +6289,7 @@ index 303c6c7..c73cb26 100644
  	u32 DramTimingLo, DramTimingHi;
  	u8 tCK16x;
  	u16 Twtr;
-@@ -968,10 +2429,11 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -972,10 +2432,11 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  	u8 byte;
  	u32 dword;
  	u32 dev;
@@ -6024,7 +6302,7 @@ index 303c6c7..c73cb26 100644
  	/* Gather all DIMM mini-max values for cycle timing data */
  	Trp = 0;
  	Trrd = 0;
-@@ -1184,88 +2646,164 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -1188,88 +2649,164 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  
  	mctAdjustAutoCycTmg_D();
  
@@ -6202,9 +6480,7 @@ index 303c6c7..c73cb26 100644
 +			val |= Trfc[i-1];
 +		}
 +		DramTimingHi |= val << 20;
- 
--	if (pDCTstat->Speed > 4) {
--		DramTimingHi |= 1 << DisAutoRefresh;
++
 +		dev = pDCTstat->dev_dct;
 +		/* Twr */
 +		val = pDCTstat->Twr;
@@ -6239,7 +6515,9 @@ index 303c6c7..c73cb26 100644
 +			DramTimingLo |= val;
 +		}
 +		Set_NB32_DCT(dev, dct, 0x88, DramTimingLo);	/*DCT Timing Low*/
-+
+ 
+-	if (pDCTstat->Speed > 4) {
+-		DramTimingHi |= 1 << DisAutoRefresh;
 +		if (pDCTstat->Speed > mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
 +			DramTimingHi |= 1 << DisAutoRefresh;
 +		}
@@ -6255,7 +6533,7 @@ index 303c6c7..c73cb26 100644
  }
  
  static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
-@@ -1299,6 +2837,8 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -1303,6 +2840,8 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
  	 * timing mode is 'Auto'.
  	 */
  
@@ -6264,7 +6542,7 @@ index 303c6c7..c73cb26 100644
  	/* Get primary timing (CAS Latency and Cycle Time) */
  	if (pDCTstat->Speed == 0) {
  		mctGet_MaxLoadFreq(pDCTstat);
-@@ -1308,6 +2848,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -1312,6 +2851,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
  
  		/* Go get best T and CL as specified by DIMM mfgs. and OEM */
  		SPDGetTCL_D(pMCTstat, pDCTstat, dct);
@@ -6272,7 +6550,7 @@ index 303c6c7..c73cb26 100644
  		/* skip callback mctForce800to1067_D */
  		pDCTstat->Speed = pDCTstat->DIMMAutoSpeed;
  		pDCTstat->CASL = pDCTstat->DIMMCASL;
-@@ -1340,7 +2881,10 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
+@@ -1344,7 +2884,10 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
  	u16 word;
  
  	/* Get CPU Si Revision defined limit (NPT) */
@@ -6284,7 +6562,7 @@ index 303c6c7..c73cb26 100644
  
  	/*Get User defined limit if  "limit" mode */
  	if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
-@@ -1377,6 +2921,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
+@@ -1381,6 +2924,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
  	u16 tCKmin16x;
  	u16 tCKproposed16x;
  	u8 CLactual, CLdesired, CLT_Fail;
@@ -6292,7 +6570,7 @@ index 303c6c7..c73cb26 100644
  
  	u8 smbaddr, byte = 0, bytex = 0;
  
-@@ -1386,6 +2931,17 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
+@@ -1390,6 +2934,17 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
  	tCKmin16x = 0;
  	CLT_Fail = 0;
  
@@ -6310,7 +6588,7 @@ index 303c6c7..c73cb26 100644
  	for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) {
  		if (pDCTstat->DIMMValid & (1 << i)) {
  			smbaddr = Get_DIMMAddress_D(pDCTstat, (dct + i));
-@@ -1415,27 +2971,44 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
+@@ -1419,27 +2974,44 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
  				tCKmin16x = byte * MTB16x;
  		}
  	}
@@ -6370,7 +6648,7 @@ index 303c6c7..c73cb26 100644
  	}
  	/* Running through this loop twice:
  	   - First time find tCL at target frequency
-@@ -1474,27 +3047,42 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
+@@ -1478,27 +3050,42 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
  		/* get CL and T */
  		if (!CLT_Fail) {
  			bytex = CLactual;
@@ -6423,7 +6701,7 @@ index 303c6c7..c73cb26 100644
  			}
  		} else {
  			pDCTstat->DIMMAutoSpeed = byte;
-@@ -1515,29 +3103,21 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
+@@ -1519,29 +3106,21 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
  static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat, u8 dct)
  {
@@ -6464,7 +6742,7 @@ index 303c6c7..c73cb26 100644
  	mctHookAfterPSCfg();
  
  	return pDCTstat->ErrCode;
-@@ -1549,11 +3129,11 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -1553,11 +3132,11 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	u32 DramControl, DramTimingLo, Status;
  	u32 DramConfigLo, DramConfigHi, DramConfigMisc, DramConfigMisc2;
  	u32 val;
@@ -6477,7 +6755,7 @@ index 303c6c7..c73cb26 100644
  
  	DramConfigLo = 0;
  	DramConfigHi = 0;
-@@ -1573,12 +3153,10 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -1577,12 +3156,10 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	Status = pDCTstat->Status;
  
  	dev = pDCTstat->dev_dct;
@@ -6492,7 +6770,7 @@ index 303c6c7..c73cb26 100644
  
  	/* FIXME: Skip mct_checkForDxSupport */
  	/* REV_CALL mct_DoRdPtrInit if not Dx */
-@@ -1620,8 +3198,12 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -1624,8 +3201,12 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct);
  
  	/* Build Dram Config Hi Register Value */
@@ -6506,7 +6784,7 @@ index 303c6c7..c73cb26 100644
  	DramConfigHi |= 1 << MemClkFreqVal;
  
  	if (Status & (1 << SB_Registered))
-@@ -1654,7 +3236,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -1658,7 +3239,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  		val = 0x0f; /* recommended setting (default) */
  	DramConfigHi |= val << 24;
  
@@ -6515,7 +6793,7 @@ index 303c6c7..c73cb26 100644
  		DramConfigHi |= 1 << DcqArbBypassEn;
  
  	/* Build MemClkDis Value from Dram Timing Lo and
-@@ -1665,7 +3247,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -1669,7 +3250,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	    NV_AllMemClks <>0 AND SB_DiagClks ==0 */
  
  	/* Dram Timing Low (owns Clock Enable bits) */
@@ -6524,7 +6802,7 @@ index 303c6c7..c73cb26 100644
  	if (mctGet_NVbits(NV_AllMemClks) == 0) {
  		/* Special Jedec SPD diagnostic bit - "enable all clocks" */
  		if (!(pDCTstat->Status & (1<<SB_DiagClks))) {
-@@ -1696,28 +3278,34 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -1700,28 +3281,34 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  				}
  				dword++ ;
  			}
@@ -6572,7 +6850,7 @@ index 303c6c7..c73cb26 100644
  	mct_EarlyArbEn_D(pMCTstat, pDCTstat, dct);
  	mctHookAfterAutoCfg();
  
-@@ -1727,6 +3315,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -1731,6 +3318,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	printk(BIOS_DEBUG, "AutoConfig: ErrStatus %x\n", pDCTstat->ErrStatus);
  	printk(BIOS_DEBUG, "AutoConfig: ErrCode %x\n", pDCTstat->ErrCode);
  	printk(BIOS_DEBUG, "AutoConfig: Done\n\n");
@@ -6580,7 +6858,7 @@ index 303c6c7..c73cb26 100644
  AutoConfig_exit:
  	return pDCTstat->ErrCode;
  }
-@@ -1744,14 +3333,12 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
+@@ -1748,14 +3336,12 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
  	u32 val;
  	u32 reg;
  	u32 dev;
@@ -6595,7 +6873,7 @@ index 303c6c7..c73cb26 100644
  
  	BankAddrReg = 0;
  	for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel+=2) {
-@@ -1816,10 +3403,10 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
+@@ -1820,10 +3406,10 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
  				/*set ChipSelect population indicator odd bits*/
  				pDCTstat->CSPresent |= 1 << (ChipSel + 1);
  
@@ -6608,7 +6886,7 @@ index 303c6c7..c73cb26 100644
  		} else {
  			if (pDCTstat->DIMMSPDCSE & (1<<ChipSel))
  				pDCTstat->CSTestFail |= (1<<ChipSel);
-@@ -1843,8 +3430,8 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
+@@ -1847,8 +3433,8 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
  	if (!pDCTstat->CSPresent)
  		pDCTstat->ErrCode = SC_StopError;
  
@@ -6619,7 +6897,7 @@ index 303c6c7..c73cb26 100644
  
  	pDCTstat->CSPresent_DCT[dct] = pDCTstat->CSPresent;
  	/* dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); */
-@@ -1929,11 +3516,9 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
+@@ -1933,11 +3519,9 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
  	u16 word;
  	u32 dev;
  	u32 reg;
@@ -6631,7 +6909,7 @@ index 303c6c7..c73cb26 100644
  
  	_DSpareEn = 0;
  
-@@ -1970,11 +3555,11 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
+@@ -1974,11 +3558,11 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
  		BiggestBank = 0;
  		for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */
  			if (pDCTstat->CSPresent & (1 << q)) {  /* bank present? */
@@ -6647,7 +6925,7 @@ index 303c6c7..c73cb26 100644
  					val >>= 19;
  					val++;
  					val <<= 19;
-@@ -1990,7 +3575,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
+@@ -1994,7 +3578,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
  		if (BiggestBank !=0) {
  			curcsBase = nxtcsBase;		/* curcsBase=nxtcsBase*/
  			/* DRAM CS Base b Address Register offset */
@@ -6656,7 +6934,7 @@ index 303c6c7..c73cb26 100644
  			if (_DSpareEn) {
  				BiggestBank = 0;
  				val = 1 << Spare;	/* Spare Enable*/
-@@ -2009,7 +3594,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
+@@ -2013,7 +3597,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
  					}
  				}
  			}
@@ -6665,7 +6943,7 @@ index 303c6c7..c73cb26 100644
  			if (_DSpareEn)
  				_DSpareEn = 0;
  			else
-@@ -2020,9 +3605,9 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
+@@ -2024,9 +3608,9 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
  		/* bank present but disabled?*/
  		if ( pDCTstat->CSTestFail & (1 << p)) {
  			/* DRAM CS Base b Address Register offset */
@@ -6677,7 +6955,7 @@ index 303c6c7..c73cb26 100644
  		}
  	}
  
-@@ -2060,7 +3645,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -2064,7 +3648,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  	u16 i, j, k;
  	u8 smbaddr;
  	u8 SPDCtrl;
@@ -6686,7 +6964,7 @@ index 303c6c7..c73cb26 100644
  	u8 devwidth;
  	u16 DimmSlots;
  	u8 byte = 0, bytex;
-@@ -2073,6 +3658,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -2077,6 +3661,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  	SPDCtrl = mctGet_NVbits(NV_SPDCHK_RESTRT);
  
  	RegDIMMPresent = 0;
@@ -6694,7 +6972,7 @@ index 303c6c7..c73cb26 100644
  	pDCTstat->DimmQRPresent = 0;
  
  	for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) {
-@@ -2111,6 +3697,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -2115,6 +3700,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  						pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8);
  					for (k = 0; k < SPD_PARTN_LENGTH; k++)
  						pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k);
@@ -6702,7 +6980,7 @@ index 303c6c7..c73cb26 100644
  					pDCTstat->DimmRevisionNumber[i] = 0;
  					for (k = 0; k < 2; k++)
  						pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8);
-@@ -2134,6 +3721,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -2138,6 +3724,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  				} else {
  					pDCTstat->DimmRegistered[i] = 0;
  				}
@@ -6715,7 +6993,7 @@ index 303c6c7..c73cb26 100644
  				/* Check ECC capable */
  				byte = mctRead_SPD(smbaddr, SPD_BusWidth);
  				if (byte & JED_ECC) {
-@@ -2217,6 +3810,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -2221,6 +3813,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  	printk(BIOS_DEBUG, "\t DIMMPresence: DIMMValid=%x\n", pDCTstat->DIMMValid);
  	printk(BIOS_DEBUG, "\t DIMMPresence: DIMMPresent=%x\n", pDCTstat->DIMMPresent);
  	printk(BIOS_DEBUG, "\t DIMMPresence: RegDIMMPresent=%x\n", RegDIMMPresent);
@@ -6723,7 +7001,7 @@ index 303c6c7..c73cb26 100644
  	printk(BIOS_DEBUG, "\t DIMMPresence: DimmECCPresent=%x\n", pDCTstat->DimmECCPresent);
  	printk(BIOS_DEBUG, "\t DIMMPresence: DimmPARPresent=%x\n", pDCTstat->DimmPARPresent);
  	printk(BIOS_DEBUG, "\t DIMMPresence: Dimmx4Present=%x\n", pDCTstat->Dimmx4Present);
-@@ -2243,6 +3837,16 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -2247,6 +3840,16 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  				pDCTstat->Status |= 1<<SB_Registered;
  			}
  		}
@@ -6740,7 +7018,7 @@ index 303c6c7..c73cb26 100644
  		if (pDCTstat->DimmECCPresent != 0) {
  			if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) {
  				/* all DIMMs are ECC capable */
-@@ -2280,6 +3884,26 @@ static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i)
+@@ -2284,6 +3887,26 @@ static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i)
  	return p[i];
  }
  
@@ -6751,7 +7029,7 @@ index 303c6c7..c73cb26 100644
 +
 +	/* Preconfigure DCT0 */
 +	DCTPreInit_D(pMCTstat, pDCTstat, 0);
-+	
++
 +	/* Configure DCT1 if unganged and enabled*/
 +	if (!pDCTstat->GangedMode) {
 +		if (pDCTstat->DIMMValidDCT[1] > 0) {
@@ -6767,7 +7045,7 @@ index 303c6c7..c73cb26 100644
  static void mct_initDCT(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat)
  {
-@@ -2291,7 +3915,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
+@@ -2295,7 +3918,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
  	if (pDCTstat->ErrCode == SC_FatalErr) {
  		/* Do nothing goto exitDCTInit; any fatal errors? */
  	} else {
@@ -6776,7 +7054,7 @@ index 303c6c7..c73cb26 100644
  		if (!pDCTstat->GangedMode) {
  			if (pDCTstat->DIMMValidDCT[1] > 0) {
  				err_code = pDCTstat->ErrCode;		/* save DCT0 errors */
-@@ -2301,17 +3925,21 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
+@@ -2305,17 +3928,21 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
  					pDCTstat->ErrCode = err_code;	/* Using DCT0 Error code to update pDCTstat.ErrCode */
  			} else {
  				val = 1 << DisDramInterface;
@@ -6801,7 +7079,7 @@ index 303c6c7..c73cb26 100644
  	mct_DramInit_Sw_D(pMCTstat, pDCTstat, dct);
  	/* mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct); */
  }
-@@ -2339,7 +3967,8 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
+@@ -2343,7 +3970,8 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
  		if (byte)
  			pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); /* Set temp. to avoid setting of ganged mode */
  
@@ -6811,7 +7089,7 @@ index 303c6c7..c73cb26 100644
  			pDCTstat->GangedMode = 1;
  			/* valid 128-bit mode population. */
  			pDCTstat->Status |= 1 << SB_128bitmode;
-@@ -2383,10 +4012,8 @@ void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data)
+@@ -2387,10 +4015,8 @@ void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data)
  
  u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index)
  {
@@ -6822,7 +7100,7 @@ index 303c6c7..c73cb26 100644
  	index &= ~(1 << DctAccessWrite);
  	Set_NB32(dev, index_reg, index);
  	do {
-@@ -2401,7 +4028,6 @@ void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data)
+@@ -2405,7 +4031,6 @@ void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data)
  {
  	u32 dword;
  
@@ -6830,7 +7108,7 @@ index 303c6c7..c73cb26 100644
  	Set_NB32(dev, index_reg + 0x4, data);
  	index |= (1 << DctAccessWrite);
  	Set_NB32(dev, index_reg, index);
-@@ -2416,16 +4042,17 @@ static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat,
+@@ -2420,16 +4045,17 @@ static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat,
  {
  	/* mct_checkForCxDxSupport_D */
  	if (pDCTstat->LogicalCPUID & AMD_DR_GT_Bx) {
@@ -6852,7 +7130,7 @@ index 303c6c7..c73cb26 100644
  	}
  	return pDCTstat->ErrCode;
  }
-@@ -2451,9 +4078,9 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
+@@ -2455,9 +4081,9 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
  		i_end = dct + 1;
  	}
  	for (i=i_start; i<i_end; i++) {
@@ -6865,7 +7143,7 @@ index 303c6c7..c73cb26 100644
  	}
  
  	return pDCTstat->ErrCode;
-@@ -2507,14 +4134,14 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
+@@ -2511,14 +4137,14 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
  	}
  
  	if (pDCTstat->DIMMValidDCT[0] == 0) {
@@ -6884,7 +7162,7 @@ index 303c6c7..c73cb26 100644
  	}
  
  	printk(BIOS_DEBUG, "SPDCalcWidth: Status %x\n", pDCTstat->Status);
-@@ -2644,21 +4271,20 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
+@@ -2648,21 +4274,20 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat, u8 dct)
  {
  	u32 reg;
@@ -6910,7 +7188,7 @@ index 303c6c7..c73cb26 100644
  	val &= 0xffff0300;
  	dword = pDCTstat->TrwtTO;
  	val |= dword << 4;
-@@ -2670,10 +4296,10 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
+@@ -2674,10 +4299,10 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
  	val |= dword << 14;
  	dword = pDCTstat->TrwtWB;
  	val |= dword;
@@ -6924,7 +7202,7 @@ index 303c6c7..c73cb26 100644
  	val &= 0xFFFFC0FF;
  	dword = pDCTstat->Twrrd >> 2;
  	val |= dword << 8;
-@@ -2681,7 +4307,7 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
+@@ -2685,7 +4310,7 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
  	val |= dword << 10;
  	dword = pDCTstat->Trdrd >> 2;
  	val |= dword << 12;
@@ -6933,7 +7211,7 @@ index 303c6c7..c73cb26 100644
  }
  
  static void Get_Trdrd(struct MCTStatStruc *pMCTstat,
-@@ -2751,18 +4377,17 @@ static void Get_TrwtWB(struct MCTStatStruc *pMCTstat,
+@@ -2755,18 +4380,17 @@ static void Get_TrwtWB(struct MCTStatStruc *pMCTstat,
  static u8 Get_Latency_Diff(struct MCTStatStruc *pMCTstat,
  			   struct DCTStatStruc *pDCTstat, u8 dct)
  {
@@ -6955,7 +7233,7 @@ index 303c6c7..c73cb26 100644
  {
  	u8 Smallest, Largest;
  	u32 val;
-@@ -2772,12 +4397,12 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
+@@ -2776,12 +4400,12 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
  	   DqsRcvEnGrossDelay of any other DIMM is equal to the Critical
  	   Gross Delay Difference (CGDD) */
  	/* DqsRcvEn byte 1,0 */
@@ -6970,7 +7248,7 @@ index 303c6c7..c73cb26 100644
  	byte = val & 0xFF;
  	bytex = (val >> 8) & 0xFF;
  	if (bytex < Smallest)
-@@ -2786,7 +4411,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
+@@ -2790,7 +4414,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
  		Largest = byte;
  
  	/* DqsRcvEn byte 5,4 */
@@ -6979,7 +7257,7 @@ index 303c6c7..c73cb26 100644
  	byte = val & 0xFF;
  	bytex = (val >> 8) & 0xFF;
  	if (bytex < Smallest)
-@@ -2795,7 +4420,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
+@@ -2799,7 +4423,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
  		Largest = byte;
  
  	/* DqsRcvEn byte 7,6 */
@@ -6988,7 +7266,7 @@ index 303c6c7..c73cb26 100644
  	byte = val & 0xFF;
  	bytex = (val >> 8) & 0xFF;
  	if (bytex < Smallest)
-@@ -2805,7 +4430,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
+@@ -2809,7 +4433,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
  
  	if (pDCTstat->DimmECCPresent> 0) {
  		/*DqsRcvEn Ecc */
@@ -6997,7 +7275,7 @@ index 303c6c7..c73cb26 100644
  		byte = val & 0xFF;
  		bytex = (val >> 8) & 0xFF;
  		if (bytex < Smallest)
-@@ -2869,7 +4494,7 @@ static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat,
+@@ -2873,7 +4497,7 @@ static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat,
  }
  
  static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
@@ -7006,7 +7284,7 @@ index 303c6c7..c73cb26 100644
  					u32 index)
  {
  	u8 Smallest, Largest;
-@@ -2887,7 +4512,7 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
+@@ -2891,7 +4515,7 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
  
  	for (i=0; i < 8; i+=2) {
  		if ( pDCTstat->DIMMValid & (1 << i)) {
@@ -7015,7 +7293,7 @@ index 303c6c7..c73cb26 100644
  			val &= 0x00E000E0;
  			byte = (val >> 5) & 0xFF;
  			if (byte < Smallest)
-@@ -2925,7 +4550,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
+@@ -2929,7 +4553,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
  	Smallest = 3;
  	Largest = 0;
  	for (i=0; i < 2; i++) {
@@ -7024,7 +7302,7 @@ index 303c6c7..c73cb26 100644
  		val &= 0x60606060;
  		val >>= 5;
  		for (j=0; j < 4; j++) {
-@@ -2941,7 +4566,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
+@@ -2945,7 +4569,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
  
  	if (pDCTstat->DimmECCPresent > 0) {
  		index++;
@@ -7033,7 +7311,7 @@ index 303c6c7..c73cb26 100644
  		val &= 0x00000060;
  		val >>= 5;
  		byte = val & 0xFF;
-@@ -2961,25 +4586,30 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
+@@ -2965,25 +4589,30 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
  static void mct_PhyController_Config(struct MCTStatStruc *pMCTstat,
  				     struct DCTStatStruc *pDCTstat, u8 dct)
  {
@@ -7075,7 +7353,7 @@ index 303c6c7..c73cb26 100644
  		}
  	}
  
-@@ -3020,21 +4650,61 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -3024,21 +4653,61 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  				val &= ~(1 << 12);
  
  			val &= 0x0FFFFFFF;
@@ -7150,7 +7428,7 @@ index 303c6c7..c73cb26 100644
  		}
  	}
  
-@@ -3051,16 +4721,103 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -3055,16 +4724,103 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  	}
  }
  
@@ -7257,7 +7535,7 @@ index 303c6c7..c73cb26 100644
  	return val;
  }
  
-@@ -3093,14 +4850,13 @@ static void clear_legacy_Mode(struct MCTStatStruc *pMCTstat,
+@@ -3097,14 +4853,13 @@ static void clear_legacy_Mode(struct MCTStatStruc *pMCTstat,
  
  	/* Clear Legacy BIOS Mode bit */
  	reg = 0x94;
@@ -7276,7 +7554,7 @@ index 303c6c7..c73cb26 100644
  }
  
  static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
-@@ -3167,7 +4923,7 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat,
+@@ -3171,7 +4926,7 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat,
  {
  	u32 val;
  	u32 dev = pDCTstat->dev_dct;
@@ -7285,7 +7563,7 @@ index 303c6c7..c73cb26 100644
  	u32 index;
  	u16 word;
  
-@@ -3182,9 +4938,9 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat,
+@@ -3186,9 +4941,9 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat,
  	}
  	word = (~word) & 0xFF;
  	index  = 0x0c;
@@ -7297,7 +7575,7 @@ index 303c6c7..c73cb26 100644
  }
  
  static void SetCKETriState(struct MCTStatStruc *pMCTstat,
-@@ -3192,7 +4948,7 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
+@@ -3196,7 +4951,7 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
  {
  	u32 val;
  	u32 dev;
@@ -7306,7 +7584,7 @@ index 303c6c7..c73cb26 100644
  	u32 index;
  	u16 word;
  
-@@ -3204,14 +4960,14 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
+@@ -3208,14 +4963,14 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
  	word = pDCTstat->CSPresent;
  
  	index  = 0x0c;
@@ -7323,7 +7601,7 @@ index 303c6c7..c73cb26 100644
  }
  
  static void SetODTTriState(struct MCTStatStruc *pMCTstat,
-@@ -3219,7 +4975,7 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
+@@ -3223,7 +4978,7 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
  {
  	u32 val;
  	u32 dev;
@@ -7332,7 +7610,7 @@ index 303c6c7..c73cb26 100644
  	u8 cs;
  	u32 index;
  	u8 odt;
-@@ -3253,86 +5009,281 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
+@@ -3257,86 +5012,281 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
  	}
  
  	index  = 0x0C;
@@ -7356,7 +7634,7 @@ index 303c6c7..c73cb26 100644
 +	uint32_t dev = pDCTstat->dev_dct;
 +
 +	printk(BIOS_DEBUG, "%s: Start\n", __func__);
-+
+ 
 +	/* Find current DDR supply voltage for this DCT */
 +	ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct);
 +
@@ -7414,7 +7692,7 @@ index 303c6c7..c73cb26 100644
 +		dword |= (amd_voltage_level_index << 2);
 +		Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f4009, dword);
 +	}
- 
++
 +	printk(BIOS_DEBUG, "%s: Done\n", __func__);
  }
  
@@ -7671,7 +7949,7 @@ index 303c6c7..c73cb26 100644
  }
  
  static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
-@@ -3355,9 +5306,9 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
+@@ -3359,9 +5309,9 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
  		NbDid |= 1;
  
  	reg = 0x94;
@@ -7683,7 +7961,7 @@ index 303c6c7..c73cb26 100644
  
  	val &= 0x07;
  	val += 3;
-@@ -3426,28 +5377,204 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
+@@ -3430,28 +5380,204 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
  }
  
  static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
@@ -7901,7 +8179,7 @@ index 303c6c7..c73cb26 100644
  
  			/* Obtain number of DIMMs on channel */
  			uint8_t dimm_count = pDCTstat->MAdimms[i];
-@@ -3459,7 +5586,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
+@@ -3463,7 +5589,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
  			uint32_t odt_pattern_3;
  
  			/* Select appropriate ODT pattern for installed DIMMs
@@ -7910,7 +8188,7 @@ index 303c6c7..c73cb26 100644
  			 */
  			if (pDCTstat->C_DCTPtr[i]->Status[DCT_STATUS_REGISTERED]) {
  				if (MaxDimmsInstallable == 2) {
-@@ -3570,10 +5697,10 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
+@@ -3574,10 +5700,10 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
  			}
  
  			/* Program ODT pattern */
@@ -7925,7 +8203,7 @@ index 303c6c7..c73cb26 100644
  		}
  	}
  }
-@@ -3581,34 +5708,32 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
+@@ -3585,34 +5711,32 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
  static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat, u8 dct)
  {
@@ -7970,7 +8248,7 @@ index 303c6c7..c73cb26 100644
  
  		DramConfigLo |=  /* DisDllShutdownSR */ 1 << 27;
  	}
-@@ -3700,52 +5825,61 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
+@@ -3704,52 +5828,61 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
  				DramMRS |= 1 << 23;
  		}
  	}
@@ -8068,7 +8346,7 @@ index 303c6c7..c73cb26 100644
  {
  	/* Bug#15114: Comp. update interrupted by Freq. change can cause
  	 * subsequent update to be invalid during any MemClk frequency change:
-@@ -3774,45 +5908,86 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
+@@ -3778,45 +5911,86 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
  	 */
  
  	u32 dev = pDCTstat->dev_dct;
@@ -8078,28 +8356,28 @@ index 303c6c7..c73cb26 100644
  
 -	u32 val;
 +	uint32_t dword;
- 
--	index = 0x08;
--	val = Get_NB32_index_wait(dev, index_reg, index);
--	if (!(val & (1 << DisAutoComp)))
--		Set_NB32_index_wait(dev, index_reg, index, val | (1 << DisAutoComp));
++
 +	if (is_fam15h()) {
 +		/* Initial setup for frequency change
 +		 * 9C_x0000_0004 must be configured before MemClkFreqVal is set
 +		 */
  
--	mct_Wait(100);
+-	index = 0x08;
+-	val = Get_NB32_index_wait(dev, index_reg, index);
+-	if (!(val & (1 << DisAutoComp)))
+-		Set_NB32_index_wait(dev, index_reg, index, val | (1 << DisAutoComp));
 +		/* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0x190 */
 +		dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006);
 +		dword &= ~(0x0000ffff);
 +		dword |= 0x00000190;
 +		Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword);
  
--	Set_NB32(dev, 0x94 + 0x100 * dct, DramConfigHi);
+-	mct_Wait(100);
 +		dword = Get_NB32_DCT(dev, dct, 0x94);
 +		dword &= ~(1 << MemClkFreqVal);
 +		Set_NB32_DCT(dev, dct, 0x94, dword);
-+
+ 
+-	Set_NB32(dev, 0x94 + 0x100 * dct, DramConfigHi);
 +		dword = DramConfigHi;
 +		dword &= ~(1 << MemClkFreqVal);
 +		Set_NB32_DCT(dev, dct, 0x94, dword);
@@ -8125,7 +8403,7 @@ index 303c6c7..c73cb26 100644
 +		do {
 +			dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94);
 +		} while (dword & (1 << FreqChgInProg));
-+	
++
 +		/* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0xf */
 +		dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006);
 +		dword &= ~(0x0000ffff);
@@ -8139,7 +8417,10 @@ index 303c6c7..c73cb26 100644
  {
 -	u8 Node;
 -	struct DCTStatStruc *pDCTstat;
--
++	if (!is_fam15h()) {
++		u8 Node;
++		struct DCTStatStruc *pDCTstat;
+ 
 -	/* Errata 178
 -	 *
 -	 * Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations
@@ -8153,14 +8434,6 @@ index 303c6c7..c73cb26 100644
 -	 */
 -	for (Node = 0; Node < 8; Node++) {
 -		pDCTstat = pDCTstatA + Node;
-+	if (!is_fam15h()) {
-+		u8 Node;
-+		struct DCTStatStruc *pDCTstat;
- 
--		if (pDCTstat->NodePresent) {
--			mct_BeforeDQSTrainSamp(pDCTstat); /* only Bx */
--			mct_ResetDLL_D(pMCTstat, pDCTstat, 0);
--			mct_ResetDLL_D(pMCTstat, pDCTstat, 1);
 +		/* Errata 178
 +		 *
 +		 * Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations
@@ -8174,7 +8447,11 @@ index 303c6c7..c73cb26 100644
 +		 */
 +		for (Node = 0; Node < 8; Node++) {
 +			pDCTstat = pDCTstatA + Node;
-+	
+ 
+-		if (pDCTstat->NodePresent) {
+-			mct_BeforeDQSTrainSamp(pDCTstat); /* only Bx */
+-			mct_ResetDLL_D(pMCTstat, pDCTstat, 0);
+-			mct_ResetDLL_D(pMCTstat, pDCTstat, 1);
 +			if (pDCTstat->NodePresent) {
 +				mct_BeforeDQSTrainSamp(pDCTstat); /* only Bx */
 +				mct_ResetDLL_D(pMCTstat, pDCTstat, 0);
@@ -8183,7 +8460,7 @@ index 303c6c7..c73cb26 100644
  		}
  	}
  }
-@@ -3823,7 +5998,6 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
+@@ -3827,7 +6001,6 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
  {
  	u8 Receiver;
  	u32 dev = pDCTstat->dev_dct;
@@ -8191,7 +8468,7 @@ index 303c6c7..c73cb26 100644
  	u32 addr;
  	u32 lo, hi;
  	u8 wrap32dis = 0;
-@@ -3834,6 +6008,11 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
+@@ -3838,6 +6011,11 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
  		return;
  	}
  
@@ -8203,7 +8480,7 @@ index 303c6c7..c73cb26 100644
  	addr = HWCR;
  	_RDMSR(addr, &lo, &hi);
  	if(lo & (1<<17)) {		/* save the old value */
-@@ -3853,11 +6032,11 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
+@@ -3857,11 +6035,11 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
  				mct_Read1LTestPattern_D(pMCTstat, pDCTstat, addr);	/* cache fills */
  
  				/* Write 0000_8000h to register F2x[1,0]9C_xD080F0C */
@@ -8217,7 +8494,7 @@ index 303c6c7..c73cb26 100644
  				mct_Wait(800); /* wait >= 2us */
  				break;
  			}
-@@ -3897,39 +6076,40 @@ static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat,
+@@ -3901,39 +6079,39 @@ static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat,
  static void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat, u8 dct)
  {
@@ -8265,33 +8542,32 @@ index 303c6c7..c73cb26 100644
 +			val |= 1 < 13;
 +			Set_NB32_DCT(dev, dct, 0x9C, val);
 +			Set_NB32_DCT(dev, dct, 0x98, 0x4D080F10);
-+	
++
 +			/* Set bit13 PowerDown to register F2x[1, 0]98_x0D080F11 */
 +			Set_NB32_DCT(dev, dct, 0x98, 0x0D080F11);
 +			val = Get_NB32_DCT(dev, dct, 0x9C);
 +			val |= 1 < 13;
 +			Set_NB32_DCT(dev, dct, 0x9C, val);
 +			Set_NB32_DCT(dev, dct, 0x98, 0x4D080F11);
-+	
++
 +			/* Set bit13 PowerDown to register F2x[1, 0]98_x0D088F30 */
 +			Set_NB32_DCT(dev, dct, 0x98, 0x0D088F30);
 +			val = Get_NB32_DCT(dev, dct, 0x9C);
 +			val |= 1 < 13;
 +			Set_NB32_DCT(dev, dct, 0x9C, val);
 +			Set_NB32_DCT(dev, dct, 0x98, 0x4D088F30);
-+	
++
 +			/* Set bit13 PowerDown to register F2x[1, 0]98_x0D08CF30 */
 +			Set_NB32_DCT(dev, dct, 0x98, 0x0D08CF30);
 +			val = Get_NB32_DCT(dev, dct, 0x9C);
 +			val |= 1 < 13;
 +			Set_NB32_DCT(dev, dct, 0x9C, val);
 +			Set_NB32_DCT(dev, dct, 0x98, 0x4D08CF30);
-+	
 +		}
  	}
  }
  
-@@ -3957,7 +6137,6 @@ static void SyncSetting(struct DCTStatStruc *pDCTstat)
+@@ -3961,7 +6139,6 @@ static void SyncSetting(struct DCTStatStruc *pDCTstat)
  static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
  
  	u32 val;
@@ -8299,7 +8575,7 @@ index 303c6c7..c73cb26 100644
  	u32 dev = pDCTstat->dev_dct;
  
  	if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) {
-@@ -3965,16 +6144,16 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
+@@ -3969,16 +6146,16 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
  		val = Get_NB32(dev, 0x110);
  		if (!(val & (1 << DramEnabled))) {
  			/* If 50 us expires while DramEnable =0 then do the following */
@@ -8719,7 +8995,7 @@ index f1fd7a5..a1cdfa6 100644
  		}
  	}	/* DoIntlv */
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 8572243..e74545b 100644
+index cc2f43a..740edae 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -18,6 +18,12 @@
@@ -9527,7 +9803,7 @@ index 8572243..e74545b 100644
 +				}
 +				last_pos = 0;
 +			}
-+	
++
 +			if (best_count > 2) {
 +				/* Restore current settings of other (previously trained) lanes to the active array */
 +				memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay));
@@ -9573,7 +9849,7 @@ index 8572243..e74545b 100644
 +				}
 +				last_pos = 0;
 +			}
-+	
++
 +			if (best_count > 2) {
 +				/* Restore current settings of other (previously trained) lanes to the active array */
 +				memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay));
@@ -9653,7 +9929,7 @@ index 8572243..e74545b 100644
 +					}
 +				}
 +			}
-+	
++
 +		}
 +#endif
 +	}
@@ -9747,11 +10023,11 @@ index 8572243..e74545b 100644
 +				/* 2.10.5.8.3 (1) */
 +				dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8));
 +				dword |= (0x1 << 8);								/* BlockRxDqsLock = 1 */
-+				Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword);	
-+	
++				Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword);
++
 +				/* 2.10.5.8.3 (3) */
 +				rx_en_offset = (initial_phy_phase_delay[lane] + 0x10) % 0x40;
-+	
++
 +				/* 2.10.5.8.3 (4) */
 +				for (current_phy_phase_delay[lane] = rx_en_offset; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) {
 +					/* 2.10.5.8.3 (4 A) */
@@ -9759,7 +10035,7 @@ index 8572243..e74545b 100644
 +
 +					/* Calculate and program MaxRdLatency */
 +					Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct);
-+	
++
 +					/* 2.10.5.8.3 (4 B) */
 +					dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1);
 +				}
@@ -9795,7 +10071,7 @@ index 8572243..e74545b 100644
 +				/* 2.10.5.8.3 (6) */
 +				dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8));
 +				dword &= ~(0x1 << 8);								/* BlockRxDqsLock = 0 */
-+				Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword);	
++				Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword);
 +			}
 +
 +#if DQS_TRAIN_DEBUG > 0
@@ -10021,7 +10297,7 @@ index 8572243..e74545b 100644
  	val &= ~0xe007c01f;
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
-index 0c52791..968f5e5 100644
+index 0c52791..11f1b2c 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 @@ -2,6 +2,7 @@
@@ -10044,13 +10320,13 @@ index 0c52791..968f5e5 100644
  
 -	OB_ChipKill = mctGet_NVbits(NV_ChipKill); 	/* ECC Chip-kill mode */
 +	OB_ChipKill = mctGet_NVbits(NV_ChipKill); 		/* ECC Chip-kill mode */
++	OF_ScrubCTL = 0;					/* Scrub CTL for Dcache, L2, and dram */
  
 -	OF_ScrubCTL = 0;		/* Scrub CTL for Dcache, L2, and dram */
 -	nvbits = mctGet_NVbits(NV_DCBKScrub);
 -	/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */
 -	OF_ScrubCTL |= (u32) nvbits << 16;
 +	if (!is_fam15h()) {
-+		OF_ScrubCTL = 0;				/* Scrub CTL for Dcache, L2, and dram */
 +		nvbits = mctGet_NVbits(NV_DCBKScrub);
 +		/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ 	/* Need not adjust */
 +		OF_ScrubCTL |= (u32) nvbits << 16;
@@ -11211,7 +11487,7 @@ index b21b96a..51cbf16 100644
  	}
  }
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index 587c414..039fcf8 100644
+index 91e8f77..011a94f 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 @@ -23,7 +23,10 @@
@@ -11843,7 +12119,7 @@ index 587c414..039fcf8 100644
  					}
  					/* 2.8.9.9.2 (7 A e)
  					 * Compare both read patterns and flag passing ranks/lanes
-@@ -534,7 +870,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
+@@ -533,7 +869,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
  				}
  
  				/* Update delays in hardware */
@@ -11852,7 +12128,7 @@ index 587c414..039fcf8 100644
  
  				/* Save previous results for comparison in the next iteration */
  				for (lane = 0; lane < 8; lane++)
-@@ -588,7 +924,483 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
+@@ -587,7 +923,483 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
  		mct_SetMaxLatency_D(pDCTstat, Channel, CTLRMaxDelay); /* program Ch A/B MaxAsyncLat to correspond with max delay */
  	}
  
@@ -12266,7 +12542,7 @@ index 587c414..039fcf8 100644
 +				 * Program the DQS Receiver Enable delay values for each lane
 +				 */
 +				write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg);
-+	
++
 +				/* 2.10.5.8.2 (3)
 +				 * Program DqsRcvTrEn = 1
 +				 */
@@ -12337,7 +12613,7 @@ index 587c414..039fcf8 100644
  
  	if(_DisableDramECC) {
  		mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
-@@ -675,10 +1487,10 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat)
+@@ -674,10 +1486,10 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat)
  	}
  
  	for (ch=0; ch<ch_end; ch++) {
@@ -12351,7 +12627,7 @@ index 587c414..039fcf8 100644
  	}
  }
  
-@@ -719,7 +1531,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly,
+@@ -718,7 +1530,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly,
  		/* get the register index from table */
  		index = Table_DQSRcvEn_Offset[i >> 1];
  		index += Addl_Index;	/* DIMMx DqsRcvEn byte0 */
@@ -12360,7 +12636,7 @@ index 587c414..039fcf8 100644
  		if(i & 1) {
  			/* odd byte lane */
  			val &= ~(0x1ff << 16);
-@@ -729,7 +1541,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly,
+@@ -728,7 +1540,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly,
  			val &= ~0x1ff;
  			val |= (RcvrEnDly & 0x1ff);
  		}
@@ -12369,7 +12645,7 @@ index 587c414..039fcf8 100644
  	}
  
  }
-@@ -743,7 +1555,6 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
+@@ -742,7 +1554,6 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
  	u32 reg;
  	u32 SubTotal;
  	u32 index_reg;
@@ -12377,7 +12653,7 @@ index 587c414..039fcf8 100644
  	u32 val;
  
  	uint8_t cpu_val_n;
-@@ -778,17 +1589,16 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
+@@ -777,17 +1588,16 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
  		Channel = 0;
  
  	dev = pDCTstat->dev_dct;
@@ -12398,7 +12674,7 @@ index 587c414..039fcf8 100644
  	if(!(val & (1 << UnBuffDimm)))
  		SubTotal += 2;
  
-@@ -796,7 +1606,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
+@@ -795,7 +1605,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
  	 *  add 1, else add 2 to the sub-total.
  	 *  if (AddrCmdSetup || CsOdtSetup || CkeSetup) then K := K + 2;
  	 */
@@ -12407,7 +12683,7 @@ index 587c414..039fcf8 100644
  	if(!(val & 0x00202020))
  		SubTotal += 1;
  	else
-@@ -804,7 +1614,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
+@@ -803,7 +1613,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
  
  	/* If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs,
  	 * then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. */
@@ -12416,7 +12692,7 @@ index 587c414..039fcf8 100644
  	SubTotal += 8 - (val & 0x0f);
  
  	/* Convert bits 7-5 (also referred to as the coarse delay) of
-@@ -825,7 +1635,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
+@@ -824,7 +1634,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
  	 * clocks (NCLKs)
  	 */
  	SubTotal *= 200 * ((Get_NB32(pDCTstat->dev_nbmisc, 0xd4) & 0x1f) + 4);
@@ -12425,7 +12701,7 @@ index 587c414..039fcf8 100644
  	SubTotal = (SubTotal + (2 - 1)) / 2;	/* Round up */
  
  	/* Add "N" NCLKs to the sub-total. "N" represents part of the
-@@ -842,13 +1652,13 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
+@@ -841,13 +1651,13 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
  	/* Program the F2x[1, 0]78[MaxRdLatency] register with
  	 * the total delay value (in NCLKs).
  	 */
@@ -12442,7 +12718,7 @@ index 587c414..039fcf8 100644
  }
  
  static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
-@@ -878,7 +1688,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -877,7 +1687,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
  	u32 dword;
  	u8 dn = 4; /* TODO: Rev C could be 4 */
  	u32 dev = pDCTstat->dev_dct;
@@ -12451,7 +12727,7 @@ index 587c414..039fcf8 100644
  
  	/* FIXME: add Cx support */
  	dword = 0x00000000;
-@@ -886,7 +1696,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -885,7 +1695,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
  		for(j=0; j<dn; j++)
  			/* DIMM0 Write Data Timing Low */
  			/* DIMM0 Write ECC Timing */
@@ -12460,7 +12736,7 @@ index 587c414..039fcf8 100644
  	}
  
  	/* errata #180 */
-@@ -894,13 +1704,13 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -893,13 +1703,13 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
  	for(i=5; i<=6; i++) {
  		for(j=0; j<dn; j++)
  			/* DIMM0 Read DQS Timing Control Low */
@@ -12476,7 +12752,7 @@ index 587c414..039fcf8 100644
  }
  
  void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel)
-@@ -913,13 +1723,13 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel)
+@@ -912,13 +1722,13 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel)
  	u32 val;
  
  	dev = pDCTstat->dev_dct;
@@ -12492,7 +12768,7 @@ index 587c414..039fcf8 100644
  		print_debug_dqs_pair("\t\tSetEccDQSRcvrPos: ChipSel ",
  					ChipSel, " rcvr_delay ",  val, 2);
  		index += 3;
-@@ -1003,95 +1813,305 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
+@@ -1002,95 +1812,305 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
  	u8 Node = 0;
  	struct DCTStatStruc *pDCTstat;
  
@@ -13352,7 +13628,7 @@ index 1c3e322..0ff4484 100644
  }
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index 9f42d54..cbb34dc 100644
+index 9f42d54..7ea7901 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 @@ -30,13 +30,22 @@
@@ -13507,7 +13783,7 @@ index 9f42d54..cbb34dc 100644
 +		uint8_t index = (uint8_t)(MAX_BYTE_LANES * dimm);
 +
 +		/* Calculate the Critical Gross Delay */
-+		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {	
++		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
 +			/* Calculate the gross delay differential for this lane */
 +			gross_diff[ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane] + pDCTData->WLGrossDelay[index+ByteLane];
 +			gross_diff[ByteLane] -= pDCTData->WLSeedPreGrossDelay[index+ByteLane];
@@ -13818,7 +14094,7 @@ index 9f42d54..cbb34dc 100644
 +						if (rank == 0) {
 +							/* Get Rtt_WR for the current DIMM and rank */
 +							uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm]);
-+	
++
 +							/* Convert dynamic termination code to corresponding nominal termination code */
 +							if (dynamic_term == 0x200)
 +								tempW1 = 0x04;
@@ -15926,5 +16202,5 @@ index 47260f2..1d4eade 100644
  	return mctGetLogicalCPUID(node);
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0037-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch b/resources/libreboot/patch/kgpe-d16/0034-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch
index 0fbf1f4..9202333 100644
--- a/resources/libreboot/patch/kgpe-d16/0037-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch
+++ b/resources/libreboot/patch/kgpe-d16/0034-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch
@@ -1,23 +1,25 @@
-From d1d919c400ef903930b558c50a4b1880717b2995 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From cf1d449f1ac17478863403eb4154433b4fb4a3e7 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 5 Sep 2015 19:37:57 -0500
-Subject: [PATCH 037/146] mainboard/asus/kgpe-d16: Add initial Family 15h CPU
+Subject: [PATCH 034/139] mainboard/asus/kgpe-d16: Add initial Family 15h CPU
  support
 
+Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/Kconfig       |    1 +
- src/mainboard/asus/kgpe-d16/cmos.default  |    3 +-
- src/mainboard/asus/kgpe-d16/cmos.layout   |   15 +-
- src/mainboard/asus/kgpe-d16/devicetree.cb |    4 +
- src/mainboard/asus/kgpe-d16/resourcemap.c |  276 ++++++++++++++++++++++++++++-
- src/mainboard/asus/kgpe-d16/romstage.c    |   58 +++---
+ src/mainboard/asus/kgpe-d16/Kconfig       |   1 +
+ src/mainboard/asus/kgpe-d16/cmos.default  |   3 +-
+ src/mainboard/asus/kgpe-d16/cmos.layout   |  15 +-
+ src/mainboard/asus/kgpe-d16/devicetree.cb |   4 +
+ src/mainboard/asus/kgpe-d16/resourcemap.c | 276 +++++++++++++++++++++++++++++-
+ src/mainboard/asus/kgpe-d16/romstage.c    |  58 ++++---
  6 files changed, 326 insertions(+), 31 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
-index f9556fc..d0af47f 100644
+index 9471692..8906dee 100644
 --- a/src/mainboard/asus/kgpe-d16/Kconfig
 +++ b/src/mainboard/asus/kgpe-d16/Kconfig
-@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
  	select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
  	select SUPERIO_NUVOTON_NCT5572D
  	select PARALLEL_CPU_INIT
@@ -86,7 +88,7 @@ index 110e0bb..e55edc4 100644
  9     1     87.5%
  9     2     75.0%
 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
-index d0288da..9bff01e 100644
+index a172d89..18e337e 100644
 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb
 +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
 @@ -228,21 +228,25 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
@@ -408,7 +410,7 @@ index 3e240dc..3aab8b8 100644
 +	}
  }
 diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
-index 18e7c16..0df2447 100644
+index a3f3310..9ea7cec 100644
 --- a/src/mainboard/asus/kgpe-d16/romstage.c
 +++ b/src/mainboard/asus/kgpe-d16/romstage.c
 @@ -42,6 +42,7 @@
@@ -559,5 +561,5 @@ index 18e7c16..0df2447 100644
  		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
  		soft_reset();
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0035-cpu-amd-family_10h-family_15h-Add-Family-15h-microco.patch b/resources/libreboot/patch/kgpe-d16/0035-cpu-amd-family_10h-family_15h-Add-Family-15h-microco.patch
new file mode 100644
index 0000000..e7068f9
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0035-cpu-amd-family_10h-family_15h-Add-Family-15h-microco.patch
@@ -0,0 +1,28 @@
+From fa4ef470b6b41bdab0063e754df2a8ec8a805238 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 16 Oct 2015 14:08:32 -0500
+Subject: [PATCH 035/139] cpu/amd/family_10h-family_15h: Add Family 15h
+ microcode file
+
+Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/family_10h-family_15h/Makefile.inc | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
+index 5a81ab8..6cd2513 100644
+--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
+@@ -12,3 +12,8 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
+ cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
+ microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
+ microcode_amd.bin-type := microcode
++
++# Microcode for Family 15h
++cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
++microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
++microcode_amd_fam15h.bin-type := microcode
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0038-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch b/resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch
index 15adb85..cd1a613 100644
--- a/resources/libreboot/patch/kgpe-d16/0038-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch
+++ b/resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch
@@ -1,18 +1,20 @@
-From 59201912928ffcdbc4c7143548ceba490dea021a Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From fd67f1513d362a0a02f999b632c62b7b5c074a50 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 1 Jun 2015 20:35:42 -0500
-Subject: [PATCH 038/146] amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup
+Subject: [PATCH 036/139] amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup
  on Fam15h
 
+Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   12 +++++++-----
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++-----
  1 file changed, 7 insertions(+), 5 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index c73cb26..3eb6b17 100644
+index 74066b1..4677c73 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1839,11 +1839,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -1842,11 +1842,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  
  	if (nv_DQSTrainCTL) {
  		mctHookBeforeAnyTraining(pMCTstat, pDCTstatA);
@@ -32,5 +34,5 @@ index c73cb26..3eb6b17 100644
  
  		if (is_fam15h()) {
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch b/resources/libreboot/patch/kgpe-d16/0037-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch
index df6dee9..d8c5a24 100644
--- a/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch
+++ b/resources/libreboot/patch/kgpe-d16/0037-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch
@@ -1,16 +1,17 @@
-From a3709a31c062419544a607dfbca9a18773dad673 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5ae2feaab88902ab9d5bb95eab1ec396f9c01b9f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 1 Jun 2015 23:58:59 -0500
-Subject: [PATCH 039/146] cpu/amd/car: Add romstage BSP stack overrun
- detection
+Subject: [PATCH 037/139] cpu/amd/car: Add romstage BSP stack overrun detection
 
+Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/car/cache_as_ram.inc    |    6 +++++-
- src/cpu/amd/car/post_cache_as_ram.c |    8 ++++++++
+ src/cpu/amd/car/cache_as_ram.inc    | 6 +++++-
+ src/cpu/amd/car/post_cache_as_ram.c | 8 ++++++++
  2 files changed, 13 insertions(+), 1 deletion(-)
 
 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
-index ec70f67..9b29932 100644
+index 6542906..4ccde3f 100644
 --- a/src/cpu/amd/car/cache_as_ram.inc
 +++ b/src/cpu/amd/car/cache_as_ram.inc
 @@ -24,7 +24,7 @@
@@ -34,7 +35,7 @@ index ec70f67..9b29932 100644
  
  	jmp	CAR_FAM10_ap_out
 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
-index e7a41e5..b4d185e 100644
+index 257b41a..787bedd 100644
 --- a/src/cpu/amd/car/post_cache_as_ram.c
 +++ b/src/cpu/amd/car/post_cache_as_ram.c
 @@ -110,6 +110,14 @@ void post_cache_as_ram(void)
@@ -53,5 +54,5 @@ index e7a41e5..b4d185e 100644
  	handoff = romstage_handoff_find_or_add();
  	if (handoff != NULL)
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0040-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch b/resources/libreboot/patch/kgpe-d16/0038-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch
index 66fcd62..b0ad3b3 100644
--- a/resources/libreboot/patch/kgpe-d16/0040-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch
+++ b/resources/libreboot/patch/kgpe-d16/0038-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch
@@ -1,17 +1,20 @@
-From e27fed2f630fcc720bed48180ed8a527d4bcd5ce Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From e3a15e1b280319fc3c95617b46630b31cf9b571e Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 2 Jun 2015 13:25:23 -0500
-Subject: [PATCH 040/146] cpu/amd/car: Increase Family 10h CAR size limit to
+Subject: [PATCH 038/139] cpu/amd/car: Increase Family 10h CAR size limit to
  128k
 
 This resolves issues with 4-node (32-core) systems not having
 sufficient CAR memory to boot.
+
+Change-Id: I5378df7fe8c034ba30f7fdf454f81dd10a0c2ae4
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/car/post_cache_as_ram.c |    2 +-
+ src/cpu/amd/car/post_cache_as_ram.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
-index b4d185e..503a666 100644
+index 787bedd..2282cee 100644
 --- a/src/cpu/amd/car/post_cache_as_ram.c
 +++ b/src/cpu/amd/car/post_cache_as_ram.c
 @@ -114,7 +114,7 @@ void post_cache_as_ram(void)
@@ -24,5 +27,5 @@ index b4d185e..503a666 100644
  		printk(BIOS_WARNING, "BSP overran lower stack boundary.  Undefined behaviour may result!\n");
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch b/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch
new file mode 100644
index 0000000..9364346
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch
@@ -0,0 +1,33 @@
+From f14fb79d7a979b95ad94b35e5127dfa033b5734c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Tue, 2 Jun 2015 20:18:44 -0500
+Subject: [PATCH 039/139] cpu/amd/car: Move AP stacks below the BSP stack to
+ free up space
+
+Caching SPD data during startup requires additional CAR space.
+There was a large chunk of free space between the AP stack top and
+the BSP stack bottom; moving the AP stacks below the BSP stack
+allows this space to be utilized.
+
+Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/family_10h-family_15h/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
+index 7c47e27..81b1d1e 100644
+--- a/src/cpu/amd/family_10h-family_15h/Kconfig
++++ b/src/cpu/amd/family_10h-family_15h/Kconfig
+@@ -33,7 +33,7 @@ config DCACHE_RAM_SIZE
+ 
+ config DCACHE_BSP_STACK_SIZE
+ 	hex
+-	default 0x2000
++	default 0x4000
+ 
+ config DCACHE_BSP_STACK_SLUSH
+ 	hex
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0042-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch b/resources/libreboot/patch/kgpe-d16/0040-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch
index d7083a1..d70b895 100644
--- a/resources/libreboot/patch/kgpe-d16/0042-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch
+++ b/resources/libreboot/patch/kgpe-d16/0040-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch
@@ -1,16 +1,18 @@
-From 8eaa58398aa389dec27dd8290fcd8102fa27daa2 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From f26e90bcbbd7b5966ac353a7e7ba63fa188ffac0 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 2 Jun 2015 20:51:59 -0500
-Subject: [PATCH 042/146] northbridge/amd/amdmct: Read SPD data into cache to
+Subject: [PATCH 040/139] northbridge/amd/amdmct: Read SPD data into cache to
  decrease bootup time
 
+Change-Id: Ic16a927a3f1fc6f7cb1aea36a8abe8cc1999cb52
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |  161 ++++++++++++++-------------
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |    7 ++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 161 +++++++++++++++-------------
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |   7 ++
  2 files changed, 92 insertions(+), 76 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 3eb6b17..b79b6c9 100644
+index 4677c73..5344ff9 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -180,7 +180,7 @@ static void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat,
@@ -43,7 +45,7 @@ index 3eb6b17..b79b6c9 100644
  static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  			struct DCTStatStruc *pDCTstatA)
  {
-@@ -1273,7 +1287,7 @@ restartinit:
+@@ -1275,7 +1289,7 @@ restartinit:
  				mct_InitialMCT_D(pMCTstat, pDCTstat);
  
  				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctSMBhub_Init\n");
@@ -52,7 +54,7 @@ index 3eb6b17..b79b6c9 100644
  
  				printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_preInitDCT\n");
  				mct_preInitDCT(pMCTstat, pDCTstat);
-@@ -2432,7 +2446,6 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -2435,7 +2449,6 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  	u32 dword;
  	u32 dev;
  	u32 val;
@@ -60,7 +62,7 @@ index 3eb6b17..b79b6c9 100644
  
  	printk(BIOS_DEBUG, "%s: Start\n", __func__);
  
-@@ -2452,64 +2465,62 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -2455,64 +2468,62 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  	for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
  		LDIMM = i >> 1;
  		if (pDCTstat->DIMMValid & (1 << i)) {
@@ -140,7 +142,7 @@ index 3eb6b17..b79b6c9 100644
  			val *= MTB16x;
  			if (Tfaw < val)
  				Tfaw = val;
-@@ -2925,7 +2936,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
+@@ -2928,7 +2939,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
  	u8 CLactual, CLdesired, CLT_Fail;
  	uint16_t min_frequency_tck16x;
  
@@ -149,7 +151,7 @@ index 3eb6b17..b79b6c9 100644
  
  	CASLatLow = 0xFF;
  	CASLatHigh = 0xFF;
-@@ -2946,28 +2957,27 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
+@@ -2949,28 +2960,27 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
  
  	for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) {
  		if (pDCTstat->DIMMValid & (1 << i)) {
@@ -184,7 +186,7 @@ index 3eb6b17..b79b6c9 100644
  
  			if (tCKmin16x < byte * MTB16x)
  				tCKmin16x = byte * MTB16x;
-@@ -3338,7 +3348,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
+@@ -3341,7 +3351,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
  	u8 byte;
  	u16 word;
  	u32 dword;
@@ -192,7 +194,7 @@ index 3eb6b17..b79b6c9 100644
  
  	dev = pDCTstat->dev_dct;
  
-@@ -3349,16 +3358,14 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
+@@ -3352,16 +3361,14 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
  			byte -= 3;
  
  		if (pDCTstat->DIMMValid & (1<<byte)) {
@@ -212,7 +214,7 @@ index 3eb6b17..b79b6c9 100644
  			Ranks = ((byte >> 3) & 7) + 1;
  
  			/* Configure Bank encoding
-@@ -3453,46 +3460,42 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
+@@ -3456,46 +3463,42 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
  	 * and determine the width mode: 64-bit, 64-bit muxed, 128-bit.
  	 */
  	u8 i;
@@ -269,7 +271,7 @@ index 3eb6b17..b79b6c9 100644
  			if (byte != byte1) {
  				pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
  				break;
-@@ -3673,8 +3676,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3676,8 +3679,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  			status = mctRead_SPD(smbaddr, SPD_ByteUse);
  			if (status >= 0) { /* SPD access is ok */
  				pDCTstat->DIMMPresent |= 1 << i;
@@ -281,7 +283,7 @@ index 3eb6b17..b79b6c9 100644
  					if (byte == JED_DDR3SDRAM) {
  						/*Dimm is 'Present'*/
  						pDCTstat->DIMMValid |= 1 << i;
-@@ -3687,36 +3691,41 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3690,36 +3694,41 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  					} else {
  						/*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/
  						pDCTstat->ErrStatus |= 1<<SB_DIMMChkSum;
@@ -335,7 +337,7 @@ index 3eb6b17..b79b6c9 100644
  				if (byte == JED_RDIMM || byte == JED_MiniRDIMM) {
  					RegDIMMPresent |= 1 << i;
  					pDCTstat->DimmRegistered[i] = 1;
-@@ -3730,13 +3739,13 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3733,13 +3742,13 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  					pDCTstat->DimmLoadReduced[i] = 0;
  				}
  				/* Check ECC capable */
@@ -351,7 +353,7 @@ index 3eb6b17..b79b6c9 100644
  				if (devwidth == 0) {
  					/* DIMM is made with x4 or x16 drams */
  					pDCTstat->Dimmx4Present |= 1 << i;
-@@ -3746,7 +3755,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3749,7 +3758,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  					pDCTstat->Dimmx16Present |= 1 << i;
  				}
  
@@ -360,7 +362,7 @@ index 3eb6b17..b79b6c9 100644
  				byte &= 7;
  				if (byte == 3) { /* 4ranks */
  					/* if any DIMMs are QR, we have to make two passes through DIMMs*/
-@@ -3781,7 +3790,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3784,7 +3793,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  
  				/* check address mirror support for unbuffered dimm */
  				/* check number of registers on a dimm for registered dimm */
@@ -369,7 +371,7 @@ index 3eb6b17..b79b6c9 100644
  				if (RegDIMMPresent & (1 << i)) {
  					if ((byte & 3) > 1)
  						pDCTstat->MirrPresU_NumRegR |= 1 << i;
-@@ -3790,20 +3799,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3793,20 +3802,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  						pDCTstat->MirrPresU_NumRegR |= 1 << i;
  				}
  				/* Get byte62: Reference Raw Card information. We dont need it now. */
@@ -396,7 +398,7 @@ index 3eb6b17..b79b6c9 100644
  				pDCTstat->CtrlWrd4 |= (byte & 0xFF) << (i << 2); /* RC4 = SPD byte 71 [3:0] */
  				pDCTstat->CtrlWrd5 |= (byte >> 4) << (i << 2); /* RC5 = SPD byte 71 [7:4] */
  			}
-@@ -6182,14 +6191,14 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
+@@ -6184,14 +6193,14 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
   *  1010	001111	16	3	10	4GB
   *  1011	010111	16	3	11	8GB
   */
@@ -413,7 +415,7 @@ index 3eb6b17..b79b6c9 100644
  	if (byte_use & 0x80)
  		byte_use = 117;
  	else
-@@ -6197,7 +6206,7 @@ u8 crcCheck(u8 smbaddr)
+@@ -6199,7 +6208,7 @@ u8 crcCheck(u8 smbaddr)
  
  	CRC = 0;
  	for (Index = 0; Index < byte_use; Index ++) {
@@ -422,7 +424,7 @@ index 3eb6b17..b79b6c9 100644
  		CRC ^= byte << 8;
  		for (i=0; i<8; i++) {
  			if (CRC & 0x8000) {
-@@ -6207,5 +6216,5 @@ u8 crcCheck(u8 smbaddr)
+@@ -6209,5 +6218,5 @@ u8 crcCheck(u8 smbaddr)
  				CRC <<= 1;
  		}
  	}
@@ -455,5 +457,5 @@ index 50fbff7..5bb09b4 100644
  
  struct amd_s3_persistent_mct_channel_data {
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0043-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch b/resources/libreboot/patch/kgpe-d16/0041-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch
index d811553..ced4d6e 100644
--- a/resources/libreboot/patch/kgpe-d16/0043-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch
+++ b/resources/libreboot/patch/kgpe-d16/0041-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch
@@ -1,15 +1,17 @@
-From 5db1eb01a5e5a0ae52f25f648a0a4df0b8b02d78 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 25cdb73c425c4f6a074308a69e0225ea2ee657ab Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 4 Jun 2015 00:07:05 -0500
-Subject: [PATCH 043/146] cpu/amd/car: Initialize entire CAR space instead of
+Subject: [PATCH 041/139] cpu/amd/car: Initialize entire CAR space instead of
  only half
 
+Change-Id: If2b6c875e523f595e662d5d62322c3c3f96ccb4a
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/car/cache_as_ram.inc |    4 ++--
+ src/cpu/amd/car/cache_as_ram.inc | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
-index 9b29932..9c71270 100644
+index 4ccde3f..9edc41f 100644
 --- a/src/cpu/amd/car/cache_as_ram.inc
 +++ b/src/cpu/amd/car/cache_as_ram.inc
 @@ -460,12 +460,12 @@ fam10_end_part1:
@@ -28,5 +30,5 @@ index 9b29932..9c71270 100644
  	rep	stosl
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0041-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch b/resources/libreboot/patch/kgpe-d16/0041-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch
deleted file mode 100644
index f0404fe..0000000
--- a/resources/libreboot/patch/kgpe-d16/0041-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From a499ee73bf8abfdc91a2118f0de29e5625ed39a4 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Tue, 2 Jun 2015 20:18:44 -0500
-Subject: [PATCH 041/146] cpu/amd/car: Move AP stacks below the BSP stack to
- free up space
-
-Caching SPD data during startup requires additional CAR space.
-There was a large chunk of free space between the AP stack top and
-the BSP stack bottom; moving the AP stacks below the BSP stack
-allows this space to be utilized.
----
- src/cpu/amd/model_10xxx/Kconfig |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
-index ebd282a..79db42a 100644
---- a/src/cpu/amd/model_10xxx/Kconfig
-+++ b/src/cpu/amd/model_10xxx/Kconfig
-@@ -32,7 +32,7 @@ config DCACHE_RAM_SIZE
- 
- config DCACHE_BSP_STACK_SIZE
- 	hex
--	default 0x2000
-+	default 0x4000
- 
- config DCACHE_BSP_STACK_SLUSH
- 	hex
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0044-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch b/resources/libreboot/patch/kgpe-d16/0042-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch
index 4b38efd..d0f9f58 100644
--- a/resources/libreboot/patch/kgpe-d16/0044-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch
+++ b/resources/libreboot/patch/kgpe-d16/0042-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch
@@ -1,18 +1,20 @@
-From a1a3d844b273e794df56059cb15c9d22fc5fd087 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 32a016ee1dea33731b9994fe23a4c43421006f99 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 4 Jun 2015 00:10:03 -0500
-Subject: [PATCH 044/146] amd/amdmct/mct_ddr3: Improve SPD DIMM detect
+Subject: [PATCH 042/139] amd/amdmct/mct_ddr3: Improve SPD DIMM detect
  reliability
 
+Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   13 ++++++++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index b79b6c9..771d743 100644
+index 5344ff9..e60adb7 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -3654,6 +3654,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3657,6 +3657,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  	u8 devwidth;
  	u16 DimmSlots;
  	u8 byte = 0, bytex;
@@ -20,7 +22,7 @@ index b79b6c9..771d743 100644
  
  	/* preload data structure with addrs */
  	mctGet_DIMMAddr(pDCTstat, pDCTstat->Node_ID);
-@@ -3674,10 +3675,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -3677,10 +3678,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  			int status;
  			smbaddr = Get_DIMMAddress_D(pDCTstat, i);
  			status = mctRead_SPD(smbaddr, SPD_ByteUse);
@@ -43,5 +45,5 @@ index b79b6c9..771d743 100644
  					if (byte == JED_DDR3SDRAM) {
  						/*Dimm is 'Present'*/
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0045-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch b/resources/libreboot/patch/kgpe-d16/0043-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch
index 52ba598..8884130 100644
--- a/resources/libreboot/patch/kgpe-d16/0045-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch
+++ b/resources/libreboot/patch/kgpe-d16/0043-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch
@@ -1,21 +1,24 @@
-From 9874b958db2c994d3827af323bd6ab4c7306da23 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From dbe04aaef5ba56c90824eb62aea47e281b75149f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 4 Jun 2015 00:11:03 -0500
-Subject: [PATCH 045/146] amd/amdmct/mct_ddr3: Use training values from
+Subject: [PATCH 043/139] amd/amdmct/mct_ddr3: Use training values from
  previous boot if possible
 
 DRAM training accounts for most of the romstage startup time, yet
 if the hardware configuration has not changed from the previous boot
 the previously discovered training values are still valid.  Use them
 if the DIMM configuration has not changed since the last boot.
+
+Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.layout       |    1 +
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   |  202 ++++++++++++++++---------
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |    6 +
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |  173 ++++++++++++++++++---
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h |   10 +-
- src/northbridge/amd/amdmct/wrappers/mcti_d.c  |   10 --
- 6 files changed, 299 insertions(+), 103 deletions(-)
+ src/mainboard/asus/kgpe-d16/cmos.layout       |   1 +
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   | 206 +++++++++++++++++---------
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |   6 +
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 175 +++++++++++++++++++---
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.h |  10 +-
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c  |   4 +
+ 6 files changed, 308 insertions(+), 94 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout
 index e55edc4..7944631 100644
@@ -30,7 +33,7 @@ index e55edc4..7944631 100644
  728        256       h       0        user_data
  984         16       h       0        check_sum
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 771d743..779d9ad 100644
+index e60adb7..20e66f2 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -39,7 +39,8 @@
@@ -218,10 +221,11 @@ index 771d743..779d9ad 100644
  					/* DDR3-1333 - DDR3-1600 */
  					slow_access = 1;
  				}
-@@ -1184,6 +1164,28 @@ static void read_spd_bytes(struct MCTStatStruc *pMCTstat,
+@@ -1184,6 +1164,30 @@ static void read_spd_bytes(struct MCTStatStruc *pMCTstat,
  	}
  }
  
++#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 +static void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat,
 +				struct DCTStatStruc *pDCTstat)
 +{
@@ -243,11 +247,12 @@ index 771d743..779d9ad 100644
 +			pDCTstat->spd_data.nvram_spd_match = 0;
 +	}
 +}
++#endif
 +
  static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  			struct DCTStatStruc *pDCTstatA)
  {
-@@ -1232,6 +1234,8 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -1232,6 +1236,8 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  	 */
  	u8 Node, NodesWmem;
  	u32 node_sys_base;
@@ -256,16 +261,16 @@ index 771d743..779d9ad 100644
  
  	uint8_t s3resume = acpi_is_wakeup_s3();
  
-@@ -1247,7 +1251,7 @@ restartinit:
- 		}
+@@ -1248,7 +1254,7 @@ restartinit:
  
+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
 -		restore_mct_information_from_nvram();
 +		restore_mct_information_from_nvram(0);
+ #endif
  
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
- 		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
-@@ -1296,9 +1300,24 @@ restartinit:
+@@ -1298,11 +1304,26 @@ restartinit:
  			node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F;
  		}
  
@@ -273,8 +278,10 @@ index 771d743..779d9ad 100644
 +		nvram = 0;
 +		set_option("allow_spd_nvram_cache_restore", &nvram);
 +
+ #if IS_ENABLED(DIMM_VOLTAGE_SET_SUPPORT)
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: DIMMSetVoltage\n");
  		DIMMSetVoltages(pMCTstat, pDCTstatA);	/* Set the DIMM voltages (mainboard specific) */
+ #endif
  
 +		/* If DIMM configuration has not changed since last boot restore training values */
 +		allow_config_restore = 1;
@@ -290,7 +297,7 @@ index 771d743..779d9ad 100644
  		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
  			struct DCTStatStruc *pDCTstat;
  			pDCTstat = pDCTstatA + Node;
-@@ -1332,14 +1351,33 @@ restartinit:
+@@ -1336,14 +1357,33 @@ restartinit:
  		CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */
  		mctHookAfterCPU();			/* Setup external northbridge(s) */
  
@@ -327,7 +334,7 @@ index 771d743..779d9ad 100644
  
  		if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/
  			goto restartinit;
-@@ -1822,7 +1860,7 @@ static void exit_training_mode_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1825,7 +1865,7 @@ static void exit_training_mode_fam15(struct MCTStatStruc *pMCTstat,
  }
  
  static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
@@ -336,7 +343,7 @@ index 771d743..779d9ad 100644
  {
  	u8 nv_DQSTrainCTL;
  
-@@ -1830,9 +1868,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -1833,9 +1873,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  		return;
  	}
  
@@ -348,7 +355,7 @@ index 771d743..779d9ad 100644
  
  	mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
  	phyAssistedMemFnceTraining(pMCTstat, pDCTstatA);
-@@ -1851,15 +1888,16 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -1854,15 +1893,16 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  		}
  	}
  
@@ -373,7 +380,7 @@ index 771d743..779d9ad 100644
  		mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass);
  
  		if (is_fam15h()) {
-@@ -1889,18 +1927,23 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -1892,18 +1932,25 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  			exit_training_mode_fam15(pMCTstat, pDCTstatA);
  		else
  			mctSetEccDQSRcvrEn_D(pMCTstat, pDCTstatA);
@@ -391,8 +398,10 @@ index 771d743..779d9ad 100644
 -		LoadDQSSigTmgRegs_D(pMCTstat, pDCTstatA);	/* load values into registers.*/
 -		/* mctDoWarmResetMemClr_D(); */
 -		MCTMemClr_D(pMCTstat, pDCTstatA);
++#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n");
 +		restore_mct_information_from_nvram(1);
++#endif
 +
 +		if (is_fam15h())
 +			exit_training_mode_fam15(pMCTstat, pDCTstatA);
@@ -406,7 +415,7 @@ index 771d743..779d9ad 100644
  }
  
  static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
-@@ -3910,6 +3953,8 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
+@@ -3913,6 +3960,8 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat)
  {
  	u8 err_code;
@@ -415,14 +424,14 @@ index 771d743..779d9ad 100644
  
  	/* Preconfigure DCT0 */
  	DCTPreInit_D(pMCTstat, pDCTstat, 0);
-@@ -3924,6 +3969,27 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
+@@ -3927,6 +3976,27 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
  				pDCTstat->ErrCode = err_code;	/* Using DCT0 Error code to update pDCTstat.ErrCode */
  		}
  	}
 +
++#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 +	calculate_and_store_spd_hashes(pMCTstat, pDCTstat);
 +
-+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 +	if (load_spd_hashes_from_nvram(pDCTstat) < 0) {
 +		pDCTstat->spd_data.nvram_spd_match = 0;
 +	}
@@ -468,7 +477,7 @@ index 5bb09b4..539ecc3 100644
  } __attribute__((packed));
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index aa23951..5cdeeb0 100644
+index aa23951..fa1873a 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 @@ -26,8 +26,10 @@
@@ -499,7 +508,7 @@ index aa23951..5cdeeb0 100644
 +
 +	for (byte = 0; byte < 256; byte++)
 +		*spd_hash += (spd_data[byte] * prime) ^ (*spd_hash >> 23);
-+	
++
 +	*spd_hash = *spd_hash ^ (*spd_hash << 37);
 +}
 +
@@ -717,8 +726,9 @@ index aa23951..5cdeeb0 100644
 +	restore_mct_data_from_save_variable(persistent_data, training_only);
  
  	return 0;
- }
+-}
 \ No newline at end of file
++}
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h
 index dcddcad..82f73a7 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h
@@ -744,26 +754,28 @@ index dcddcad..82f73a7 100644
 +void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only);
 \ No newline at end of file
 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
-index 1d4eade..2e53f0b 100644
+index 1d4eade..af34d3b 100644
 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
-@@ -399,16 +399,6 @@ static void mctHookAfterCPU(void)
+@@ -399,14 +399,18 @@ static void mctHookAfterCPU(void)
  }
  
  
--static void mctSaveDQSSigTmg_D(void)
--{
--}
--
--
--static void mctGetDQSSigTmg_D(void)
--{
--}
--
--
- static void mctHookBeforeECC(void)
++#if IS_ENABLED(CONFIG_DIMM_DDR2)
+ static void mctSaveDQSSigTmg_D(void)
  {
  }
++#endif
+ 
+ 
++#if IS_ENABLED(CONFIG_DIMM_DDR2)
+ static void mctGetDQSSigTmg_D(void)
+ {
+ }
++#endif
+ 
+ 
+ static void mctHookBeforeECC(void)
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0046-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch b/resources/libreboot/patch/kgpe-d16/0044-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch
index 7b5b1f8..9ed1c3d 100644
--- a/resources/libreboot/patch/kgpe-d16/0046-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch
+++ b/resources/libreboot/patch/kgpe-d16/0044-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch
@@ -1,19 +1,21 @@
-From a56e3642d8003813e19d6685c7f8680e1b645b22 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From a8478c829628eb43b1222ad981600ff742d271e8 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 5 Jun 2015 21:13:30 -0500
-Subject: [PATCH 046/146] northbridge/amd/amdfam10: Enable CC6 DRAM save area
+Subject: [PATCH 044/139] northbridge/amd/amdfam10: Enable CC6 DRAM save area
  setup
 
+Change-Id: Ibeb35da3395dc77a21a2f92f0e1d0845be53d175
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/northbridge.c  |   70 ++++++++++++++
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |  132 +++++++++++++++++++++++++++
+ src/northbridge/amd/amdfam10/northbridge.c  |  70 +++++++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 132 ++++++++++++++++++++++++++++
  2 files changed, 202 insertions(+)
 
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index a29dad9..d13932c 100644
+index baf77d6..51eac77 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -704,6 +704,8 @@ struct chip_operations northbridge_amd_amdfam10_ops = {
+@@ -706,6 +706,8 @@ struct chip_operations northbridge_amd_amdfam10_ops = {
  static void amdfam10_domain_read_resources(device_t dev)
  {
  	unsigned reg;
@@ -22,7 +24,7 @@ index a29dad9..d13932c 100644
  
  	/* Find the already assigned resource pairs */
  	get_fx_devs();
-@@ -747,6 +749,74 @@ static void amdfam10_domain_read_resources(device_t dev)
+@@ -749,6 +751,74 @@ static void amdfam10_domain_read_resources(device_t dev)
  	/* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
  	ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
  #endif
@@ -56,12 +58,12 @@ index a29dad9..d13932c 100644
 +
 +				if ((dword >> 8) & 0x7)
 +					interleaved = 1;
-+		
++
 +				dword = f1_read_config32(0x44 + (range * 0x8));
 +				dword2 = f1_read_config32(0x144 + (range * 0x8));
 +				qword = ((((uint64_t)dword) >> 16) & 0xffff) << 24;
 +				qword |= (((uint64_t)dword2) & 0xff) << 40;
-+		
++
 +				if (qword > max_range_limit) {
 +					max_range = range;
 +					max_range_limit = qword;
@@ -98,12 +100,12 @@ index a29dad9..d13932c 100644
  
  static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 779d9ad..0e97715 100644
+index 20e66f2..2798506 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1186,6 +1186,100 @@ static void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat,
- 	}
+@@ -1188,6 +1188,100 @@ static void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat,
  }
+ #endif
  
 +static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
 +				struct DCTStatStruc *pDCTstat, uint8_t num_nodes)
@@ -202,7 +204,7 @@ index 779d9ad..0e97715 100644
  static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  			struct DCTStatStruc *pDCTstatA)
  {
-@@ -1235,6 +1329,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -1237,6 +1331,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
  	u8 Node, NodesWmem;
  	u32 node_sys_base;
  	uint8_t nvram;
@@ -210,7 +212,7 @@ index 779d9ad..0e97715 100644
  	uint8_t allow_config_restore;
  
  	uint8_t s3resume = acpi_is_wakeup_s3();
-@@ -1400,6 +1495,43 @@ restartinit:
+@@ -1406,6 +1501,43 @@ restartinit:
  			mct_ForceNBPState0_Dis_Fam15(pMCTstat, pDCTstat);
  		}
  
@@ -255,5 +257,5 @@ index 779d9ad..0e97715 100644
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus);
  	}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0047-mainboard-asus-kgpe-d16-Enable-CC6.patch b/resources/libreboot/patch/kgpe-d16/0045-mainboard-asus-kgpe-d16-Enable-CC6.patch
index aed8245..26ddad6 100644
--- a/resources/libreboot/patch/kgpe-d16/0047-mainboard-asus-kgpe-d16-Enable-CC6.patch
+++ b/resources/libreboot/patch/kgpe-d16/0045-mainboard-asus-kgpe-d16-Enable-CC6.patch
@@ -1,12 +1,14 @@
-From baa72eab99ba320f2975d3925d0dc90429cf8919 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 32b3afadc08bd155e25b12a0af8b11b629c064c3 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 5 Jun 2015 21:14:23 -0500
-Subject: [PATCH 047/146] mainboard/asus/kgpe-d16: Enable CC6
+Subject: [PATCH 045/139] mainboard/asus/kgpe-d16: Enable CC6
 
+Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.default      |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout       |    3 ++-
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |   10 +++++++++-
+ src/mainboard/asus/kgpe-d16/cmos.default      |  1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout       |  3 ++-
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 10 +++++++++-
  3 files changed, 12 insertions(+), 2 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -36,7 +38,7 @@ index 7944631..630219e 100644
  728        256       h       0        user_data
  984         16       h       0        check_sum
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index 5cdeeb0..24f78b2 100644
+index fa1873a..83c7b02 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 @@ -625,7 +625,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
@@ -64,5 +66,5 @@ index 5cdeeb0..24f78b2 100644
  	}
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0048-cpu-amd-Add-CC6-support.patch b/resources/libreboot/patch/kgpe-d16/0046-cpu-amd-Add-CC6-support.patch
index df8cc6d..026d843 100644
--- a/resources/libreboot/patch/kgpe-d16/0048-cpu-amd-Add-CC6-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0046-cpu-amd-Add-CC6-support.patch
@@ -1,30 +1,32 @@
-From ba75258bcf9104031d7c91c5ced514e0b03f8548 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 674911f61b4b32b0707962fa6a5a7e50811f721a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 8 Jun 2015 19:35:06 -0500
-Subject: [PATCH 048/146] cpu/amd: Add CC6 support
+Subject: [PATCH 046/139] cpu/amd: Add CC6 support
 
+Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/arch/x86/acpigen.c                         |   26 +++-
- src/arch/x86/include/arch/acpigen.h            |    3 +
- src/cpu/amd/model_10xxx/fidvid.c               |  170 ++++++++++++------------
- src/cpu/amd/model_10xxx/init_cpus.c            |   77 +++++++++++
- src/cpu/amd/model_10xxx/powernow_acpi.c        |  135 +++++++++++++++++--
- src/include/cpu/amd/powernow.h                 |    2 +
- src/mainboard/asus/kgpe-d16/cmos.default       |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout        |    5 +-
- src/northbridge/amd/amdfam10/link_control.c    |   78 +++++++++++
- src/northbridge/amd/amdfam10/northbridge.c     |   58 ++++----
- src/northbridge/amd/amdht/AsPsDefs.h           |    3 +-
- src/northbridge/amd/amdmct/amddefs.h           |   66 ++++-----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |   57 ++++----
- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c |    8 ++
- src/southbridge/amd/sb700/early_setup.c        |   20 ++-
- src/southbridge/amd/sb700/fadt.c               |    4 +
- src/southbridge/amd/sb700/sb700.h              |    7 +-
- src/southbridge/amd/sb700/sm.c                 |    5 +-
- src/southbridge/amd/sb800/fadt.c               |    3 +
- src/southbridge/amd/sb800/sb800.h              |    8 +-
- 20 files changed, 536 insertions(+), 200 deletions(-)
+ src/arch/x86/acpigen.c                            |  26 +++-
+ src/arch/x86/include/arch/acpigen.h               |   3 +
+ src/cpu/amd/family_10h-family_15h/fidvid.c        | 170 +++++++++++-----------
+ src/cpu/amd/family_10h-family_15h/init_cpus.c     |  80 ++++++++++
+ src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 135 +++++++++++++++--
+ src/include/cpu/amd/powernow.h                    |   2 +
+ src/mainboard/asus/kgpe-d16/cmos.default          |   1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout           |   5 +-
+ src/northbridge/amd/amdfam10/link_control.c       |  78 ++++++++++
+ src/northbridge/amd/amdfam10/northbridge.c        |  58 ++++----
+ src/northbridge/amd/amdht/AsPsDefs.h              |   3 +-
+ src/northbridge/amd/amdmct/amddefs.h              |  66 +++++----
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c       |  57 +++++---
+ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c    |   8 +
+ src/southbridge/amd/sb700/early_setup.c           |  20 ++-
+ src/southbridge/amd/sb700/fadt.c                  |   4 +
+ src/southbridge/amd/sb700/sb700.h                 |   7 +-
+ src/southbridge/amd/sb700/sm.c                    |   5 +-
+ src/southbridge/amd/sb800/fadt.c                  |   3 +
+ src/southbridge/amd/sb800/sb800.h                 |   8 +-
+ 20 files changed, 539 insertions(+), 200 deletions(-)
 
 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
 index 3aa823c..4136e65 100644
@@ -116,10 +118,10 @@ index a3e65eb..8e50960 100644
  void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
  void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list);
  void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
-diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
+diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
 index 2e26645..0e870e3 100644
---- a/src/cpu/amd/model_10xxx/fidvid.c
-+++ b/src/cpu/amd/model_10xxx/fidvid.c
+--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
 @@ -169,87 +169,87 @@ static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) {
  }
  
@@ -345,10 +347,10 @@ index 2e26645..0e870e3 100644
    	   printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
  	};
  
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index aced850..57b9b89 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index aced850..818431b 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -30,6 +30,14 @@
  #include <northbridge/amd/amdfam10/raminit_amdmct.c>
  #include <reset.h>
@@ -373,10 +375,11 @@ index aced850..57b9b89 100644
  
  	printk(BIOS_DEBUG, "cpuSetAMDMSR ");
  
-@@ -936,6 +946,39 @@ void cpuSetAMDMSR(uint8_t node_id)
+@@ -936,6 +946,42 @@ void cpuSetAMDMSR(uint8_t node_id)
  		wrmsr(FP_CFG, msr);
  	}
  
++#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
 +	if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
 +		/* Set up message triggered C1E */
 +		msr = rdmsr(0xc0010055);
@@ -396,10 +399,9 @@ index aced850..57b9b89 100644
 +
 +	if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) {
 +		enable_c_states = 0;
-+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-+		if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
-+			enable_c_states = !!nvram;
-+#endif
++		if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
++			if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
++				enable_c_states = !!nvram;
 +
 +		if (enable_c_states) {
 +			/* Set up the C-state base address */
@@ -409,11 +411,14 @@ index aced850..57b9b89 100644
 +			wrmsr(0xc0010073, c_state_addr_msr);
 +		}
 +	}
++#else
++	enable_c_states = 0;
++#endif
 +
  	printk(BIOS_DEBUG, " done\n");
  }
  
-@@ -950,6 +993,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -950,6 +996,7 @@ static void cpuSetAMDPCI(u8 node)
  	u32 platform;
  	u32 val;
  	u8 offset;
@@ -421,7 +426,7 @@ index aced850..57b9b89 100644
  	uint64_t revision;
  
  	printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
-@@ -1008,6 +1052,39 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1008,6 +1055,39 @@ static void cpuSetAMDPCI(u8 node)
  	   if (revision & (AMD_DR_B2 | AMD_DR_B3))
  	   dctPhyDiag(); */
  
@@ -461,10 +466,10 @@ index aced850..57b9b89 100644
  	printk(BIOS_DEBUG, " done\n");
  }
  
-diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c
-index 84e5514..8d94d1c 100644
---- a/src/cpu/amd/model_10xxx/powernow_acpi.c
-+++ b/src/cpu/amd/model_10xxx/powernow_acpi.c
+diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+index 84e5514..028ae3f 100644
+--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
++++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
 @@ -21,6 +21,7 @@
  
  #include <console/console.h>
@@ -567,7 +572,7 @@ index 84e5514..8d94d1c 100644
 +			/* TODO
 +			 * Detect dual core status and skip CSD generation if dual core is disabled
 +			 */
-+	
++
 +			/* Generate C state dependency entries */
 +			acpigen_write_CSD_package((cpu->path.apic.apic_id >> 1) & 0x7f, 2, CSD_HW_ALL, 0);
 +		}
@@ -807,10 +812,10 @@ index 1091ef4..4acd66c 100644
  
  	printk(BIOS_DEBUG, "done.\n");
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index d13932c..f777d02 100644
+index 51eac77..3fc31c0 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -768,53 +768,49 @@ static void amdfam10_domain_read_resources(device_t dev)
+@@ -770,53 +770,49 @@ static void amdfam10_domain_read_resources(device_t dev)
  			uint8_t num_nodes;
  
  			/* Find highest DRAM range (DramLimitAddr) */
@@ -826,12 +831,12 @@ index d13932c..f777d02 100644
 -
 -				if ((dword >> 8) & 0x7)
 -					interleaved = 1;
--		
+-
 -				dword = f1_read_config32(0x44 + (range * 0x8));
 -				dword2 = f1_read_config32(0x144 + (range * 0x8));
 -				qword = ((((uint64_t)dword) >> 16) & 0xffff) << 24;
 -				qword |= (((uint64_t)dword2) & 0xff) << 40;
--		
+-
 -				if (qword > max_range_limit) {
 -					max_range = range;
 -					max_range_limit = qword;
@@ -1020,10 +1025,10 @@ index 20a77d3..7aa4698 100644
 +#define AMD_PKGTYPE_C32 5
 \ No newline at end of file
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 0e97715..1442340 100644
+index 2798506..4044c36 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1195,6 +1195,7 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1197,6 +1197,7 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
  	int8_t max_range;
  	uint8_t max_node;
  	uint64_t max_range_limit;
@@ -1031,7 +1036,7 @@ index 0e97715..1442340 100644
  	uint32_t dword;
  	uint32_t dword2;
  	uint64_t qword;
-@@ -1214,7 +1215,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1216,7 +1217,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
  
  		dword = Get_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8));
  		dword2 = Get_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8));
@@ -1041,7 +1046,7 @@ index 0e97715..1442340 100644
  		qword |= (((uint64_t)dword2) & 0xff) << 40;
  
  		if (qword > max_range_limit) {
-@@ -1224,26 +1226,35 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1226,26 +1228,35 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
  		}
  	}
  
@@ -1097,7 +1102,7 @@ index 0e97715..1442340 100644
  	}
  
  	/* Determine save state destination node */
-@@ -1525,8 +1536,8 @@ restartinit:
+@@ -1531,8 +1542,8 @@ restartinit:
  					pDCTstat = pDCTstatA + Node;
  
  					if (pDCTstat->NodePresent) {
@@ -1107,7 +1112,7 @@ index 0e97715..1442340 100644
  					}
  				}
  			}
-@@ -5103,7 +5114,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
+@@ -5110,7 +5121,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
  		/* get base/limit from Node0 */
  		reg = 0x40 + (Node << 3);		/* Node0/Dram Base 0 */
  		val = Get_NB32(dev, reg);
@@ -1117,7 +1122,7 @@ index 0e97715..1442340 100644
  		reg = 0x44 + (Node << 3);		/* Node0/Dram Base 0 */
  		val = Get_NB32(dev, reg);
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
-index 968f5e5..c930380 100644
+index 11f1b2c..3a9fecc 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 @@ -159,6 +159,14 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
@@ -1235,10 +1240,10 @@ index b477091..941a4fd 100644
  extern void pm_iowrite(u8 reg, u8 value);
  extern u8 pm_ioread(u8 reg);
 diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
-index 3e6ddf1..200522a 100644
+index a4b78d0..81e3046 100644
 --- a/src/southbridge/amd/sb700/sm.c
 +++ b/src/southbridge/amd/sb700/sm.c
-@@ -112,7 +112,10 @@ static void sm_init(device_t dev)
+@@ -114,7 +114,10 @@ static void sm_init(device_t dev)
  	pci_write_config8(dev, 0x41, byte);
  
  	byte = pm_ioread(0x61);
@@ -1298,5 +1303,5 @@ index 9049182..3e3f077 100644
  void pm_iowrite(u8 reg, u8 value);
  u8 pm_ioread(u8 reg);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0049-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch b/resources/libreboot/patch/kgpe-d16/0047-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch
index eff8374..8bd1471 100644
--- a/resources/libreboot/patch/kgpe-d16/0049-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch
+++ b/resources/libreboot/patch/kgpe-d16/0047-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch
@@ -1,28 +1,30 @@
-From 3632ae70a8596e983588296158045552a0fdf33e Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From cac705ed59bc27d7eacdfdc16ed3c762fd41e84f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 8 Jun 2015 19:54:56 -0500
-Subject: [PATCH 049/146] northbridge/amd/amdmct: Skip DCT config write to
+Subject: [PATCH 047/139] northbridge/amd/amdmct: Skip DCT config write to
  Flash if unchanged
 
+Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   |    3 +++
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |    1 +
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |   21 +++++++++++++++++++--
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   |  3 +++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |  1 +
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 21 +++++++++++++++++++--
  3 files changed, 23 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 1442340..6d8c23e 100644
+index 4044c36..3edce9e 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1358,6 +1358,7 @@ restartinit:
- 
+@@ -1361,6 +1361,7 @@ restartinit:
+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
  		restore_mct_information_from_nvram(0);
 +		pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
+ #endif
  
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
- 		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
-@@ -2080,6 +2081,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -2087,6 +2088,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  
  		if (is_fam15h())
  			exit_training_mode_fam15(pMCTstat, pDCTstatA);
@@ -44,7 +46,7 @@ index 539ecc3..adf89b2 100644
  /*===============================================================================
  	Local DCT Status structure (a structure for each DCT)
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index 24f78b2..4c0e58d 100644
+index 83c7b02..1e5c1a0 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 @@ -213,7 +213,7 @@ static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t d
@@ -97,5 +99,5 @@ index 24f78b2..4c0e58d 100644
  	/* Obtain CBFS file offset */
  	s3nv_offset = get_s3nv_file_offset();
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0050-southbridge-amd-sb700-Add-AHCI-support.patch b/resources/libreboot/patch/kgpe-d16/0048-southbridge-amd-sb700-Add-AHCI-support.patch
index 8fde17c..ed4bd52 100644
--- a/resources/libreboot/patch/kgpe-d16/0050-southbridge-amd-sb700-Add-AHCI-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0048-southbridge-amd-sb700-Add-AHCI-support.patch
@@ -1,19 +1,21 @@
-From 2b426e29b8a34e7ce3ae479d6472d52687903165 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5c3cca2a8c938c140d6d217fd3fa9a646713678c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 9 Jun 2015 18:09:50 -0500
-Subject: [PATCH 050/146] southbridge/amd/sb700: Add AHCI support
+Subject: [PATCH 048/139] southbridge/amd/sb700: Add AHCI support
 
+Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/include/device/pci_ids.h             |    2 +
- src/mainboard/asus/kgpe-d16/Kconfig      |    4 +
- src/mainboard/asus/kgpe-d16/cmos.default |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout  |    3 +-
- src/southbridge/amd/sb700/Kconfig        |    4 +
- src/southbridge/amd/sb700/early_setup.c  |   73 ++++++---
- src/southbridge/amd/sb700/ide.c          |   42 +++--
- src/southbridge/amd/sb700/sata.c         |  264 ++++++++++++++++++++----------
- src/southbridge/amd/sb800/fadt.c         |    1 +
- 9 files changed, 271 insertions(+), 123 deletions(-)
+ src/include/device/pci_ids.h             |   2 +
+ src/mainboard/asus/kgpe-d16/Kconfig      |   4 +
+ src/mainboard/asus/kgpe-d16/cmos.default |   1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout  |   3 +-
+ src/southbridge/amd/sb700/Kconfig        |   4 +
+ src/southbridge/amd/sb700/early_setup.c  |  73 ++++++---
+ src/southbridge/amd/sb700/ide.c          |  42 +++--
+ src/southbridge/amd/sb700/sata.c         | 256 +++++++++++++++++++++----------
+ src/southbridge/amd/sb800/fadt.c         |   1 +
+ 9 files changed, 267 insertions(+), 119 deletions(-)
 
 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
 index fcaf4aa..664ac49 100644
@@ -29,10 +31,10 @@ index fcaf4aa..664ac49 100644
  #define PCI_DEVICE_ID_ATI_SB700_HDA		0x4383
  #define PCI_DEVICE_ID_ATI_SB700_PCI		0x4384
 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
-index d0af47f..9c359da 100644
+index 8906dee..75bf0ee 100644
 --- a/src/mainboard/asus/kgpe-d16/Kconfig
 +++ b/src/mainboard/asus/kgpe-d16/Kconfig
-@@ -88,6 +88,10 @@ config IRQ_SLOT_COUNT
+@@ -89,6 +89,10 @@ config IRQ_SLOT_COUNT
  	int
  	default 13
  
@@ -70,10 +72,10 @@ index 7f9f661..247fd7b 100644
  728        256       h       0        user_data
  984         16       h       0        check_sum
 diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
-index 064f32e..246b645 100644
+index f56f84a..92fb9ab 100644
 --- a/src/southbridge/amd/sb700/Kconfig
 +++ b/src/southbridge/amd/sb700/Kconfig
-@@ -45,6 +45,10 @@ config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
+@@ -46,6 +46,10 @@ config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
  	bool
  	default n
  
@@ -85,7 +87,7 @@ index 064f32e..246b645 100644
  	hex
  	default 0xfef00000
 diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
-index fd3b099..70a2aee 100644
+index fd3b099..a06a72f 100644
 --- a/src/southbridge/amd/sb700/early_setup.c
 +++ b/src/southbridge/amd/sb700/early_setup.c
 @@ -354,9 +354,13 @@ static void sb700_devices_por_init(void)
@@ -172,7 +174,7 @@ index fd3b099..70a2aee 100644
 +		dword &= ~(0xff << 16);		/* Sub-Class Code = 0x6 */
 +		dword |= (0x6 << 16);
 +		dword &= ~(0xff << 8);		/* Operating Mode Selection = 0x1 */
-+		dword |= (0x1 << 8);	
++		dword |= (0x1 << 8);
 +		pci_write_config32(dev, 0x08, dword);
 +	}
 +
@@ -269,7 +271,7 @@ index 8803d7f..4e07717 100644
  }
  
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index 172ad36..c0b3cd5 100644
+index 172ad36..d97288a 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -2,6 +2,7 @@
@@ -455,13 +457,13 @@ index 172ad36..c0b3cd5 100644
 +	max_port_count = read32(sata_bar5 + 0x00) & 0x1f;
 +	max_port_count++;
 +	printk(BIOS_SPEW, "Maximum SATA port count supported by silicon: %d\n", max_port_count);
-+
+ 
 +	/* Set number of ports */
 +	dword = CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD;
 +	for (i = max_port_count; i < 32; i++)
 +		dword &= ~(0x1 << i);
 +	write32(sata_bar5 + 0x0c, dword);
- 
++
 +	/* Write protect Sub-Class Code */
  	byte = pci_read_config8(dev, 0x40);
  	byte &= ~(1 << 0);
@@ -496,25 +498,6 @@ index 172ad36..c0b3cd5 100644
 -			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
 -			/* Try to do something about it. */
 -			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
--
--			/* Read in Port-N Serial ATA Control Register */
--			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
--
--			/* Set Reset Bit and 1.5g bit */
--			byte |= 0x11;
--			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
--
--			/* Wait 1ms */
--			mdelay(1);
--
--			/* Clear Reset Bit */
--			byte &= ~0x01;
--			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
--
--			/* Wait 1ms */
--			mdelay(1);
--
--			/* Reread status */
 +	/* Determine port count */
 +	port_count = 0;
 +	for (i = 0; i < 32; i++) {
@@ -534,43 +517,58 @@ index 172ad36..c0b3cd5 100644
 +		/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */
 +		/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
 +		for (i = 0; i < port_count; i++) {
- 			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
- 			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
- 			byte &= 0xF;
--		}
--
--		if (byte == 0x3) {
--			for (j = 0; j < 10; j++) {
--				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
--					break;
++			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
++			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
++			byte &= 0xF;
 +			if (byte == 0x1) {
 +				/* If the drive status is 0x1 then we see it but we aren't talking to it. */
 +				/* Try to do something about it. */
 +				printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
-+	
+ 
+-			/* Read in Port-N Serial ATA Control Register */
+-			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
 +				/* Read in Port-N Serial ATA Control Register */
 +				byte = read8(sata_bar5 + 0x12C + 0x80 * i);
-+	
+ 
+-			/* Set Reset Bit and 1.5g bit */
+-			byte |= 0x11;
+-			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
 +				/* Set Reset Bit and 1.5g bit */
 +				byte |= 0x11;
 +				write8((sata_bar5 + 0x12C + 0x80 * i), byte);
-+	
+ 
+-			/* Wait 1ms */
+-			mdelay(1);
 +				/* Wait 1ms */
 +				mdelay(1);
-+	
+ 
+-			/* Clear Reset Bit */
+-			byte &= ~0x01;
+-			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
 +				/* Clear Reset Bit */
 +				byte &= ~0x01;
 +				write8((sata_bar5 + 0x12C + 0x80 * i), byte);
-+	
+ 
+-			/* Wait 1ms */
+-			mdelay(1);
 +				/* Wait 1ms */
 +				mdelay(1);
-+	
+ 
+-			/* Reread status */
+-			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+-			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+-			byte &= 0xF;
+-		}
 +				/* Reread status */
 +				byte = read8(sata_bar5 + 0x128 + 0x80 * i);
 +				printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 +				byte &= 0xF;
 +			}
-+	
+ 
+-		if (byte == 0x3) {
+-			for (j = 0; j < 10; j++) {
+-				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
+-					break;
 +			if (byte == 0x3) {
 +				for (j = 0; j < 10; j++) {
 +					if (i < 4)
@@ -654,5 +652,5 @@ index 5250e20..95e3354 100644
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License as published by
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0051-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch b/resources/libreboot/patch/kgpe-d16/0049-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch
index 6113a16..28bdf5f 100644
--- a/resources/libreboot/patch/kgpe-d16/0051-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch
+++ b/resources/libreboot/patch/kgpe-d16/0049-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch
@@ -1,11 +1,13 @@
-From c76661067c11f2ba9a7b58a7cb87215cea2a3f61 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 8402270ff9ebd9f118f28daa2eda5d3852843a32 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 9 Jun 2015 18:57:23 -0500
-Subject: [PATCH 051/146] mainboard/asus/kgpe-d16: Properly initialize SB700
+Subject: [PATCH 049/139] mainboard/asus/kgpe-d16: Properly initialize SB700
  SATA PHYs
 
+Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/mainboard.c |   23 +++++++++++++++++++++++
+ src/mainboard/asus/kgpe-d16/mainboard.c | 23 +++++++++++++++++++++++
  1 file changed, 23 insertions(+)
 
 diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c
@@ -43,5 +45,5 @@ index 47ede34..8de6f26 100644
  	.enable_dev = mainboard_enable,
  };
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0052-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch b/resources/libreboot/patch/kgpe-d16/0050-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch
index 01ff80a..8bc23ec 100644
--- a/resources/libreboot/patch/kgpe-d16/0052-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch
+++ b/resources/libreboot/patch/kgpe-d16/0050-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch
@@ -1,15 +1,17 @@
-From 173148993ede860eb9e00d5d6efee322f6b03424 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 77b9c8b935e51ba8eb779fcf050f8ac407d0c4f3 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 9 Jun 2015 19:12:35 -0500
-Subject: [PATCH 052/146] southbridge/amd/sb700: Disable broken SATA MSI
+Subject: [PATCH 050/139] southbridge/amd/sb700: Disable broken SATA MSI
  functionality
 
+Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/early_setup.c |    7 ++++---
+ src/southbridge/amd/sb700/early_setup.c | 7 ++++---
  1 file changed, 4 insertions(+), 3 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
-index 70a2aee..1f92a4e 100644
+index a06a72f..da03961 100644
 --- a/src/southbridge/amd/sb700/early_setup.c
 +++ b/src/southbridge/amd/sb700/early_setup.c
 @@ -678,6 +678,7 @@ static void sb700_pci_cfg(void)
@@ -35,5 +37,5 @@ index 70a2aee..1f92a4e 100644
  	pci_write_config8(dev, 0x40, byte);
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0053-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch b/resources/libreboot/patch/kgpe-d16/0051-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch
index bb770ae..e2dda8b 100644
--- a/resources/libreboot/patch/kgpe-d16/0053-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch
+++ b/resources/libreboot/patch/kgpe-d16/0051-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch
@@ -1,13 +1,14 @@
-From 657c3cc04be3d40e735acc460968950a3400f302 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 2480454b78d3ad98e1107f07bcd8175b80b69219 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 9 Jun 2015 19:34:16 -0500
-Subject: [PATCH 053/146] southbridge/amd/sb700: Indicate iSATA/eSATA port
- type
+Subject: [PATCH 051/139] southbridge/amd/sb700: Indicate iSATA/eSATA port type
 
+Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/mainboard.c |   16 ++++++++++++++++
- src/southbridge/amd/sb700/sata.c        |   19 +++++++++++++++++++
- src/southbridge/amd/sb700/sb700.h       |    1 +
+ src/mainboard/asus/kgpe-d16/mainboard.c | 16 ++++++++++++++++
+ src/southbridge/amd/sb700/sata.c        | 19 +++++++++++++++++++
+ src/southbridge/amd/sb700/sb700.h       |  1 +
  3 files changed, 36 insertions(+)
 
 diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c
@@ -38,7 +39,7 @@ index 8de6f26..77e55db 100644
  	.enable_dev = mainboard_enable,
  };
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index c0b3cd5..dda2fc3 100644
+index d97288a..d35f84d 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -78,6 +78,23 @@ void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev)
@@ -88,5 +89,5 @@ index 941a4fd..8f792e7 100644
  #endif
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0054-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch b/resources/libreboot/patch/kgpe-d16/0052-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch
index 09aa956..909f3df 100644
--- a/resources/libreboot/patch/kgpe-d16/0054-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0052-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch
@@ -1,14 +1,16 @@
-From 9e4833cba06cfb3b771f2d6472996534abb082fd Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From f12fffe558a4ffd6ea77eadac08a2292ce2d8c96 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Wed, 10 Jun 2015 00:35:05 -0500
-Subject: [PATCH 054/146] northbridge/amd/amdfam10: Add ability to set maximum
+Subject: [PATCH 052/139] northbridge/amd/amdfam10: Add ability to set maximum
  P-state limit
 
+Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.default    |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout     |    3 ++-
- src/northbridge/amd/amdfam10/misc_control.c |   25 +++++++++++++++++++++----
- 3 files changed, 24 insertions(+), 5 deletions(-)
+ src/mainboard/asus/kgpe-d16/cmos.default    |  1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout     |  3 ++-
+ src/northbridge/amd/amdfam10/misc_control.c | 24 ++++++++++++++++++++----
+ 3 files changed, 23 insertions(+), 5 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
 index 5bfaadd..a52b7fa 100644
@@ -37,18 +39,10 @@ index 247fd7b..307bddc 100644
  728        256       h       0        user_data
  984         16       h       0        check_sum
 diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
-index 8777e8f..1057ac1 100644
+index 8777e8f..703ae51 100644
 --- a/src/northbridge/amd/amdfam10/misc_control.c
 +++ b/src/northbridge/amd/amdfam10/misc_control.c
-@@ -32,6 +32,7 @@
- #include <device/pci_ids.h>
- #include <device/pci_ops.h>
- #include <pc80/mc146818rtc.h>
-+#include <option.h>
- #include <lib.h>
- #include <cpu/amd/model_10xxx_rev.h>
- 
-@@ -124,16 +125,32 @@ static void mcf3_set_resources(device_t dev)
+@@ -124,16 +124,32 @@ static void mcf3_set_resources(device_t dev)
  
  static void misc_control_init(struct device *dev)
  {
@@ -86,5 +80,5 @@ index 8777e8f..1057ac1 100644
  	printk(BIOS_DEBUG, "done.\n");
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0055-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch b/resources/libreboot/patch/kgpe-d16/0053-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch
index 5de1482..2d97530 100644
--- a/resources/libreboot/patch/kgpe-d16/0055-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch
+++ b/resources/libreboot/patch/kgpe-d16/0053-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch
@@ -1,35 +1,41 @@
-From 1786c1ae0d378df7f2a0f99e13d32df619e0f010 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5ae82615bbd3e9a7a5f6d7b5c7c203b0a780c554 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Wed, 10 Jun 2015 10:46:17 -0500
-Subject: [PATCH 055/146] northbridge/amd/amdmct: Verify MCT NVRAM options
+Subject: [PATCH 053/139] northbridge/amd/amdmct: Verify MCT NVRAM options
  before skipping training
 
+Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   |    5 +++-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |    2 ++
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |   36 ++++++++++++++++++++++++-
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h |    3 ++-
- 4 files changed, 43 insertions(+), 3 deletions(-)
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   |  9 ++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |  2 ++
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.h |  3 ++-
+ 4 files changed, 47 insertions(+), 3 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 6d8c23e..e493158 100644
+index 3edce9e..4d7e5aa 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -4119,7 +4119,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
+@@ -4126,7 +4126,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
  	calculate_and_store_spd_hashes(pMCTstat, pDCTstat);
  
- #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 -	if (load_spd_hashes_from_nvram(pDCTstat) < 0) {
 +	if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) {
  		pDCTstat->spd_data.nvram_spd_match = 0;
  	}
  	else {
-@@ -4134,6 +4134,9 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
+@@ -4141,6 +4141,13 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
  	if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS)
  		allow_config_restore = !!nvram;
  
++#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 +	if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash())
 +		allow_config_restore = 0;
++#else
++	allow_config_restore = 0;
++#endif
 +
  	if (!allow_config_restore)
  		pDCTstat->spd_data.nvram_spd_match = 0;
@@ -55,7 +61,7 @@ index adf89b2..11555ae 100644
  
  /*===============================================================================
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index 4c0e58d..2132648 100644
+index 1e5c1a0..fe89af1 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 @@ -143,6 +143,36 @@ void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash)
@@ -139,5 +145,5 @@ index 82f73a7..74922c4 100644
  
  #ifdef __RAMSTAGE__
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0056-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch b/resources/libreboot/patch/kgpe-d16/0054-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch
index be38014..4bbc1c7 100644
--- a/resources/libreboot/patch/kgpe-d16/0056-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch
+++ b/resources/libreboot/patch/kgpe-d16/0054-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch
@@ -1,15 +1,17 @@
-From 7c25f47057008eede54dd92a7242052b6ec3b479 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From da111dc0736f1101683c5e596fdfed46fd48717d Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 11 Jun 2015 16:14:15 -0500
-Subject: [PATCH 056/146] src/northbridge/amd/amdmct: Add option to override
+Subject: [PATCH 054/139] src/northbridge/amd/amdmct: Add option to override
  bad SPD checksum
 
+Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.default     |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout      |    7 ++++++-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |    7 ++++---
- src/northbridge/amd/amdmct/wrappers/mcti_d.c |    8 ++++++++
- 4 files changed, 19 insertions(+), 4 deletions(-)
+ src/mainboard/asus/kgpe-d16/cmos.default     | 1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout      | 7 ++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  | 5 +++--
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 ++++++++
+ 4 files changed, 18 insertions(+), 3 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
 index a52b7fa..73f2a38 100644
@@ -50,10 +52,10 @@ index 307bddc..e91568c 100644
  checksums
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index e493158..28f8d18 100644
+index 4d7e5aa..f4859d0 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1443,10 +1443,10 @@ restartinit:
+@@ -1449,7 +1449,7 @@ restartinit:
  			}
  		}
  		if (NodesWmem == 0) {
@@ -61,12 +63,8 @@ index e493158..28f8d18 100644
 +			printk(BIOS_ALERT, "Unable to detect valid memory on any nodes.  Halting!\n");
  			goto fatalexit;
  		}
--	
-+
- 		printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n");
- 		SyncDCTsReady_D(pMCTstat, pDCTstatA);	/* Make sure DCTs are ready for accesses.*/
- 	
-@@ -3877,13 +3877,14 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+ 
+@@ -3884,13 +3884,14 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  					read_spd_bytes(pMCTstat, pDCTstat, i);
  					crc_status = crcCheck(pDCTstat, i);
  				}
@@ -83,7 +81,7 @@ index e493158..28f8d18 100644
  					if (SPDCtrl == 0) {
  						pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum;
 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
-index 2e53f0b..1a4e984 100644
+index af34d3b..86a0b14 100644
 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 @@ -150,6 +150,14 @@ static u16 mctGet_NVbits(u8 index)
@@ -102,5 +100,5 @@ index 2e53f0b..1a4e984 100644
  	case NV_DQSTrainCTL:
  		//val = 0;	/*Skip dqs training */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0057-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch b/resources/libreboot/patch/kgpe-d16/0055-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch
index 37bfa24..518947d 100644
--- a/resources/libreboot/patch/kgpe-d16/0057-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0055-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch
@@ -1,11 +1,13 @@
-From ade9e1905927f05cdd4cba50a9127be1ef954af5 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From ffdb5fd36669b7f722d46777f421d4ee37005f1c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 12 Jun 2015 13:32:52 -0500
-Subject: [PATCH 057/146] mainboard/asus/kgpe-d16: Add missing IRQ routing for
+Subject: [PATCH 055/139] mainboard/asus/kgpe-d16: Add missing IRQ routing for
  PIKE card
 
+Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/dsdt.asl |   74 +++++++++++++++++++++++++---------
+ src/mainboard/asus/kgpe-d16/dsdt.asl | 74 +++++++++++++++++++++++++++---------
  1 file changed, 55 insertions(+), 19 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl
@@ -203,5 +205,5 @@ index b6f10d9..bbe445f 100644
  				}
  				Device (SLT1)
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0058-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch b/resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch
index 3dfd6e1..6c11daf 100644
--- a/resources/libreboot/patch/kgpe-d16/0058-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch
+++ b/resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch
@@ -1,15 +1,17 @@
-From 89a7158d49583b376c9ba34d8b180d8a99f6aa84 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From b0454d907b46b7d117a8778e18aa01c4258aeb1a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 12 Jun 2015 19:43:06 -0500
-Subject: [PATCH 058/146] northbridge/amd/amdmct: Fix hang on boot due to
+Subject: [PATCH 056/139] northbridge/amd/amdmct: Fix hang on boot due to
  invalid array access
 
+Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/wrappers/mcti_d.c |    4 ++--
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
-index 1a4e984..d1da07b 100644
+index 86a0b14..0a31aad 100644
 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 @@ -344,7 +344,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
@@ -31,5 +33,5 @@ index 1a4e984..d1da07b 100644
  				highest_rank_count[i] = pDCTData->DimmRanks[dimm];
  		}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch b/resources/libreboot/patch/kgpe-d16/0057-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch
index 095f3e7..dc2ad90 100644
--- a/resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch
+++ b/resources/libreboot/patch/kgpe-d16/0057-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch
@@ -1,11 +1,13 @@
-From d70984fcd30907e57adb6017e0c36b295b354be3 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From c6ad4c2dc41378273147690741de931ca2f292f5 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 12 Jun 2015 19:43:38 -0500
-Subject: [PATCH 059/146] southbridge/amd/sr5650: Fix GPP3a link training in
+Subject: [PATCH 057/139] southbridge/amd/sr5650: Fix GPP3a link training in
  higher width modes
 
+Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sr5650/pcie.c |   51 ++++++++++++++++++++++++++++++++++---
+ src/southbridge/amd/sr5650/pcie.c | 51 ++++++++++++++++++++++++++++++++++++---
  1 file changed, 47 insertions(+), 4 deletions(-)
 
 diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
@@ -79,5 +81,5 @@ index d306b5a..79f2a5f 100644
  					AtiPcieCfg.PortDetect |= 1 << port;
  				} else {
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0060-southbridge-amd-sr5650-Add-optional-delay-after-link.patch b/resources/libreboot/patch/kgpe-d16/0058-southbridge-amd-sr5650-Add-optional-delay-after-link.patch
index 9929753..9466989 100644
--- a/resources/libreboot/patch/kgpe-d16/0060-southbridge-amd-sr5650-Add-optional-delay-after-link.patch
+++ b/resources/libreboot/patch/kgpe-d16/0058-southbridge-amd-sr5650-Add-optional-delay-after-link.patch
@@ -1,16 +1,19 @@
-From 542a978ac79f24d04a5afab2084f0f783f35ae58 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From fbb842e25841100adff123f3154c3149d241fd30 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 12 Jun 2015 20:08:29 -0500
-Subject: [PATCH 060/146] southbridge/amd/sr5650: Add optional delay after
- link training
+Subject: [PATCH 058/139] southbridge/amd/sr5650: Add optional delay after link
+ training
 
 Certain devices (such as the LSI SAS 2008 controller) do not
 respond to PCI probes immediately after link training.  If it
 is known that such a device is likely to be installed allow the
 mainboard to insert an appropriate delay.
+
+Change-Id: Ibcd9426628cacd6f88e6e3fcbc2b3eb7e3a92081
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sr5650/chip.h   |    4 ++++
- src/southbridge/amd/sr5650/sr5650.c |    3 +++
+ src/southbridge/amd/sr5650/chip.h   | 4 ++++
+ src/southbridge/amd/sr5650/sr5650.c | 3 +++
  2 files changed, 7 insertions(+)
 
 diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h
@@ -64,5 +67,5 @@ index 75383de..6db1eb1 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0061-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch b/resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch
index be41590..822d763 100644
--- a/resources/libreboot/patch/kgpe-d16/0061-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch
+++ b/resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch
@@ -1,15 +1,17 @@
-From 62cde1966c383de9e3a4d579d5201406ee2f82f3 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 64ad6ee510824d3804a38a538f1822e5313eb3a3 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 12 Jun 2015 20:10:58 -0500
-Subject: [PATCH 061/146] mainboard/asus/kgpe-d16: Properly configure SR5690
+Subject: [PATCH 059/139] mainboard/asus/kgpe-d16: Properly configure SR5690
  southbridge PIKE slot
 
+Change-Id: I2f1373905ffd6460ac3c7c21738e2e2a9aa2e463
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/devicetree.cb |    6 +++---
+ src/mainboard/asus/kgpe-d16/devicetree.cb | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
-index 9bff01e..05b975b 100644
+index 18e337e..ada268b 100644
 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb
 +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
 @@ -43,9 +43,9 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
@@ -26,5 +28,5 @@ index 9bff01e..05b975b 100644
  				chip southbridge/amd/sb700		# Secondary southbridge
  					device pci 11.0 on end			# SATA
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0062-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch b/resources/libreboot/patch/kgpe-d16/0060-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch
index 8bf3220..84cd46a 100644
--- a/resources/libreboot/patch/kgpe-d16/0062-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch
+++ b/resources/libreboot/patch/kgpe-d16/0060-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch
@@ -1,13 +1,15 @@
-From 449d225e67724a4f1e0de116f1b37af0a07565fe Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From c13f090d6aa84c3537521bdb89cfb8dd10e70006 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 18 Jun 2015 11:48:02 -0500
-Subject: [PATCH 062/146] southbridge/amd/sb700: Add option to disable SATA
+Subject: [PATCH 060/139] southbridge/amd/sb700: Add option to disable SATA
  ALPM
 
+Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.default |    1 +
- src/mainboard/asus/kgpe-d16/cmos.layout  |    8 ++++----
- src/southbridge/amd/sb700/sata.c         |   12 ++++++++++++
+ src/mainboard/asus/kgpe-d16/cmos.default |  1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout  |  8 ++++----
+ src/southbridge/amd/sb700/sata.c         | 12 ++++++++++++
  3 files changed, 17 insertions(+), 4 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -43,7 +45,7 @@ index e91568c..f705af2 100644
  984         16       h       0        check_sum
  # Reserve the extended AMD configuration registers
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index dda2fc3..10dbca2 100644
+index d35f84d..b09ae73 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -108,6 +108,7 @@ static void sata_init(struct device *dev)
@@ -80,5 +82,5 @@ index dda2fc3..10dbca2 100644
  	byte = pci_read_config8(dev, 0x40);
  	byte &= ~(1 << 0);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0063-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch b/resources/libreboot/patch/kgpe-d16/0061-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch
index 011376d..d5a3a46 100644
--- a/resources/libreboot/patch/kgpe-d16/0063-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch
+++ b/resources/libreboot/patch/kgpe-d16/0061-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch
@@ -1,17 +1,19 @@
-From e25111f4814bf9f7dfd08196673b3fe2aa42f2c4 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 226e682880c316f193d58fc00b31265563c7ac38 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 18 Jun 2015 12:37:08 -0500
-Subject: [PATCH 063/146] mainboard/asus/kgpe-d16: Set SP5100 subtype
+Subject: [PATCH 061/139] mainboard/asus/kgpe-d16: Set SP5100 subtype
 
+Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/Kconfig |    1 +
+ src/mainboard/asus/kgpe-d16/Kconfig | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
-index 9c359da..761fc93 100644
+index 75bf0ee..084a412 100644
 --- a/src/mainboard/asus/kgpe-d16/Kconfig
 +++ b/src/mainboard/asus/kgpe-d16/Kconfig
-@@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
  	select SOUTHBRIDGE_AMD_SR5650
  	select SOUTHBRIDGE_AMD_SB700
  	select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
@@ -20,5 +22,5 @@ index 9c359da..761fc93 100644
  	select PARALLEL_CPU_INIT
  	select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0064-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch b/resources/libreboot/patch/kgpe-d16/0062-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch
index 401ad06..34b14f0 100644
--- a/resources/libreboot/patch/kgpe-d16/0064-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch
+++ b/resources/libreboot/patch/kgpe-d16/0062-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch
@@ -1,15 +1,17 @@
-From 05a000dc3aaf0f156962d0247fa464f4bfb065e9 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 136ca22907a8f16c8cce4d05a208ded2f2f054ac Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 20 Jun 2015 14:40:56 -0500
-Subject: [PATCH 064/146] northbridge/amd/amdmct: Fix crash on startup due to
+Subject: [PATCH 062/139] northbridge/amd/amdmct: Fix crash on startup due to
  NULL pointer access
 
+Change-Id: I47089f2ad886a6fda4e0cd4472efd975bb8e06c5
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/wrappers/mcti_d.c |    5 ++---
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
-index d1da07b..2376b20 100644
+index 0a31aad..ce2329d 100644
 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 @@ -353,11 +353,10 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
@@ -27,5 +29,5 @@ index d1da07b..2376b20 100644
  	}
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0065-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch b/resources/libreboot/patch/kgpe-d16/0063-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch
index 5ab2321..da29a67 100644
--- a/resources/libreboot/patch/kgpe-d16/0065-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0063-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch
@@ -1,16 +1,18 @@
-From 7599efdbd3f19a7d57036a9f6b56da8253fab4ce Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 1900ff138ed07b4cbe30aa4f73cb59b9ec5b4720 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 20 Jun 2015 20:02:49 -0500
-Subject: [PATCH 065/146] northbridge/amd/amdmct: Clear memory before enabling
+Subject: [PATCH 063/139] northbridge/amd/amdmct: Clear memory before enabling
  ECC
 
+Change-Id: I992e7040520570893ba6a213138dd57bfa14733b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |   45 ++++++++----------------
- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c |   38 +++++++++++++++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 45 ++++++++------------------
+ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 38 +++++++++++++++++++++-
  2 files changed, 51 insertions(+), 32 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 28f8d18..e39ce17 100644
+index f4859d0..d8a09f0 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -51,8 +51,6 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
@@ -22,7 +24,7 @@ index 28f8d18..e39ce17 100644
  static u8 NodePresent_D(u8 Node);
  static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstatA);
-@@ -1494,10 +1492,11 @@ restartinit:
+@@ -1500,10 +1498,11 @@ restartinit:
  		InterleaveChannels_D(pMCTstat, pDCTstatA);
  
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n");
@@ -38,7 +40,7 @@ index 28f8d18..e39ce17 100644
  
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
  		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
-@@ -2087,9 +2086,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -2094,9 +2093,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  
  	/* FIXME - currently uses calculated value	TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */
  	mctHookAfterAnyTraining();
@@ -48,7 +50,7 @@ index 28f8d18..e39ce17 100644
  }
  
  static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
-@@ -2377,26 +2373,6 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
+@@ -2384,26 +2380,6 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
  	}
  }
  
@@ -75,7 +77,7 @@ index 28f8d18..e39ce17 100644
  static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat)
  {
-@@ -2417,9 +2393,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
+@@ -2424,9 +2400,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
  		} while (!(val & (1 << Dr_MemClrStatus)));
  	}
  
@@ -90,7 +92,7 @@ index 28f8d18..e39ce17 100644
  }
  
  static u8 NodePresent_D(u8 Node)
-@@ -3082,6 +3061,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
+@@ -3089,6 +3068,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
  	u16 proposedFreq;
  	u16 word;
  
@@ -99,7 +101,7 @@ index 28f8d18..e39ce17 100644
  	/* Get CPU Si Revision defined limit (NPT) */
  	if (is_fam15h())
  		proposedFreq = 933;
-@@ -3106,6 +3087,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
+@@ -3113,6 +3094,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
  		pDCTstat->PresetmaxFreq = word;
  	}
  	/* Check F3xE8[DdrMaxRate] for maximum DRAM data rate support */
@@ -109,7 +111,7 @@ index 28f8d18..e39ce17 100644
  
  static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
-index c930380..99cccb8 100644
+index 3a9fecc..918e91e 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 @@ -88,6 +88,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
@@ -179,5 +181,5 @@ index c930380..99cccb8 100644
  		pMCTstat->GStatus |= 1<<GSB_ECCDIMMs;
  	else
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0066-southbridge-amd-sb700-Do-drive-detection-even-in-AHC.patch b/resources/libreboot/patch/kgpe-d16/0064-southbridge-amd-sb700-Do-drive-detection-even-in-AHC.patch
index 3c6c1f3..17871d0 100644
--- a/resources/libreboot/patch/kgpe-d16/0066-southbridge-amd-sb700-Do-drive-detection-even-in-AHC.patch
+++ b/resources/libreboot/patch/kgpe-d16/0064-southbridge-amd-sb700-Do-drive-detection-even-in-AHC.patch
@@ -1,18 +1,21 @@
-From b199e0e69955a8313cee68c1d589cac5956982b9 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 8e2c343cbbca40d27e0f50b7d563c5c44020d1da Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 20 Jun 2015 21:31:15 -0500
-Subject: [PATCH 066/146] southbridge/amd/sb700: Do drive detection even in
+Subject: [PATCH 064/139] southbridge/amd/sb700: Do drive detection even in
  AHCI mode
 
 SeaBIOS AHCI drive detection randomly fails for drives present
 on the secondary channel of each AHCI SATA BAR.  Forcing native
 drive detection in AHCI mode resolves this issue.
+
+Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/sata.c |  101 ++++++++++++++++++++------------------
- 1 file changed, 54 insertions(+), 47 deletions(-)
+ src/southbridge/amd/sb700/sata.c | 99 +++++++++++++++++++++-------------------
+ 1 file changed, 53 insertions(+), 46 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index 10dbca2..6afdfdf 100644
+index b09ae73..24f78dd 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -301,65 +301,72 @@ static void sata_init(struct device *dev)
@@ -69,30 +72,29 @@ index 10dbca2..6afdfdf 100644
 -				/* If the drive status is 0x1 then we see it but we aren't talking to it. */
 -				/* Try to do something about it. */
 -				printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
--	
+-
 -				/* Read in Port-N Serial ATA Control Register */
 -				byte = read8(sata_bar5 + 0x12C + 0x80 * i);
--	
+-
 -				/* Set Reset Bit and 1.5g bit */
 -				byte |= 0x11;
 -				write8((sata_bar5 + 0x12C + 0x80 * i), byte);
--	
+-
 -				/* Wait 1ms */
 -				mdelay(1);
--	
+-
 -				/* Clear Reset Bit */
 -				byte &= ~0x01;
 -				write8((sata_bar5 + 0x12C + 0x80 * i), byte);
--	
+-
 -				/* Wait 1ms */
 -				mdelay(1);
--	
++		}
+ 
 -				/* Reread status */
 -				byte = read8(sata_bar5 + 0x128 + 0x80 * i);
 -				printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 -				byte &= 0xF;
-+		}
-+
 +		if (byte == 0x3) {
 +			for (j = 0; j < 10; j++) {
 +				if (i < 4)
@@ -102,7 +104,7 @@ index 10dbca2..6afdfdf 100644
 +				if (!sata_drive_detect(i, current_bar))
 +					break;
  			}
--	
+-
 -			if (byte == 0x3) {
 -				for (j = 0; j < 10; j++) {
 -					if (i < 4)
@@ -117,7 +119,7 @@ index 10dbca2..6afdfdf 100644
 +						i,
 +						(j == 10) ? "not " : "",
 +						(j == 10) ? j : j + 1);
-+			else 
++			else
  				printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
  						(i / 2) ? "Secondary" : "Primary",
  						(i % 2 ) ? "Slave" : "Master",
@@ -136,5 +138,5 @@ index 10dbca2..6afdfdf 100644
  	}
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0067-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch b/resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch
index 350e3d7..f63be47 100644
--- a/resources/libreboot/patch/kgpe-d16/0067-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch
+++ b/resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch
@@ -1,7 +1,7 @@
-From 6e707886c395da568608ac70760ce03b00c737c4 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 15a27b612b1da36173017dd671763ce455f319ad Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 21 Jun 2015 16:27:03 -0500
-Subject: [PATCH 067/146] src/southbridge/amd/sb700: Reset SATA controller in
+Subject: [PATCH 065/139] src/southbridge/amd/sb700: Reset SATA controller in
  AHCI mode during startup
 
 In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts),
@@ -9,12 +9,15 @@ with the probability of a failure increasing with the number of disks
 connected to the controller.  Resetting the SATA controller appears to
 show the true state of the underlying hardware, allowing the drive
 detection code to attempt link renegotiation as needed.
+
+Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/sata.c |   47 ++++++++++++++++++++++++++++----------
+ src/southbridge/amd/sb700/sata.c | 47 ++++++++++++++++++++++++++++++----------
  1 file changed, 35 insertions(+), 12 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index 6afdfdf..9f610a4 100644
+index 24f78dd..d51baa1 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -135,6 +135,8 @@ static void sata_init(struct device *dev)
@@ -44,7 +47,7 @@ index 6afdfdf..9f610a4 100644
 +		dword &= ~(0x1 << 27);
 +#endif
 +		write32(sata_bar5 + 0x00, dword);
-+	
++
 +		/* Reset the HBA to avoid stuck drives in SeaBIOS */
 +		dword = read32(sata_bar5 + 0x04);
 +		dword |= 0x1;
@@ -89,5 +92,5 @@ index 6afdfdf..9f610a4 100644
  	/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch b/resources/libreboot/patch/kgpe-d16/0066-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch
index dbc48be..68138ca 100644
--- a/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch
+++ b/resources/libreboot/patch/kgpe-d16/0066-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch
@@ -1,15 +1,17 @@
-From 2c28e8112799a9ec7b72478c0593664dbeab4757 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From c1413dd2277df0bd10fd2faf94302232889e95d8 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 22 Jun 2015 02:21:29 -0500
-Subject: [PATCH 068/146] southbridge/amd/sb700: Recover if AHCI disk
- detection fails
+Subject: [PATCH 066/139] southbridge/amd/sb700: Recover if AHCI disk detection
+ fails
 
+Change-Id: I29051af5eca5d31b6aecc261e9a48028380eccb3
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/sata.c |   83 ++++++++++++++++++++++++++++++++++----
+ src/southbridge/amd/sb700/sata.c | 83 ++++++++++++++++++++++++++++++++++++----
  1 file changed, 75 insertions(+), 8 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index 9f610a4..f27ec49 100644
+index d51baa1..ce242c1 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -31,12 +31,15 @@
@@ -104,18 +106,18 @@ index 9f610a4..f27ec49 100644
 +	for (i = 0; i < port_count; i++) {
 +		/* Read in Port-N Serial ATA Control Register */
 +		byte = read8(sata_bar5 + 0x12C + 0x80 * i);
-+	
++
 +		/* Set Reset Bit */
 +		byte |= 0x1;
 +		write8((sata_bar5 + 0x12C + 0x80 * i), byte);
-+	
++
 +		/* Wait 1ms */
 +		mdelay(1);
-+	
++
 +		/* Clear Reset Bit */
 +		byte &= ~0x01;
 +		write8((sata_bar5 + 0x12C + 0x80 * i), byte);
-+	
++
 +		/* Wait 1ms */
 +		mdelay(1);
 +	}
@@ -157,5 +159,5 @@ index 9f610a4..f27ec49 100644
  			if (sata_ahci_mode)
  				printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n",
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0069-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch b/resources/libreboot/patch/kgpe-d16/0067-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch
index b515a7a..6466354 100644
--- a/resources/libreboot/patch/kgpe-d16/0069-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch
+++ b/resources/libreboot/patch/kgpe-d16/0067-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch
@@ -1,15 +1,17 @@
-From 26a5ebad4ca95370319d630f323b5a982cc113c0 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 0785e1c4b21ee56c6265df7b6c7f95ad94a43fbb Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 22 Jun 2015 02:56:10 -0500
-Subject: [PATCH 069/146] southbridge/amd/sb700: Fix SATA port 4/5 drive
+Subject: [PATCH 067/139] southbridge/amd/sb700: Fix SATA port 4/5 drive
  detection
 
+Change-Id: I01481f25189d01b6f4ed778902b2ecc4d39c7912
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/sata.c |   42 ++++++++++++++++++++++++++++++++++----
+ src/southbridge/amd/sb700/sata.c | 42 ++++++++++++++++++++++++++++++++++++----
  1 file changed, 38 insertions(+), 4 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index f27ec49..da6f107 100644
+index ce242c1..dc64082 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -126,6 +126,8 @@ static void sata_init(struct device *dev)
@@ -91,5 +93,5 @@ index f27ec49..da6f107 100644
  		byte = read8(sata_bar5 + 0x4);
  		byte |= 1 << 1;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0070-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch b/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch
index 536823e..0d16a01 100644
--- a/resources/libreboot/patch/kgpe-d16/0070-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch
+++ b/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch
@@ -1,15 +1,17 @@
-From ca61ec33fb6c8f3eab823d6fa5415c6775b48192 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 6b5ae665f42bf04cb5dd54d719a18f5f1e670c63 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 22 Jun 2015 20:57:39 -0500
-Subject: [PATCH 070/146] southbridge/amd/sb700: Fix random persistent SATA
+Subject: [PATCH 068/139] southbridge/amd/sb700: Fix random persistent SATA
  AHCI drive detection failure
 
+Change-Id: I4202a62217a7aaeaba07e4b994a350e83e064c9c
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/sata.c |   81 ++++++++++++++++++++------------------
+ src/southbridge/amd/sb700/sata.c | 81 +++++++++++++++++++++-------------------
  1 file changed, 42 insertions(+), 39 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
-index da6f107..c3efd4a 100644
+index dc64082..9d354bb 100644
 --- a/src/southbridge/amd/sb700/sata.c
 +++ b/src/southbridge/amd/sb700/sata.c
 @@ -125,7 +125,6 @@ static void sata_init(struct device *dev)
@@ -159,5 +161,5 @@ index da6f107..c3efd4a 100644
  			}
  			if (sata_ahci_mode)
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0071-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch b/resources/libreboot/patch/kgpe-d16/0069-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch
index f37c380..4b7392b 100644
--- a/resources/libreboot/patch/kgpe-d16/0071-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch
+++ b/resources/libreboot/patch/kgpe-d16/0069-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch
@@ -1,39 +1,23 @@
-From 4818de5c4895e3de9bca7d7f3566492e8e529e21 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From c942d174cfc1a0ba6e91e0131c0a105addddbbd4 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Wed, 24 Jun 2015 19:15:09 -0500
-Subject: [PATCH 071/146] northbridge/amd/amdmct/mct_ddr3: Fix lockups and
+Subject: [PATCH 069/139] northbridge/amd/amdmct/mct_ddr3: Fix lockups and
  wasted time during ECC init
 
+Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |  146 +++++++++++++++---------
- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c |   39 ++++++-
- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c  |   22 +++-
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |    3 +-
- 4 files changed, 147 insertions(+), 63 deletions(-)
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 142 +++++++++++++++----------
+ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c |  39 ++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctproc.c  |  22 +++-
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |   3 +-
+ 4 files changed, 145 insertions(+), 61 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index e39ce17..b66b328 100644
+index d8a09f0..68957f5 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -983,7 +983,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
- 				/* 2 DIMMs detected */
- 				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
- 				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
--				
-+
- 				if (MemClkFreq == 0x4) {
- 					/* DDR3-667 */
- 					calibration_code = 0x00390039;
-@@ -1072,7 +1072,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
- 				/* 2 DIMMs detected */
- 				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
- 				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
--				
-+
- 				if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
- 					|| (MemClkFreq == 0xa)) {
- 					/* DDR3-667 - DDR3-1066 */
-@@ -1492,11 +1492,12 @@ restartinit:
+@@ -1498,11 +1498,12 @@ restartinit:
  		InterleaveChannels_D(pMCTstat, pDCTstatA);
  
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n");
@@ -51,7 +35,7 @@ index e39ce17..b66b328 100644
  
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
  		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
-@@ -1689,7 +1690,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -1695,7 +1696,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		uint8_t x8_present = 0;
  		uint8_t memclk_index;
  		uint8_t interleave_channels = 0;
@@ -59,7 +43,7 @@ index e39ce17..b66b328 100644
  		uint16_t trdrdsddc;
  		uint16_t trdrddd;
  		uint16_t cdd_trdrddd;
-@@ -1727,9 +1727,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -1733,9 +1733,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		if (pDCTstat->DIMMValidDCT[0] && pDCTstat->DIMMValidDCT[1] && mctGet_NVbits(NV_Unganged))
  			interleave_channels = 1;
  
@@ -69,7 +53,7 @@ index e39ce17..b66b328 100644
  		dword = (Get_NB32_DCT(dev, dct, 0x240) >> 4) & 0xf;
  		if (dword > 6)
  			read_odt_delay = dword - 6;
-@@ -1922,21 +1919,10 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -1927,21 +1924,10 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		dword |= (interleave_channels & 0x1) << 2;
  		Set_NB32_DCT(dev, dct, 0x110, dword);			/* DRAM Controller Select Low */
  
@@ -95,7 +79,7 @@ index e39ce17..b66b328 100644
  
  		/* FIXME
  		 * The BKDG-recommended settings cause memory corruption on the ASUS KGPE-D16.
-@@ -1978,11 +1964,17 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -1983,11 +1969,17 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		dword |= ((((dword >> 8) & 0x1f) + 1) << 16);
  		Set_NB32_DCT(dev, dct, 0x21c, dword);			/* DRAM Timing 6 */
  
@@ -115,7 +99,7 @@ index e39ce17..b66b328 100644
  	}
  }
  
-@@ -2084,6 +2076,19 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -2091,6 +2083,19 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  		pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
  	}
  
@@ -135,7 +119,7 @@ index e39ce17..b66b328 100644
  	/* FIXME - currently uses calculated value	TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */
  	mctHookAfterAnyTraining();
  }
-@@ -2330,6 +2335,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
+@@ -2337,6 +2342,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
  	 * status are checked to ensure that memclr has completed.
  	 */
  	u8 Node;
@@ -143,7 +127,7 @@ index e39ce17..b66b328 100644
  	struct DCTStatStruc *pDCTstat;
  
  	if (!mctGet_NVbits(NV_DQSTrainCTL)){
-@@ -2350,6 +2356,16 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
+@@ -2357,6 +2363,16 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
  			}
  		}
  	}
@@ -160,7 +144,7 @@ index e39ce17..b66b328 100644
  }
  
  static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
-@@ -2357,48 +2373,59 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
+@@ -2364,48 +2380,59 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
  {
  	u32 val;
  	u32 dev;
@@ -209,10 +193,10 @@ index e39ce17..b66b328 100644
 -			val = Get_NB32(dev, reg);
 -		} while (val & (1 << MemClrBusy));
 +			dword = Get_NB32(dev, 0x110);
-+			
+ 
 +			printk(BIOS_DEBUG, ".");
 +		} while (dword & (1 << MemClrBusy));
- 
++
 +		printk(BIOS_DEBUG, "\n");
  		do {
 -			val = Get_NB32(dev, reg);
@@ -239,7 +223,7 @@ index e39ce17..b66b328 100644
  }
  
  static u8 NodePresent_D(u8 Node)
-@@ -3339,8 +3366,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3346,8 +3373,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	dev = pDCTstat->dev_dct;
  
  	/* Build Dram Control Register Value */
@@ -250,7 +234,7 @@ index e39ce17..b66b328 100644
  
  	/* FIXME: Skip mct_checkForDxSupport */
  	/* REV_CALL mct_DoRdPtrInit if not Dx */
-@@ -3395,9 +3422,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3402,9 +3429,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  			/* set only if x8 Registered DIMMs in System*/
  			DramConfigHi |= 1 << RDqsEn;
  
@@ -269,8 +253,8 @@ index e39ce17..b66b328 100644
  
  	/* Control Bank Swizzle */
  	if (0) /* call back not needed mctBankSwizzleControl_D()) */
-@@ -4105,8 +4138,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
- #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+@@ -4112,8 +4145,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat,
+ 
  	if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) {
  		pDCTstat->spd_data.nvram_spd_match = 0;
 -	}
@@ -279,7 +263,7 @@ index e39ce17..b66b328 100644
  		compare_nvram_spd_hashes(pMCTstat, pDCTstat);
  	}
  #else
-@@ -4300,8 +4332,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
+@@ -4311,8 +4343,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
  	}
  	for (i=i_start; i<i_end; i++) {
  		index_reg = 0x98;
@@ -290,7 +274,7 @@ index e39ce17..b66b328 100644
  	}
  
  	return pDCTstat->ErrCode;
-@@ -6091,11 +6123,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
+@@ -6102,11 +6134,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
  		DramMRS |= 1 << 1;
  
  	dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84);
@@ -304,7 +288,7 @@ index e39ce17..b66b328 100644
  }
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
-index 99cccb8..e352886 100644
+index 918e91e..a0482e8 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 @@ -92,8 +92,13 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
@@ -405,7 +389,7 @@ index 5ef4a2c..32b447f 100644
  			misc2 |= 1 << SubMemclkRegDly;
  			if (mctGet_NVbits(NV_MAX_DIMMS) == 8)
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index cbb34dc..3995a70 100644
+index 7ea7901..c760bac 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 @@ -209,7 +209,8 @@ void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta
@@ -419,5 +403,5 @@ index cbb34dc..3995a70 100644
  				pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane];
  			}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0072-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch b/resources/libreboot/patch/kgpe-d16/0070-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch
index f8392d9..0b55b83 100644
--- a/resources/libreboot/patch/kgpe-d16/0072-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch
+++ b/resources/libreboot/patch/kgpe-d16/0070-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch
@@ -1,22 +1,24 @@
-From 1171e5a4e83f2aedeb59b78ffa29cac927ff3441 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 589c0f7e4f80b82bdf8e604f0a7ded82cc9c09fe Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 25 Jun 2015 15:07:34 -0500
-Subject: [PATCH 072/146] cpu/amd: Fix AMD Family 15h ECC initialization
+Subject: [PATCH 070/139] cpu/amd: Fix AMD Family 15h ECC initialization
  reliability issues
 
+Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/car/cache_as_ram.inc               |    4 +
- src/cpu/amd/model_10xxx/init_cpus.c            |   16 ++++
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |   16 ++--
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |    6 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   21 ++++-
- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c |  110 +++++++++++-------------
- src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c |    6 +-
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c  |   57 +++++++-----
- 8 files changed, 138 insertions(+), 98 deletions(-)
+ src/cpu/amd/car/cache_as_ram.inc               |   4 +
+ src/cpu/amd/family_10h-family_15h/init_cpus.c  |  16 ++++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |  12 +--
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |   6 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |  21 ++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 110 +++++++++++--------------
+ src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c |   6 +-
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c  |  57 ++++++++-----
+ 8 files changed, 136 insertions(+), 96 deletions(-)
 
 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
-index 9c71270..9a51e3c 100644
+index 9edc41f..5db9224 100644
 --- a/src/cpu/amd/car/cache_as_ram.inc
 +++ b/src/cpu/amd/car/cache_as_ram.inc
 @@ -362,12 +362,16 @@ clear_fixed_var_mtrr_out:
@@ -36,10 +38,10 @@ index 9c71270..9a51e3c 100644
  #if CONFIG_XIP_ROM_SIZE
  
  	/* Enable write base caching so we can do execute in place (XIP)
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 57b9b89..0d1f043 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 818431b..0044dc6 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -317,6 +317,22 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid)
  		msr = rdmsr(BU_CFG2);
  		msr.lo &= ~(1 << ClLinesToNbDis);
@@ -64,27 +66,20 @@ index 57b9b89..0d1f043 100644
  
  	disable_cache_as_ram(skip_sharedc_config);	// inline
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index b66b328..5a0c746 100644
+index 68957f5..fadb353 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1447,13 +1447,12 @@ restartinit:
- 
- 		printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n");
- 		SyncDCTsReady_D(pMCTstat, pDCTstatA);	/* Make sure DCTs are ready for accesses.*/
--	
-+
- 		printk(BIOS_DEBUG, "mctAutoInitMCT_D: HTMemMapInit_D\n");
+@@ -1458,8 +1458,7 @@ restartinit:
  		HTMemMapInit_D(pMCTstat, pDCTstatA);	/* Map local memory into system address space.*/
  		mctHookAfterHTMap();
--	
+ 
 -		printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
 -		CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */
-+
 +		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n");
  		mctHookAfterCPU();			/* Setup external northbridge(s) */
  
  		/* FIXME
-@@ -1476,9 +1475,6 @@ restartinit:
+@@ -1482,9 +1481,6 @@ restartinit:
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
  		DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore);	/* Get Receiver Enable and DQS signal timing*/
  
@@ -94,7 +89,7 @@ index b66b328..5a0c746 100644
  		if (!allow_config_restore) {
  			printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
  			mct_OtherTiming(pMCTstat, pDCTstatA);
-@@ -1499,6 +1495,12 @@ restartinit:
+@@ -1505,6 +1501,12 @@ restartinit:
  			MCTMemClr_D(pMCTstat,pDCTstatA);
  		}
  
@@ -133,7 +128,7 @@ index 11555ae..ac8c934 100644
  
  struct amd_s3_persistent_node_data {
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index e74545b..207a135 100644
+index 740edae..b0ad54b 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -902,6 +902,16 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat,
@@ -180,7 +175,7 @@ index e74545b..207a135 100644
  
  static void start_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
-index e352886..37db37c 100644
+index a0482e8..d25ed53 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
 @@ -92,13 +92,8 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
@@ -381,7 +376,7 @@ index 596fb23..abc8ae3 100644
  		lo = 0;
  		hi = lo;
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index 2132648..2edb7ce 100644
+index fe89af1..b4a084c 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
 @@ -89,6 +89,28 @@ static uint32_t read_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint3
@@ -475,5 +470,5 @@ index 2132648..2edb7ce 100644
  			if (is_fam15h())
  				/* Set LockDramCfg and CC6SaveEn */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0071-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch b/resources/libreboot/patch/kgpe-d16/0071-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch
new file mode 100644
index 0000000..460ea7d
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0071-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch
@@ -0,0 +1,120 @@
+From ad1418509321ae8765b2e4692f10e5becc28073e Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Thu, 25 Jun 2015 15:28:23 -0500
+Subject: [PATCH 071/139] northbridge/amd/amdfam10: Properly indicate node and
+ channel in SMBIOS tables
+
+Change-Id: Ie7278745358daf0c78cdb9c579db5291a1a2a0cb
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdfam10/northbridge.c  |  7 ++++++-
+ src/northbridge/amd/amdmct/mct/mct_d.c      | 12 ++++++++++++
+ src/northbridge/amd/amdmct/mct/mct_d.h      |  7 +++++--
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 ++++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |  8 +++++---
+ 5 files changed, 40 insertions(+), 6 deletions(-)
+
+diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
+index 3fc31c0..95e902d 100644
+--- a/src/northbridge/amd/amdfam10/northbridge.c
++++ b/src/northbridge/amd/amdfam10/northbridge.c
+@@ -1207,7 +1207,12 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
+ 				t->attributes = 0;
+ 				t->attributes |= ranks & 0xf;	/* rank number is stored in the lowest 4 bits of the attributes field */
+ 				t->form_factor = MEMORY_FORMFACTOR_DIMM;
+-				snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1);
++				if (mem_info->dct_stat[node].Dual_Node_Package) {
++					snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node >> 1,
++						(mem_info->dct_stat[node].Internal_Node_ID)?((slot & 0x1)?"D":"C"):((slot & 0x1)?"B":"A"), (slot >> 1) + 1);
++				} else {
++					snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1);
++				}
+ 				t->device_locator = smbios_add_string(t->eos, string_buffer);
+ 				if (IS_ENABLED(CONFIG_DIMM_DDR2))
+ 					t->memory_type = MEMORY_TYPE_DDR2;
+diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
+index be0af65..c805d41 100644
+--- a/src/northbridge/amd/amdmct/mct/mct_d.c
++++ b/src/northbridge/amd/amdmct/mct/mct_d.c
+@@ -236,6 +236,18 @@ restartinit:
+ 		pDCTstat->dev_nbmisc = PA_NBMISC(Node);
+ 		pDCTstat->NodeSysBase = node_sys_base;
+ 
++		if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) {
++			uint32_t dword;
++			pDCTstat->Dual_Node_Package = 1;
++
++			/* Get the internal node number */
++			dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8);
++			dword = (dword >> 30) & 0x3;
++			pDCTstat->Internal_Node_ID = dword;
++		} else {
++			pDCTstat->Dual_Node_Package = 0;
++		}
++
+ 		print_tx("mctAutoInitMCT_D: mct_init Node ", Node);
+ 		mct_init(pMCTstat, pDCTstat);
+ 		mctNodeIDDebugPort_D();
+diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
+index 6b6194d..7569300 100644
+--- a/src/northbridge/amd/amdmct/mct/mct_d.h
++++ b/src/northbridge/amd/amdmct/mct/mct_d.h
+@@ -291,8 +291,11 @@ struct MCTStatStruc {
+ 
+ struct DCTStatStruc {		/* A per Node structure*/
+ /* DCTStatStruct_F -  start */
+-	u8 Node_ID;		/* Node ID of current controller*/
+-	u8 ErrCode;		/* Current error condition of Node
++	u8 Node_ID;			/* Node ID of current controller*/
++	uint8_t Internal_Node_ID;	/* Internal Node ID of the current controller */
++	uint8_t Dual_Node_Package;	/* 1=Dual node package (G34) */
++	uint8_t stopDCT;		/* Set if the DCT will be stopped */
++	u8 ErrCode;			/* Current error condition of Node
+ 		0= no error
+ 		1= Variance Error, DCT is running but not in an optimal configuration.
+ 		2= Stop Error, DCT is NOT running
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+index fadb353..573c0af 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+@@ -1389,6 +1389,18 @@ restartinit:
+ 			pDCTstat->dev_nbctl = PA_NBCTL(Node);
+ 			pDCTstat->NodeSysBase = node_sys_base;
+ 
++			if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) {
++				uint32_t dword;
++				pDCTstat->Dual_Node_Package = 1;
++
++				/* Get the internal node number */
++				dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8);
++				dword = (dword >> 30) & 0x3;
++				pDCTstat->Internal_Node_ID = dword;
++			} else {
++				pDCTstat->Dual_Node_Package = 0;
++			}
++
+ 			printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_init Node %d\n", Node);
+ 			mct_init(pMCTstat, pDCTstat);
+ 			mctNodeIDDebugPort_D();
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+index ac8c934..8c9da47 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+@@ -335,9 +335,11 @@ struct amd_spd_node_data {
+ 
+ struct DCTStatStruc {		/* A per Node structure*/
+ /* DCTStatStruct_F -  start */
+-	u8 Node_ID;		/* Node ID of current controller */
+-	uint8_t stopDCT;	/* Set if the DCT will be stopped */
+-	u8 ErrCode;		/* Current error condition of Node
++	u8 Node_ID;			/* Node ID of current controller */
++	uint8_t Internal_Node_ID;	/* Internal Node ID of the current controller */
++	uint8_t Dual_Node_Package;	/* 1=Dual node package (G34) */
++	uint8_t stopDCT;		/* Set if the DCT will be stopped */
++	u8 ErrCode;			/* Current error condition of Node
+ 		0= no error
+ 		1= Variance Error, DCT is running but not in an optimal configuration.
+ 		2= Stop Error, DCT is NOT running
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0074-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch b/resources/libreboot/patch/kgpe-d16/0072-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch
index 405cee3..682326b 100644
--- a/resources/libreboot/patch/kgpe-d16/0074-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0072-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch
@@ -1,15 +1,17 @@
-From 3d935128d5120ab48978aabfa2e99fe7d11992e1 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From e2624058dba93cd3820dffbf7964cd84b3ddd973 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 25 Jun 2015 17:07:57 -0500
-Subject: [PATCH 074/146] amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and
+Subject: [PATCH 072/139] amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and
  ODT values
 
+Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |  432 ++++++++++++++++++---------
- 1 file changed, 295 insertions(+), 137 deletions(-)
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 422 +++++++++++++++++++---------
+ 1 file changed, 290 insertions(+), 132 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 4a47ee8..c35e972 100644
+index 573c0af..643fa39 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -822,28 +822,12 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
@@ -65,8 +67,7 @@ index 4a47ee8..c35e972 100644
 +			} else if (MaxDimmsInstallable == 2) {
  				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
  				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
--				
-+
+ 
 +				if (dimm_count == 1) {
 +					/* 1 DIMM detected */
 +					if (MemClkFreq == 0x4) {
@@ -91,7 +92,7 @@ index 4a47ee8..c35e972 100644
 +					/* 2 DIMMs detected */
 +					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 +					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+					
++
 +					if (MemClkFreq == 0x4) {
 +						/* DDR3-667 */
 +						calibration_code = 0x10222222;
@@ -150,7 +151,7 @@ index 4a47ee8..c35e972 100644
 +				} else if (MemClkFreq == 0x16) {
 +					/* DDR3-1866 */
 +					calibration_code = 0x30332222;
-+				}
+ 				}
 +			} else if (MaxDimmsInstallable == 2) {
 +				if (dimm_count == 1) {
 +					/* 1 DIMM detected */
@@ -171,7 +172,7 @@ index 4a47ee8..c35e972 100644
 +					/* 2 DIMMs detected */
 +					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 +					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+					
++
 +					if (MemClkFreq == 0x4) {
 +						/* DDR3-667 */
 +						calibration_code = 0x10222222;
@@ -191,7 +192,7 @@ index 4a47ee8..c35e972 100644
 +						else
 +							calibration_code = 0x30112222;
 +					}
- 				}
++				}
 +			} else if (MaxDimmsInstallable == 3) {
 +				/* TODO
 +				 * 3 DIMM/channel support unimplemented
@@ -204,7 +205,7 @@ index 4a47ee8..c35e972 100644
  		}
  	} else {
  		/* TODO
-@@ -917,43 +1002,71 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
+@@ -917,41 +1002,69 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
  
  	if (package_type == PT_GR) {
  		/* Socket G34 */
@@ -305,11 +306,8 @@ index 4a47ee8..c35e972 100644
 +			/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
 +			if (MaxDimmsInstallable == 1) {
  				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
--
-+	
+ 
  				if (MemClkFreq == 0x4) {
- 					/* DDR3-667 */
- 					if (rank_count_dimm0 == 1)
 @@ -978,34 +1091,68 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
  						calibration_code = 0x00353533;
  					else
@@ -322,28 +320,11 @@ index 4a47ee8..c35e972 100644
 -				/* 2 DIMMs detected */
 -				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 -				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
--
--				if (MemClkFreq == 0x4) {
--					/* DDR3-667 */
--					calibration_code = 0x00390039;
--				} else if (MemClkFreq == 0x6) {
--					/* DDR3-800 */
--					calibration_code = 0x00390039;
--				} else if (MemClkFreq == 0xa) {
--					/* DDR3-1066 */
--					calibration_code = 0x003a3a3a;
--				} else if (MemClkFreq == 0xe) {
--					/* DDR3-1333 */
--					calibration_code = 0x00003939;
--				} else if (MemClkFreq == 0x12) {
--					/* DDR3-1600 */
--					if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
--						calibration_code = 0x00003738;
 +			} else if (MaxDimmsInstallable == 2) {
 +				if (dimm_count == 1) {
 +					/* 1 DIMM detected */
 +					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+	
++
 +					if (MemClkFreq == 0x4) {
 +						/* DDR3-667 */
 +						if (rank_count_dimm0 == 1)
@@ -373,7 +354,23 @@ index 4a47ee8..c35e972 100644
 +					/* 2 DIMMs detected */
 +					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 +					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+	
+ 
+-				if (MemClkFreq == 0x4) {
+-					/* DDR3-667 */
+-					calibration_code = 0x00390039;
+-				} else if (MemClkFreq == 0x6) {
+-					/* DDR3-800 */
+-					calibration_code = 0x00390039;
+-				} else if (MemClkFreq == 0xa) {
+-					/* DDR3-1066 */
+-					calibration_code = 0x003a3a3a;
+-				} else if (MemClkFreq == 0xe) {
+-					/* DDR3-1333 */
+-					calibration_code = 0x00003939;
+-				} else if (MemClkFreq == 0x12) {
+-					/* DDR3-1600 */
+-					if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
+-						calibration_code = 0x00003738;
 +					if (MemClkFreq == 0x4) {
 +						/* DDR3-667 */
 +						calibration_code = 0x00390039;
@@ -439,8 +436,7 @@ index 4a47ee8..c35e972 100644
 +			/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
 +			if (MaxDimmsInstallable == 1) {
  				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
--
-+	
+ 
  				if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
  					|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
  					/* DDR3-667 - DDR3-1333 */
@@ -458,7 +454,11 @@ index 4a47ee8..c35e972 100644
 -				/* 2 DIMMs detected */
 -				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 -				rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
--
++			} else if (MaxDimmsInstallable == 2) {
++				if (dimm_count == 1) {
++					/* 1 DIMM detected */
++					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
+ 
 -				if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
 -					|| (MemClkFreq == 0xa)) {
 -					/* DDR3-667 - DDR3-1066 */
@@ -466,11 +466,6 @@ index 4a47ee8..c35e972 100644
 -				} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
 -					/* DDR3-1333 - DDR3-1600 */
 -					slow_access = 1;
-+			} else if (MaxDimmsInstallable == 2) {
-+				if (dimm_count == 1) {
-+					/* 1 DIMM detected */
-+					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+	
 +					if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
 +						|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
 +						/* DDR3-667 - DDR3-1333 */
@@ -486,7 +481,7 @@ index 4a47ee8..c35e972 100644
 +					/* 2 DIMMs detected */
 +					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
 +					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
-+	
++
 +					if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
 +						|| (MemClkFreq == 0xa)) {
 +						/* DDR3-667 - DDR3-1066 */
@@ -509,5 +504,5 @@ index 4a47ee8..c35e972 100644
  	} else {
  		/* TODO
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0073-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch b/resources/libreboot/patch/kgpe-d16/0073-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch
deleted file mode 100644
index 6db95da..0000000
--- a/resources/libreboot/patch/kgpe-d16/0073-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From c05d2f8115f94ba223ee481bc8790312d8b9fbd5 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Thu, 25 Jun 2015 15:28:23 -0500
-Subject: [PATCH 073/146] northbridge/amd/amdfam10: Properly indicate node and
- channel in SMBIOS tables
-
----
- src/northbridge/amd/amdfam10/northbridge.c  |    7 ++++++-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   12 ++++++++++++
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |    8 +++++---
- 3 files changed, 23 insertions(+), 4 deletions(-)
-
-diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index f777d02..7cbb732 100644
---- a/src/northbridge/amd/amdfam10/northbridge.c
-+++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -1205,7 +1205,12 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
- 				t->attributes = 0;
- 				t->attributes |= ranks & 0xf;	/* rank number is stored in the lowest 4 bits of the attributes field */
- 				t->form_factor = MEMORY_FORMFACTOR_DIMM;
--				snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1);
-+				if (mem_info->dct_stat[node].Dual_Node_Package) {
-+					snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node >> 1,
-+						(mem_info->dct_stat[node].Internal_Node_ID)?((slot & 0x1)?"D":"C"):((slot & 0x1)?"B":"A"), (slot >> 1) + 1);
-+				} else {
-+					snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1);
-+				}
- 				t->device_locator = smbios_add_string(t->eos, string_buffer);
- 				if (IS_ENABLED(CONFIG_DIMM_DDR2))
- 					t->memory_type = MEMORY_TYPE_DDR2;
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 5a0c746..4a47ee8 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1385,6 +1385,18 @@ restartinit:
- 			pDCTstat->dev_nbctl = PA_NBCTL(Node);
- 			pDCTstat->NodeSysBase = node_sys_base;
- 
-+			if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) {
-+				uint32_t dword;
-+				pDCTstat->Dual_Node_Package = 1;
-+
-+				/* Get the internal node number */
-+				dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8);
-+				dword = (dword >> 30) & 0x3;
-+				pDCTstat->Internal_Node_ID = dword;
-+			} else {
-+				pDCTstat->Dual_Node_Package = 0;
-+			}
-+
- 			printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_init Node %d\n", Node);
- 			mct_init(pMCTstat, pDCTstat);
- 			mctNodeIDDebugPort_D();
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
-index ac8c934..8c9da47 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
-@@ -335,9 +335,11 @@ struct amd_spd_node_data {
- 
- struct DCTStatStruc {		/* A per Node structure*/
- /* DCTStatStruct_F -  start */
--	u8 Node_ID;		/* Node ID of current controller */
--	uint8_t stopDCT;	/* Set if the DCT will be stopped */
--	u8 ErrCode;		/* Current error condition of Node
-+	u8 Node_ID;			/* Node ID of current controller */
-+	uint8_t Internal_Node_ID;	/* Internal Node ID of the current controller */
-+	uint8_t Dual_Node_Package;	/* 1=Dual node package (G34) */
-+	uint8_t stopDCT;		/* Set if the DCT will be stopped */
-+	u8 ErrCode;			/* Current error condition of Node
- 		0= no error
- 		1= Variance Error, DCT is running but not in an optimal configuration.
- 		2= Stop Error, DCT is NOT running
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch b/resources/libreboot/patch/kgpe-d16/0073-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch
index 6436922..43ba5d1 100644
--- a/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch
+++ b/resources/libreboot/patch/kgpe-d16/0073-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch
@@ -1,12 +1,14 @@
-From 46ebd28412a108fc6329118acb53345b44feea4c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 15e1fd712629a70457b1dfd76fe46c539e7c64e5 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 25 Jun 2015 18:08:53 -0500
-Subject: [PATCH 075/146] northbridge/amd/amdmct/mct_ddr3: Attempt to recover
+Subject: [PATCH 073/139] northbridge/amd/amdmct/mct_ddr3: Attempt to recover
  from phy training errors
 
+Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c  |   68 +++++++++++++++++++------
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c |   36 ++++++++++---
+ src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c  | 68 +++++++++++++++++++++------
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 36 +++++++++++---
  2 files changed, 83 insertions(+), 21 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c
@@ -160,7 +162,7 @@ index 5e81808..539cb0d 100644
  			for (dct = 0; dct < 2; dct++) {
  				sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct];
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index 3995a70..72c74e6 100644
+index c760bac..bb076cb 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 @@ -54,7 +54,7 @@ static int32_t abs(int32_t val) {
@@ -218,7 +220,7 @@ index 3995a70..72c74e6 100644
 +				/* Stepping memory clocks between adjacent allowed frequencies
 +				 *  should not yield large phy value differences...
 +				 */
-+				
++
 +				if (abs(total_delay_phy - total_delay_seed) > 0x20)
 +					faulty_value_detected = 1;
 +			}
@@ -250,5 +252,5 @@ index 3995a70..72c74e6 100644
  
  /*----------------------------------------------------------------------------
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch b/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch
index c269358..5703442 100644
--- a/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch
@@ -1,15 +1,17 @@
-From d78d6f37c04273b66bc0de4ea62deea5c033bf97 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 91caf442aef8c846b9d860bf3e8d2954a2a5e21b Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 25 Jun 2015 18:37:45 -0500
-Subject: [PATCH 076/146] northbridge/amd/amdmct/mct_ddr3: Work around strange
+Subject: [PATCH 074/139] northbridge/amd/amdmct/mct_ddr3: Work around strange
  phy training issue
 
+Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c |   16 ++++++++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++
  1 file changed, 16 insertions(+)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index 72c74e6..9c18d12 100644
+index bb076cb..bd37ba7 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 @@ -207,6 +207,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
@@ -36,5 +38,5 @@ index 72c74e6..9c18d12 100644
  		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
  			uint8_t faulty_value_detected = 0;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch b/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch
index 37de631..728e747 100644
--- a/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch
+++ b/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch
@@ -1,19 +1,21 @@
-From 8f15507b4cf857a15d81bf5aaa8447b339a60645 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From feb85d8596ae2447a8ec82e370350e30cfefbc90 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 26 Jun 2015 00:17:10 -0500
-Subject: [PATCH 077/146] northbridge/amd/amdmct/mct_ddr3: Add additional
- debug trace statements
+Subject: [PATCH 075/139] northbridge/amd/amdmct/mct_ddr3: Add additional debug
+ trace statements
 
+Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |    8 ++++++++
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c |   16 ++++++++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |  8 ++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 16 ++++++++++++++++
  2 files changed, 24 insertions(+)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index c35e972..e7eb6af 100644
+index 643fa39..f9a7934 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -5804,7 +5804,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
+@@ -5815,7 +5815,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
  static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
  					struct DCTStatStruc *pDCTstat, u8 dct)
  {
@@ -25,7 +27,7 @@ index c35e972..e7eb6af 100644
  }
  
  static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
-@@ -5814,6 +5818,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5825,6 +5829,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  	u32 dword;
  	u32 dev = pDCTstat->dev_dct;
  
@@ -34,7 +36,7 @@ index c35e972..e7eb6af 100644
  	/* FIXME
  	 * Mainboards need to be able to specify the maximum number of DIMMs installable per channel
  	 * For now assume a maximum of 2 DIMMs per channel can be installed
-@@ -6128,6 +6134,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -6139,6 +6145,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  			Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
  		}
  	}
@@ -114,5 +116,5 @@ index 51cbf16..380c5f2 100644
 +	printk(BIOS_DEBUG, "%s: Done\n", __func__);
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch b/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch
index 2b4ab06..73d5696 100644
--- a/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch
+++ b/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch
@@ -1,16 +1,18 @@
-From e708c2a00f881e5bb37a9b224f72109e2c9ffecc Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 55d9af79adf271287c8cf9091da53b707f67e02f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 26 Jun 2015 12:17:48 -0500
-Subject: [PATCH 078/146] northbridge/amd/amdmct/mct_ddr3: Fix null pointer
+Subject: [PATCH 076/139] northbridge/amd/amdmct/mct_ddr3: Fix null pointer
  access and related hangs
 
+Change-Id: Iaf826b6a0c8e929372519f6d97933515a80f0b39
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |   58 ++++++++++++++------------
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c |    8 ++--
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  | 58 +++++++++++++++-------------
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c |  8 ++--
  2 files changed, 34 insertions(+), 32 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index e7eb6af..61293ba 100644
+index f9a7934..e859c54 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -826,7 +826,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
@@ -41,7 +43,7 @@ index e7eb6af..61293ba 100644
 -					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
 +					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 					
+ 
  					if (MemClkFreq == 0x4) {
  						/* DDR3-667 */
 @@ -943,8 +943,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
@@ -52,7 +54,7 @@ index e7eb6af..61293ba 100644
 -					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
 +					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 					
+ 
  					if (MemClkFreq == 0x4) {
  						/* DDR3-667 */
 @@ -1065,7 +1065,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
@@ -61,7 +63,7 @@ index e7eb6af..61293ba 100644
  			if (MaxDimmsInstallable == 1) {
 -				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +				rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 	
+ 
  				if (MemClkFreq == 0x4) {
  					/* DDR3-667 */
 @@ -1098,7 +1098,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
@@ -70,7 +72,7 @@ index e7eb6af..61293ba 100644
  					/* 1 DIMM detected */
 -					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +					rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 	
+ 
  					if (MemClkFreq == 0x4) {
  						/* DDR3-667 */
 @@ -1127,8 +1127,8 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
@@ -81,7 +83,7 @@ index e7eb6af..61293ba 100644
 -					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
 +					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 	
+ 
  					if (MemClkFreq == 0x4) {
  						/* DDR3-667 */
 @@ -1196,7 +1196,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
@@ -90,7 +92,7 @@ index e7eb6af..61293ba 100644
  			if (MaxDimmsInstallable == 1) {
 -				rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +				rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 	
+ 
  				if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
  					|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
 @@ -1212,7 +1212,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
@@ -99,7 +101,7 @@ index e7eb6af..61293ba 100644
  					/* 1 DIMM detected */
 -					rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +					rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 	
+ 
  					if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
  						|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
 @@ -1227,8 +1227,8 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
@@ -110,10 +112,10 @@ index e7eb6af..61293ba 100644
 -					rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
 +					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
 +					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
- 	
+ 
  					if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
  						|| (MemClkFreq == 0xa)) {
-@@ -5840,14 +5840,18 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5851,14 +5851,18 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  		uint8_t write_odt_delay;
  		uint8_t read_odt_delay;
  
@@ -134,7 +136,7 @@ index e7eb6af..61293ba 100644
  					if (rank_count_dimm1 == 1) {
  						odt_pattern_0 = 0x00000000;
  						odt_pattern_1 = 0x00000000;
-@@ -5872,8 +5876,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5883,8 +5887,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  					}
  				} else {
  					/* 2 DIMMs detected */
@@ -145,7 +147,7 @@ index e7eb6af..61293ba 100644
  					if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) {
  						odt_pattern_0 = 0x00000000;
  						odt_pattern_1 = 0x01010202;
-@@ -5911,7 +5915,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5922,7 +5926,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  				odt_pattern_2 = 0x00000000;
  				odt_pattern_3 = 0x00000000;
  			}
@@ -154,7 +156,7 @@ index e7eb6af..61293ba 100644
  			/* TODO
  			 * Load reduced dimms UNIMPLEMENTED
  			 */
-@@ -5923,7 +5927,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5934,7 +5938,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  			if (MaxDimmsInstallable == 2) {
  				if (dimm_count == 1) {
  					/* 1 DIMM detected */
@@ -163,7 +165,7 @@ index e7eb6af..61293ba 100644
  					if (rank_count_dimm1 == 1) {
  						odt_pattern_0 = 0x00000000;
  						odt_pattern_1 = 0x00000000;
-@@ -5959,7 +5963,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5970,7 +5974,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  			}
  		}
  
@@ -172,7 +174,7 @@ index e7eb6af..61293ba 100644
  			/* TODO
  			 * Load reduced dimms UNIMPLEMENTED
  			 */
-@@ -6019,11 +6023,11 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -6030,11 +6034,11 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  			/* Select appropriate ODT pattern for installed DIMMs
  			 * Refer to the Fam10h BKDG Rev. 3.62, page 120 onwards
  			 */
@@ -186,7 +188,7 @@ index e7eb6af..61293ba 100644
  						if (rank_count_dimm1 == 1) {
  							odt_pattern_0 = 0x00000000;
  							odt_pattern_1 = 0x00000000;
-@@ -6048,8 +6052,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -6059,8 +6063,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  						}
  					} else {
  						/* 2 DIMMs detected */
@@ -197,7 +199,7 @@ index e7eb6af..61293ba 100644
  						if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) {
  							odt_pattern_0 = 0x00000000;
  							odt_pattern_1 = 0x01010202;
-@@ -6091,7 +6095,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -6102,7 +6106,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  				if (MaxDimmsInstallable == 2) {
  					if (dimm_count == 1) {
  						/* 1 DIMM detected */
@@ -234,5 +236,5 @@ index 380c5f2..c7d7463 100644
  
  	if (is_fam15h())
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch b/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch
index 4993062..b406fc9 100644
--- a/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch
+++ b/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch
@@ -1,16 +1,18 @@
-From 7a77252a55fa5de541a7e6c687fcd42168f86d55 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From bc99fcbab8c0bd2851216a34f3d72fddbe790332 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 26 Jun 2015 14:15:57 -0500
-Subject: [PATCH 079/146] northbridge/amd/amdmct/mct_ddr3: Add missing Family
+Subject: [PATCH 077/139] northbridge/amd/amdmct/mct_ddr3: Add missing Family
  15h RDIMM Rtt values
 
+Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |    4 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c |  201 +++++++++++++++++++++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |   4 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 201 ++++++++++++++++++++++++++-
  2 files changed, 198 insertions(+), 7 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 61293ba..68ff3f8 100644
+index e859c54..8ca2c25 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -897,8 +897,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
@@ -262,5 +264,5 @@ index c7d7463..dfbd2d9 100644
  				/* Socket G34: Fam15h BKDG v3.14 Table 56 */
  				if (MaxDimmsInstallable == 1) {
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch b/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch
index 5f3df4a..7b3d0f1 100644
--- a/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch
@@ -1,19 +1,21 @@
-From 171fd97470dab51d069dc434e3e99ef64a8c77bd Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From e8926cb6ee7046c3b4ceacb1ca8c885a2ec1c037 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 26 Jun 2015 17:49:25 -0500
-Subject: [PATCH 080/146] northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when
+Subject: [PATCH 078/139] northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when
  both DCTs are in use
 
+Change-Id: Ibcce54fc53b79beba2f790994bcf87cc0354213a
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   41 +++++++++++++++++++++------
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |    2 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 41 +++++++++++++++++++++++------
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |  2 +-
  2 files changed, 34 insertions(+), 9 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 68ff3f8..98a6952 100644
+index 8ca2c25..aea17a1 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -2636,7 +2636,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC
+@@ -2643,7 +2643,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC
  
  	/* Reset DCT registers */
  	ClearDCT_D(pMCTstat, pDCTstat, dct);
@@ -22,7 +24,7 @@ index 68ff3f8..98a6952 100644
  
  	if (!is_fam15h()) {
  		/* Enable DDR3 support */
-@@ -2647,7 +2647,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC
+@@ -2654,7 +2654,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC
  
  	/* Read the SPD information into the data structures */
  	if (mct_DIMMPresence(pMCTstat, pDCTstat, dct) < SC_StopError) {
@@ -31,7 +33,7 @@ index 68ff3f8..98a6952 100644
  	}
  }
  
-@@ -2673,17 +2673,40 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
+@@ -2680,17 +2680,40 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
  				printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n");
  				if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) {
  					printk(BIOS_DEBUG, "\t\tDCTInit_D: PlatformSpec_D Done\n");
@@ -78,7 +80,7 @@ index 68ff3f8..98a6952 100644
  		dword = 1 << DisDramInterface;
  		Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword);
  
-@@ -4337,6 +4360,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
+@@ -4348,6 +4371,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
  
  	/* Config. DCT0 for Ganged or unganged mode */
  	DCTInit_D(pMCTstat, pDCTstat, 0);
@@ -86,7 +88,7 @@ index 68ff3f8..98a6952 100644
  	if (pDCTstat->ErrCode == SC_FatalErr) {
  		/* Do nothing goto exitDCTInit; any fatal errors? */
  	} else {
-@@ -4346,6 +4370,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
+@@ -4357,6 +4381,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
  				err_code = pDCTstat->ErrCode;		/* save DCT0 errors */
  				pDCTstat->ErrCode = 0;
  				DCTInit_D(pMCTstat, pDCTstat, 1);
@@ -108,5 +110,5 @@ index 8c9da47..7bc392b 100644
  		0= no error
  		1= Variance Error, DCT is running but not in an optimal configuration.
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch b/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch
index 4f9da00..2f8a513 100644
--- a/resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch
+++ b/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch
@@ -1,11 +1,13 @@
-From 9ee624980e31d6f489505388f417e06d121d0947 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 146d781ece056408e0ba28b4c8d7a46df6d0257a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 27 Jun 2015 17:52:18 -0500
-Subject: [PATCH 081/146] northbridge/amd/amdmct/mct_ddr3: Properly indicate
+Subject: [PATCH 079/139] northbridge/amd/amdmct/mct_ddr3: Properly indicate
  clobbered registers
 
+Change-Id: Icb2754143762bd64ee1df5674fa071de1c595eaf
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h |   11 +++++++++--
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 11 +++++++++--
  1 file changed, 9 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h
@@ -52,5 +54,5 @@ index f6aa755..cc8d971 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0082-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch b/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch
index d7d15cc..4f7af96 100644
--- a/resources/libreboot/patch/kgpe-d16/0082-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch
@@ -1,19 +1,21 @@
-From 3d30e829f9630d588dee70215b67343c75996520 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From ddbdb1b748edc2f8a8c453d93a36f28e7d26f2e5 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 27 Jun 2015 17:52:45 -0500
-Subject: [PATCH 082/146] northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot
+Subject: [PATCH 080/139] northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot
  failure
 
+Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |   28 +++++++++++++++++++-------
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c |    8 +++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  | 28 +++++++++++++++++++++-------
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c |  8 +++++++-
  2 files changed, 28 insertions(+), 8 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 98a6952..6de8140 100644
+index aea17a1..1758bd6 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1622,6 +1622,11 @@ restartinit:
+@@ -1628,6 +1628,11 @@ restartinit:
  		HTMemMapInit_D(pMCTstat, pDCTstatA);	/* Map local memory into system address space.*/
  		mctHookAfterHTMap();
  
@@ -25,7 +27,7 @@ index 98a6952..6de8140 100644
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n");
  		mctHookAfterCPU();			/* Setup external northbridge(s) */
  
-@@ -1645,6 +1650,11 @@ restartinit:
+@@ -1651,6 +1656,11 @@ restartinit:
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
  		DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore);	/* Get Receiver Enable and DQS signal timing*/
  
@@ -37,7 +39,7 @@ index 98a6952..6de8140 100644
  		if (!allow_config_restore) {
  			printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
  			mct_OtherTiming(pMCTstat, pDCTstatA);
-@@ -1665,11 +1675,13 @@ restartinit:
+@@ -1671,11 +1681,13 @@ restartinit:
  			MCTMemClr_D(pMCTstat,pDCTstatA);
  		}
  
@@ -55,7 +57,7 @@ index 98a6952..6de8140 100644
  
  		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
  		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
-@@ -6332,11 +6344,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
+@@ -6343,11 +6355,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
  		DramMRS |= 1 << 1;
  
  	dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84);
@@ -73,14 +75,14 @@ index 98a6952..6de8140 100644
  }
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index 039fcf8..1d41aa4 100644
+index 011a94f..57641a1 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-@@ -909,9 +909,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
+@@ -908,9 +908,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
  			 * Flush the receiver FIFO
  			 * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO
  			 */
--			
+-
 +			/* FIXME
 +			 * This does not seem to be needed, and has a tendency to lock up the
 +			 * boot process while attempting to write the test pattern.
@@ -94,5 +96,5 @@ index 039fcf8..1d41aa4 100644
  		MaxDelay_CH[Channel] = CTLRMaxDelay;
  	}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0083-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch b/resources/libreboot/patch/kgpe-d16/0081-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch
index 81602d4..32a1e8a 100644
--- a/resources/libreboot/patch/kgpe-d16/0083-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch
+++ b/resources/libreboot/patch/kgpe-d16/0081-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch
@@ -1,15 +1,18 @@
-From 4ac11f31fdfe91eb2d6e998f293f88fb0a32452c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 789bac438e1ab4c10ec6bbeb9f62a78d0abcd156 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 3 Jul 2015 17:16:22 -0500
-Subject: [PATCH 083/146] src/southbridge/amd/sr5650: Always configure lane
+Subject: [PATCH 081/139] src/southbridge/amd/sr5650: Always configure lane
  director on startup
 
 On the ASUS KGPE-D16 it was noted that the pin straps did not properly
 configure the lane director hardware, causing link training failure
 on NIC B.  Forcing coreboot to always reconfigure the lane director
 on startup resolves this problem.
+
+Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sr5650/pcie.c |   13 +++----------
+ src/southbridge/amd/sr5650/pcie.c | 13 +++----------
  1 file changed, 3 insertions(+), 10 deletions(-)
 
 diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
@@ -44,5 +47,5 @@ index 79f2a5f..09ce217 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0082-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch b/resources/libreboot/patch/kgpe-d16/0082-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch
new file mode 100644
index 0000000..72f6948
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0082-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch
@@ -0,0 +1,28 @@
+From 170af60b6ef005f40458f7d55d370dbc083a9a8b Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 24 Jul 2015 17:34:29 -0500
+Subject: [PATCH 082/139] cpu/amd/family_10h-family_15h: Fix BSP stack
+ corruption on 32-core Fam10 systems
+
+Change-Id: I72ae8f7abeb9a83b57505469922818f9ec5bdf3f
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/family_10h-family_15h/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
+index 81b1d1e..b95943f 100644
+--- a/src/cpu/amd/family_10h-family_15h/Kconfig
++++ b/src/cpu/amd/family_10h-family_15h/Kconfig
+@@ -37,7 +37,7 @@ config DCACHE_BSP_STACK_SIZE
+ 
+ config DCACHE_BSP_STACK_SLUSH
+ 	hex
+-	default 0x1000
++	default 0x4000
+ 
+ config DCACHE_AP_STACK_SIZE
+ 	hex
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0085-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch b/resources/libreboot/patch/kgpe-d16/0083-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch
index 351906e..6bf6885 100644
--- a/resources/libreboot/patch/kgpe-d16/0085-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch
+++ b/resources/libreboot/patch/kgpe-d16/0083-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch
@@ -1,28 +1,30 @@
-From 4faf00104dc3474340520213fc0e5f15f14e7146 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 34c8a0f868d298f787713a2dd3ba6852c794ae86 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 25 Jul 2015 01:23:17 -0500
-Subject: [PATCH 085/146] northbridge/amd/amdmct/mct_ddr3: Fix RDIMM errors
- due to undefined number of slots
+Subject: [PATCH 083/139] northbridge/amd/amdmct/mct_ddr3: Fix RDIMM errors due
+ to undefined number of slots
 
+Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct/mct_d.h         |    2 ++
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |   40 +++++++-----------------
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |    2 ++
- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c  |    6 +---
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   |   12 ++-----
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |    6 +---
- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    |    2 --
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |   24 +++++---------
- src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c |   11 ++++---
- src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h   |    4 ---
- src/northbridge/amd/amdmct/wrappers/mcti_d.c   |    7 +++++
- 11 files changed, 41 insertions(+), 75 deletions(-)
+ src/northbridge/amd/amdmct/mct/mct_d.h         |  2 ++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 24 ++++--------------------
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |  2 ++
+ src/northbridge/amd/amdmct/mct_ddr3/mctproc.c  |  6 +-----
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   | 12 ++----------
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |  6 +-----
+ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    |  2 --
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  | 20 ++++++--------------
+ src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c | 11 ++++++-----
+ src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h   |  4 ----
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c   |  7 +++++++
+ 11 files changed, 31 insertions(+), 65 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
-index 6b6194d..34f7f4c 100644
+index 7569300..296f3f0 100644
 --- a/src/northbridge/amd/amdmct/mct/mct_d.h
 +++ b/src/northbridge/amd/amdmct/mct/mct_d.h
-@@ -688,6 +688,8 @@ struct DCTStatStruc {		/* A per Node structure*/
+@@ -691,6 +691,8 @@ struct DCTStatStruc {		/* A per Node structure*/
  					xx0b = disable
  					yy1b = enable with DctSelIntLvAddr set to yyb */
  
@@ -32,7 +34,7 @@ index 6b6194d..34f7f4c 100644
  	CBMEM storage
  ===============================================================================*/
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 6de8140..030372d 100644
+index 1758bd6..b616c2d 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -803,11 +803,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p
@@ -48,24 +50,6 @@ index 6de8140..030372d 100644
  
  	uint8_t package_type;
  	uint32_t calibration_code = 0;
-@@ -877,7 +873,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
- 					/* 2 DIMMs detected */
- 					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
- 					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
--					
-+
- 					if (MemClkFreq == 0x4) {
- 						/* DDR3-667 */
- 						calibration_code = 0x10222222;
-@@ -945,7 +941,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
- 					/* 2 DIMMs detected */
- 					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
- 					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
--					
-+
- 					if (MemClkFreq == 0x4) {
- 						/* DDR3-667 */
- 						calibration_code = 0x10222222;
 @@ -983,11 +979,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
  
  static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct)
@@ -79,33 +63,6 @@ index 6de8140..030372d 100644
  
  	uint8_t package_type;
  	uint32_t calibration_code = 0;
-@@ -1066,7 +1058,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
- 			/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
- 			if (MaxDimmsInstallable == 1) {
- 				rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
--	
-+
- 				if (MemClkFreq == 0x4) {
- 					/* DDR3-667 */
- 					if (rank_count_dimm0 == 1)
-@@ -1099,7 +1091,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
- 				if (dimm_count == 1) {
- 					/* 1 DIMM detected */
- 					rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
--	
-+
- 					if (MemClkFreq == 0x4) {
- 						/* DDR3-667 */
- 						if (rank_count_dimm0 == 1)
-@@ -1129,7 +1121,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
- 					/* 2 DIMMs detected */
- 					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
- 					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
--	
-+
- 					if (MemClkFreq == 0x4) {
- 						/* DDR3-667 */
- 						calibration_code = 0x00390039;
 @@ -1165,11 +1157,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
  
  static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct)
@@ -119,34 +76,7 @@ index 6de8140..030372d 100644
  
  	uint8_t package_type;
  	uint32_t slow_access = 0;
-@@ -1197,7 +1185,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
- 			/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
- 			if (MaxDimmsInstallable == 1) {
- 				rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
--	
-+
- 				if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
- 					|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
- 					/* DDR3-667 - DDR3-1333 */
-@@ -1213,7 +1201,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
- 				if (dimm_count == 1) {
- 					/* 1 DIMM detected */
- 					rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
--	
-+
- 					if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
- 						|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
- 						/* DDR3-667 - DDR3-1333 */
-@@ -1229,7 +1217,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
- 					/* 2 DIMMs detected */
- 					rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
- 					rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
--	
-+
- 					if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
- 						|| (MemClkFreq == 0xa)) {
- 						/* DDR3-667 - DDR3-1066 */
-@@ -5857,11 +5845,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5868,11 +5856,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  
  	printk(BIOS_DEBUG, "%s: Start\n", __func__);
  
@@ -220,7 +150,7 @@ index dfbd2d9..6a2c2a7 100644
  	if (is_fam15h()) {
  		if (pDCTstat->Status & (1 << SB_LoadReduced)) {
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index 1d41aa4..3655e84 100644
+index 57641a1..9313673 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 @@ -105,11 +105,7 @@ static uint16_t fam15_receiver_enable_training_seed(struct DCTStatStruc *pDCTsta
@@ -250,18 +180,9 @@ index 0ff4484..6b63ba0 100644
  
  void PrepareC_DCT(struct MCTStatStruc *pMCTstat,
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index 9c18d12..26e1374 100644
+index bd37ba7..47ad152 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-@@ -191,7 +191,7 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
- 		uint8_t index = (uint8_t)(MAX_BYTE_LANES * dimm);
- 
- 		/* Calculate the Critical Gross Delay */
--		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {	
-+		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
- 			/* Calculate the gross delay differential for this lane */
- 			gross_diff[ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane] + pDCTData->WLGrossDelay[index+ByteLane];
- 			gross_diff[ByteLane] -= pDCTData->WLSeedPreGrossDelay[index+ByteLane];
 @@ -419,11 +419,7 @@ static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms
  {
  	uint16_t term;
@@ -288,17 +209,15 @@ index 9c18d12..26e1374 100644
  
  	if (number_of_dimms == 1) {
  		if (MaxDimmsInstallable < 3) {
-@@ -574,8 +566,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
+@@ -574,7 +566,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
  					if (number_of_dimms > 1) {
  						if (rank == 0) {
  							/* Get Rtt_WR for the current DIMM and rank */
 -							uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm]);
--	
 +							uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm]);
-+
+ 
  							/* Convert dynamic termination code to corresponding nominal termination code */
  							if (dynamic_term == 0x200)
- 								tempW1 = 0x04;
 @@ -584,13 +576,13 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
  							else
  								tempW1 = 0x0;
@@ -389,7 +308,7 @@ index 162340e..12e7c4a 100644
  } sMCTStruct;
  
 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
-index 2376b20..85f117b 100644
+index ce2329d..28d298f 100644
 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
 @@ -74,6 +74,13 @@ static u16 mctGet_NVbits(u8 index)
@@ -407,5 +326,5 @@ index 2376b20..85f117b 100644
  		/* Maximum platform supported memclk */
  		val =  MEM_MAX_LOAD_FREQ;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0086-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch b/resources/libreboot/patch/kgpe-d16/0084-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch
index df19909..565f248 100644
--- a/resources/libreboot/patch/kgpe-d16/0086-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch
+++ b/resources/libreboot/patch/kgpe-d16/0084-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch
@@ -1,24 +1,27 @@
-From 00c038da36969597eb1c8e6e526ec0b0a9f12b43 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 02fa90cabc031623e5a5e05888588fb1f22949d2 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 26 Jul 2015 00:55:43 -0500
-Subject: [PATCH 086/146] amd/amdmct/mct_ddr3: Partially fix up registered
+Subject: [PATCH 084/139] amd/amdmct/mct_ddr3: Partially fix up registered
  DIMMs on Fam10h
 
 Sufficient support has been added to allow booting with registered
 DIMMs on the KGPE-D16 in certain slots.  ECC support needs additional
 work; the ECC data lanes appear to cause boot failures in some slots.
+
+Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |  196 ++++++++++++++++++++++--
- src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c |   32 ++--
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   58 ++++---
- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c   |  151 ++++++++++++------
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   |    8 +
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |   26 ++--
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |   72 ++++++---
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 196 ++++++++++++++++++++++---
+ src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c |  32 ++--
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |  58 +++++---
+ src/northbridge/amd/amdmct/mct_ddr3/mctrci.c   | 151 ++++++++++++-------
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   |   8 +
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |  26 ++--
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |  72 ++++++---
  7 files changed, 399 insertions(+), 144 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 030372d..28796bb 100644
+index b616c2d..8102f2a 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -305,6 +305,120 @@ static uint16_t mhz_to_memclk_config(uint16_t freq)
@@ -193,12 +196,12 @@ index 030372d..28796bb 100644
 +}
 +#endif
 +
+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
  static void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat)
- {
-@@ -1504,12 +1638,14 @@ restartinit:
- 		restore_mct_information_from_nvram(0);
+@@ -1508,12 +1642,14 @@ restartinit:
  		pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
+ #endif
  
 -		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
 -		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -216,7 +219,7 @@ index 030372d..28796bb 100644
  		}
  	} else {
  		NodesWmem = 0;
-@@ -1669,14 +1805,14 @@ restartinit:
+@@ -1675,14 +1811,14 @@ restartinit:
  
  			printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
  			UMAMemTyping_D(pMCTstat, pDCTstatA);	/* Fix up for UMA sizing */
@@ -237,7 +240,7 @@ index 030372d..28796bb 100644
  		}
  
  		if (is_fam15h()) {
-@@ -2710,6 +2846,10 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p
+@@ -2717,6 +2853,10 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p
  		dword = 1 << DisDramInterface;
  		Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword);
  
@@ -248,7 +251,7 @@ index 030372d..28796bb 100644
  		/* To maximize power savings when DisDramInterface=1b,
  		 * all of the MemClkDis bits should also be set.
  		 */
-@@ -3593,7 +3733,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3600,7 +3740,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  		dword++;
  	}
  
@@ -259,7 +262,7 @@ index 030372d..28796bb 100644
  		DramConfigLo |= 1 << UnBuffDimm;	/* Unbuffered DIMMs */
  
  	if (mctGet_NVbits(NV_ECC_CAP))
-@@ -4082,6 +4224,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -4089,6 +4231,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  			if (status >= 0) { /* SPD access is ok */
  				pDCTstat->DIMMPresent |= 1 << i;
  				read_spd_bytes(pMCTstat, pDCTstat, i);
@@ -269,7 +272,7 @@ index 030372d..28796bb 100644
  				crc_status = crcCheck(pDCTstat, i);
  				if (!crc_status) {
  					/* Try again in case there was a transient glitch */
-@@ -4377,6 +4522,10 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
+@@ -4388,6 +4533,10 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
  				val = 1 << DisDramInterface;
  				Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val);
  
@@ -280,7 +283,7 @@ index 030372d..28796bb 100644
  				/* To maximize power savings when DisDramInterface=1b,
  				 * all of the MemClkDis bits should also be set.
  				 */
-@@ -4529,8 +4678,9 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
+@@ -4540,8 +4689,9 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
  	}
  	for (i=i_start; i<i_end; i++) {
  		index_reg = 0x98;
@@ -292,7 +295,7 @@ index 030372d..28796bb 100644
  	}
  
  	return pDCTstat->ErrCode;
-@@ -4587,11 +4737,19 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
+@@ -4598,11 +4748,19 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
  		val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94);
  		val |= 1 << DisDramInterface;
  		Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, val);
@@ -312,7 +315,7 @@ index 030372d..28796bb 100644
  	}
  
  	printk(BIOS_DEBUG, "SPDCalcWidth: Status %x\n", pDCTstat->Status);
-@@ -6022,6 +6180,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -6033,6 +6191,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  		dword &= ~(0xf);				/* RdOdtTrnOnDly = read_odt_delay */
  		dword |= (read_odt_delay & 0xf);
  		Set_NB32_DCT(dev, dct, 0x240, dword);
@@ -321,7 +324,7 @@ index 030372d..28796bb 100644
  	} else if (pDCTstat->LogicalCPUID & AMD_DR_Dx) {
  		if (pDCTstat->Speed == 3)
  			dword = 0x00000800;
-@@ -6157,6 +6317,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -6168,6 +6328,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  			Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x181, odt_pattern_0);
  			Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x182, odt_pattern_3);
  			Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
@@ -406,7 +409,7 @@ index 3df262b..4ae1aec 100644
  		*ODC_CTL = 0x00223323;
  	}
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 207a135..41b7244 100644
+index b0ad54b..36e9858 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -241,37 +241,53 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
@@ -467,15 +470,15 @@ index 207a135..41b7244 100644
  
 -	DQSDelay >>= 8;		/* 256 */
 +		DQSDelay = DQSDelay * (~scale);
-+	
-+		DQSDelay += 0x80;	/* round it */
-+	
-+		DQSDelay >>= 8;		/* 256 */
  
 -	if (DQSDelay0>DQSDelay1) {
 -		DQSDelay = DQSDelay1 - DQSDelay;
 -	} else {
 -		DQSDelay += DQSDelay1;
++		DQSDelay += 0x80;	/* round it */
++
++		DQSDelay >>= 8;		/* 256 */
++
 +		if (DQSDelay0>DQSDelay1) {
 +			DQSDelay = DQSDelay1 - DQSDelay;
 +		} else {
@@ -746,10 +749,10 @@ index 6a2c2a7..9ccf77e 100644
  }
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index 3655e84..abb5321 100644
+index 9313673..981f467 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-@@ -1745,6 +1745,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -1744,6 +1744,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
  	u16 EccDQSLike;
  	u8 EccDQSScale;
  	u32 val, val0, val1;
@@ -757,7 +760,7 @@ index 3655e84..abb5321 100644
  
  	EccDQSLike = pDCTstat->CH_EccDQSLike[Channel];
  	EccDQSScale = pDCTstat->CH_EccDQSScale[Channel];
-@@ -1754,14 +1755,22 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -1753,14 +1754,22 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
  			u16 *p;
  			p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1];
  
@@ -773,7 +776,7 @@ index 3655e84..abb5321 100644
 +
 +				delay_differential = (int16_t)val1 - (int16_t)val0;
 +				delay_differential += (int16_t)val1;
-+	
++
 +				val = delay_differential;
 +			} else {
 +				/* DQS Delay Value of Data Bytelane
@@ -787,7 +790,7 @@ index 3655e84..abb5321 100644
  				if(val0 > val1) {
  					val = val0 - val1;
  				} else {
-@@ -1776,9 +1785,6 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -1775,9 +1784,6 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
  				} else {
  					val += val0;
  				}
@@ -798,7 +801,7 @@ index 3655e84..abb5321 100644
  
  			pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index 26e1374..fb3b3d8 100644
+index 47ad152..e5e4031 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 @@ -930,7 +930,9 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
@@ -953,5 +956,5 @@ index 26e1374..fb3b3d8 100644
 +	printk(BIOS_SPEW, "\tLane %02x final adjusted value: %04x\n", ByteLane, ((gross & 0x1f) << 5) | (fine & 0x1f));
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0084-cpu-amd-model_10xxx-Fix-BSP-stack-corruption-on-32-c.patch b/resources/libreboot/patch/kgpe-d16/0084-cpu-amd-model_10xxx-Fix-BSP-stack-corruption-on-32-c.patch
deleted file mode 100644
index c527503..0000000
--- a/resources/libreboot/patch/kgpe-d16/0084-cpu-amd-model_10xxx-Fix-BSP-stack-corruption-on-32-c.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 50df46615e5505f7b649c20a08e0cfbcc7c34eb6 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Fri, 24 Jul 2015 17:34:29 -0500
-Subject: [PATCH 084/146] cpu/amd/model_10xxx: Fix BSP stack corruption on
- 32-core Fam10 systems
-
----
- src/cpu/amd/model_10xxx/Kconfig |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
-index 79db42a..d6bcaa2 100644
---- a/src/cpu/amd/model_10xxx/Kconfig
-+++ b/src/cpu/amd/model_10xxx/Kconfig
-@@ -36,7 +36,7 @@ config DCACHE_BSP_STACK_SIZE
- 
- config DCACHE_BSP_STACK_SLUSH
- 	hex
--	default 0x1000
-+	default 0x4000
- 
- config DCACHE_AP_STACK_SIZE
- 	hex
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0087-northbridge-amd-amdmct-Fix-Family-15h-detection.patch b/resources/libreboot/patch/kgpe-d16/0085-northbridge-amd-amdmct-Fix-Family-15h-detection.patch
index 3c09ca6..f9d5afb 100644
--- a/resources/libreboot/patch/kgpe-d16/0087-northbridge-amd-amdmct-Fix-Family-15h-detection.patch
+++ b/resources/libreboot/patch/kgpe-d16/0085-northbridge-amd-amdmct-Fix-Family-15h-detection.patch
@@ -1,11 +1,13 @@
-From 82ac366ef8d8c624af7038cc5bfa58c8c5a3486c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5ab09d94caec3d1b2cbc156fdf0b32bd7c2e518c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 28 Jul 2015 13:45:29 -0500
-Subject: [PATCH 087/146] northbridge/amd/amdmct: Fix Family 15h detection
+Subject: [PATCH 085/139] northbridge/amd/amdmct: Fix Family 15h detection
 
+Change-Id: I3623f8945bd62b7050ec609934f96543552c792b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct/mct.h        |    3 ++-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |    2 +-
+ src/northbridge/amd/amdmct/mct/mct.h        | 3 ++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +-
  2 files changed, 3 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h
@@ -43,5 +45,5 @@ index 6b5d8c1..e327d38 100644
  void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass);
  void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch b/resources/libreboot/patch/kgpe-d16/0086-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch
index 0aba7eb..37cda08 100644
--- a/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch
+++ b/resources/libreboot/patch/kgpe-d16/0086-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch
@@ -1,24 +1,26 @@
-From 46e87f3f6b6085488fa6eb8b5ad69ba2efdc3e4f Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 95e15fd07cd76057737c0b52a4ece6f73501ea1e Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 28 Jul 2015 15:16:46 -0500
-Subject: [PATCH 088/146] northbridge/amd/amdmct/mct_ddr3: Add registered and
+Subject: [PATCH 086/139] northbridge/amd/amdmct/mct_ddr3: Add registered and
  x4 DIMM support to Fam15h
 
+Change-Id: I9ee0bb7346aa35f564fe535cdd337ec7f6148f2b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |  186 ++++++-----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |    2 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |    4 +
- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c   |   17 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c   |  191 +++++++----
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   |   42 ++-
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |  267 +++++++++-------
- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    |   16 +-
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |  402 +++++++++++++++---------
- src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h   |   13 +-
- 10 files changed, 706 insertions(+), 434 deletions(-)
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 186 +++++++-----
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |   2 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   4 +
+ src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c   |  17 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctrci.c   | 191 ++++++++----
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   |  42 ++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   | 253 +++++++++-------
+ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    |  16 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  | 400 +++++++++++++++----------
+ src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h   |  13 +-
+ 10 files changed, 698 insertions(+), 426 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 28796bb..55cdd24 100644
+index 8102f2a..5a57dc0 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -166,7 +166,7 @@ static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,
@@ -41,7 +43,7 @@ index 28796bb..55cdd24 100644
  	delay_ns = (((uint64_t)clocks * 1000) / fam15h_freq_tab[memclk_freq]);
  	precise_ndelay_fam15(pMCTstat, delay_ns);
  }
-@@ -2315,7 +2319,7 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -2320,7 +2324,7 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  	nv_DQSTrainCTL = !allow_config_restore;
  
  	mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
@@ -50,7 +52,7 @@ index 28796bb..55cdd24 100644
  
  	if (is_fam15h()) {
  		uint8_t Node;
-@@ -3350,7 +3354,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3357,7 +3361,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  }
  
  static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
@@ -59,7 +61,7 @@ index 28796bb..55cdd24 100644
  {
  	/* Initialize  DCT Timing registers as per DIMM SPD.
  	 * For primary timing (T, CL) use best case T value.
-@@ -3454,7 +3458,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
+@@ -3461,7 +3465,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
  }
  
  static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
@@ -68,7 +70,7 @@ index 28796bb..55cdd24 100644
  {
  	/* Find the best T and CL primary timing parameter pair, per Mfg.,
  	 * for the given set of DIMMs, and store into DCTStatStruc
-@@ -3733,10 +3737,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3740,10 +3744,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  		dword++;
  	}
  
@@ -88,7 +90,7 @@ index 28796bb..55cdd24 100644
  
  	if (mctGet_NVbits(NV_ECC_CAP))
  		if (Status & (1 << SB_ECCDIMMs))
-@@ -3754,10 +3763,11 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3761,10 +3770,11 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	DramConfigHi |= dword - offset;	/* get MemClk encoding */
  	DramConfigHi |= 1 << MemClkFreqVal;
  
@@ -104,7 +106,7 @@ index 28796bb..55cdd24 100644
  
  	if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) {
  		DramConfigLo |= 1 << 25;	/* PendRefPaybackS3En = 1 */
-@@ -3769,14 +3779,16 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3776,14 +3786,16 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  			DramConfigHi |= 1 << 16;
  	}
  
@@ -127,7 +129,7 @@ index 28796bb..55cdd24 100644
  		byte = mctGet_NVbits(NV_4RANKType);
  		if (byte == 2)
  			DramConfigHi |= 1 << 17;	/* S4 (4-Rank SO-DIMMs) */
-@@ -4577,8 +4589,9 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
+@@ -4588,8 +4600,9 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
  			Set_NB32(pDCTstat->dev_dct, reg, val);
  		}
  		if (byte)	/* NV_Unganged */
@@ -138,7 +140,7 @@ index 28796bb..55cdd24 100644
  	return pDCTstat->ErrCode;
  }
  
-@@ -4639,6 +4652,8 @@ void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data)
+@@ -4650,6 +4663,8 @@ void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data)
  static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat,
  					struct DCTStatStruc *pDCTstat, u8 dct)
  {
@@ -147,7 +149,7 @@ index 28796bb..55cdd24 100644
  	/* mct_checkForCxDxSupport_D */
  	if (pDCTstat->LogicalCPUID & AMD_DR_GT_Bx) {
  		/* Family 10h Errata 322: Address and Command Fine Delay Values May Be Incorrect */
-@@ -4653,6 +4668,9 @@ static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat,
+@@ -4664,6 +4679,9 @@ static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat,
  		else
  			Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0D02E001, 0x90);
  	}
@@ -157,7 +159,7 @@ index 28796bb..55cdd24 100644
  	return pDCTstat->ErrCode;
  }
  
-@@ -4663,6 +4681,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
+@@ -4674,6 +4692,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
  	 * and program them into DCT.
  	 */
  
@@ -166,7 +168,7 @@ index 28796bb..55cdd24 100644
  	u32 dev = pDCTstat->dev_dct;
  	u32 index_reg;
  	u8 i, i_start, i_end;
-@@ -4683,6 +4703,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
+@@ -4694,6 +4714,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
  		printk(BIOS_SPEW, "Programmed DCT %d timing/termination pattern %08x %08x\n", dct, pDCTstat->CH_ADDR_TMG[i], pDCTstat->CH_ODC_CTL[i]);
  	}
  
@@ -175,7 +177,7 @@ index 28796bb..55cdd24 100644
  	return pDCTstat->ErrCode;
  }
  
-@@ -4694,7 +4716,8 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat)
+@@ -4705,7 +4727,8 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat)
  	if (pDCTstat->NodePresent) {
  		dev = pDCTstat->dev_dct;
  
@@ -185,7 +187,7 @@ index 28796bb..55cdd24 100644
  			do {
  				val = Get_NB32(dev, 0x110);
  			} while (!(val & (1 << DramEnabled)));
-@@ -5642,57 +5665,56 @@ static void InitDDRPhy(struct MCTStatStruc *pMCTstat,
+@@ -5653,57 +5676,56 @@ static void InitDDRPhy(struct MCTStatStruc *pMCTstat,
  	/* Fam15h BKDG v3.14 section 2.10.5.3
  	 * The remainder of the Phy Initialization algorithm picks up in phyAssistedMemFnceTraining
  	 */
@@ -292,7 +294,7 @@ index 28796bb..55cdd24 100644
  
  	printk(BIOS_DEBUG, "%s: Done\n", __func__);
  }
-@@ -5708,18 +5730,24 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
+@@ -5719,18 +5741,24 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
  	uint32_t dword;
  	const u8 *p;
  
@@ -320,7 +322,7 @@ index 28796bb..55cdd24 100644
  		/* Determine TxPreP/TxPreN for data lanes (Stage 1) */
  		dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000);
  		drive_strength = (dword >> 20) & 0x7;	/* DqsDrvStren */
-@@ -5865,12 +5893,14 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
+@@ -5876,12 +5904,14 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
  		Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0a, dword);
  	}
  
@@ -336,7 +338,7 @@ index 28796bb..55cdd24 100644
  	if (!is_fam15h()) {
  		u32 reg;
  		u32 val;
-@@ -5892,6 +5922,8 @@ static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat,
+@@ -5903,6 +5933,8 @@ static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat,
  
  		Set_NB32_DCT(dev, dct, reg, val);
  	}
@@ -345,7 +347,7 @@ index 28796bb..55cdd24 100644
  }
  
  static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
-@@ -6535,6 +6567,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
+@@ -6546,6 +6578,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
  
  	uint32_t dword;
  
@@ -354,7 +356,7 @@ index 28796bb..55cdd24 100644
  	if (is_fam15h()) {
  		/* Initial setup for frequency change
  		 * 9C_x0000_0004 must be configured before MemClkFreqVal is set
-@@ -6567,6 +6601,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
+@@ -6578,6 +6612,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
  		mct_Wait(100);
  	}
  
@@ -363,7 +365,7 @@ index 28796bb..55cdd24 100644
  	/* Program the DRAM Configuration High register */
  	Set_NB32_DCT(dev, dct, 0x94, DramConfigHi);
  
-@@ -6582,6 +6618,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
+@@ -6593,6 +6629,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
  		dword |= 0x0000000f;
  		Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword);
  	}
@@ -386,7 +388,7 @@ index e327d38..486b16c 100644
  u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct);
  void mct_Wait(u32 cycles);
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 41b7244..bc9ac4b 100644
+index 36e9858..c70fa6d 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -1588,6 +1588,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
@@ -399,7 +401,7 @@ index 41b7244..bc9ac4b 100644
  		dword |= (0x1 << 13);
 @@ -1627,6 +1628,9 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
  				rx_en_offset = (initial_phy_phase_delay[lane] + 0x10) % 0x40;
- 	
+ 
  				/* 2.10.5.8.3 (4) */
 +#if DQS_TRAIN_DEBUG > 0
 +				printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 Receiver %d lane %d initial phy delay %04x: iterating from %04x to %04x\n", Receiver, lane, initial_phy_phase_delay[lane], rx_en_offset, 0x3ff);
@@ -904,10 +906,10 @@ index 9ccf77e..09a5f68 100644
  		 * must be done for each chip select pair */
  		if (pDCTstat->Status & (1 << SB_Registered))
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index abb5321..3af3eb2 100644
+index 981f467..707e6a9 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-@@ -1147,8 +1147,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
+@@ -1146,8 +1146,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
  	uint8_t dimm;
  	uint8_t rank;
  	uint8_t lane;
@@ -918,7 +920,7 @@ index abb5321..3af3eb2 100644
  	uint16_t current_total_delay[MAX_BYTE_LANES];
  	uint16_t dqs_ret_pass1_total_delay[MAX_BYTE_LANES];
  	uint16_t rank0_current_total_delay[MAX_BYTE_LANES];
-@@ -1164,6 +1166,11 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
+@@ -1163,6 +1165,11 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
  	print_debug_dqs("\nTrainRcvEn: Node", pDCTstat->Node_ID, 0);
  	print_debug_dqs("TrainRcvEn: Pass", Pass, 0);
  
@@ -930,7 +932,7 @@ index abb5321..3af3eb2 100644
  	dev = pDCTstat->dev_dct;
  	index_reg = 0x98;
  	ch_start = 0;
-@@ -1246,132 +1253,148 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
+@@ -1245,132 +1252,148 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
  			else
  				_2Ranks = 0;
  			for (rank = 0; rank < (_2Ranks + 1); rank++) {
@@ -950,20 +952,6 @@ index abb5321..3af3eb2 100644
 -				 * Retrieve gross and fine timing fields from write DQS registers
 -				 */
 -				read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg);
--
--				/* 2.10.5.8.2.1
--				 * Generate the DQS Receiver Enable Training Seed Values
--				 */
--				if (Pass == FirstPass) {
--					initial_seed = fam15_receiver_enable_training_seed(pDCTstat, Channel, dimm, rank, package_type);
--
--					/* Adjust seed for the minimum platform supported frequency */
--					initial_seed = (uint16_t) (((((uint64_t) initial_seed) *
--						fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100)));
--
--					for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
--						uint16_t wl_pass1_delay;
--						wl_pass1_delay = current_total_delay[lane];
 +				for (nibble = 0; nibble < (train_both_nibbles + 1); nibble++) {
 +					/* 2.10.5.8.2 (1)
 +					 * Specify the target DIMM and nibble to be trained
@@ -980,6 +968,31 @@ index abb5321..3af3eb2 100644
 +					 */
 +					read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg);
  
+-				/* 2.10.5.8.2.1
+-				 * Generate the DQS Receiver Enable Training Seed Values
+-				 */
+-				if (Pass == FirstPass) {
+-					initial_seed = fam15_receiver_enable_training_seed(pDCTstat, Channel, dimm, rank, package_type);
++					/* 2.10.5.8.2.1
++					 * Generate the DQS Receiver Enable Training Seed Values
++					 */
++					if (Pass == FirstPass) {
++						initial_seed = fam15_receiver_enable_training_seed(pDCTstat, Channel, dimm, rank, package_type);
+ 
+-					/* Adjust seed for the minimum platform supported frequency */
+-					initial_seed = (uint16_t) (((((uint64_t) initial_seed) *
+-						fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100)));
++						/* Adjust seed for the minimum platform supported frequency */
++						initial_seed = (uint16_t) (((((uint64_t) initial_seed) *
++							fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100)));
+ 
+-					for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
+-						uint16_t wl_pass1_delay;
+-						wl_pass1_delay = current_total_delay[lane];
++						for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
++							uint16_t wl_pass1_delay;
++							wl_pass1_delay = current_total_delay[lane];
+ 
 -						seed[lane] = initial_seed + wl_pass1_delay;
 -					}
 -				} else {
@@ -998,20 +1011,6 @@ index abb5321..3af3eb2 100644
 -						* Load reduced DIMM support unimplemented
 -						*/
 -						register_delay = 0x0;
-+					/* 2.10.5.8.2.1
-+					 * Generate the DQS Receiver Enable Training Seed Values
-+					 */
-+					if (Pass == FirstPass) {
-+						initial_seed = fam15_receiver_enable_training_seed(pDCTstat, Channel, dimm, rank, package_type);
-+	
-+						/* Adjust seed for the minimum platform supported frequency */
-+						initial_seed = (uint16_t) (((((uint64_t) initial_seed) *
-+							fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100)));
-+	
-+						for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
-+							uint16_t wl_pass1_delay;
-+							wl_pass1_delay = current_total_delay[lane];
-+	
 +							seed[lane] = initial_seed + wl_pass1_delay;
 +						}
  					} else {
@@ -1019,7 +1018,7 @@ index abb5321..3af3eb2 100644
 +						uint8_t addr_prelaunch = 0;		/* TODO: Fetch the correct value from RC2[0] */
 +						uint16_t register_delay;
 +						int16_t seed_prescaling;
-+	
++
 +						memcpy(current_total_delay, dqs_ret_pass1_total_delay, sizeof(current_total_delay));
 +						if ((pDCTstat->Status & (1 << SB_Registered))) {
 +							if (addr_prelaunch)
@@ -1034,7 +1033,7 @@ index abb5321..3af3eb2 100644
 +						} else {
 +							register_delay = 0x0;
 +						}
-+	
++
 +						for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
 +							seed_prescaling = current_total_delay[lane] - register_delay - 0x20;
 +							seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100)));
@@ -1044,30 +1043,20 @@ index abb5321..3af3eb2 100644
  					for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
 -						seed_prescaling = current_total_delay[lane] - register_delay - 0x20;
 -						seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100)));
+-					}
+-				}
 +						seed_gross[lane] = (seed[lane] >> 5) & 0x1f;
 +						seed_fine[lane] = seed[lane] & 0x1f;
-+	
+ 
+-				for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
+-					seed_gross[lane] = (seed[lane] >> 5) & 0x1f;
+-					seed_fine[lane] = seed[lane] & 0x1f;
 +						/*if (seed_gross[lane] == 0)
 +							seed_pre_gross[lane] = 0;
 +						else */if (seed_gross[lane] & 0x1)
 +							seed_pre_gross[lane] = 1;
 +						else
 +							seed_pre_gross[lane] = 2;
-+	
-+						/* Calculate phase recovery delays */
-+						phase_recovery_delays[lane] = ((seed_pre_gross[lane] & 0x1f) << 5) | (seed_fine[lane] & 0x1f);
-+	
-+						/* Set the gross delay.
-+						* NOTE: While the BKDG states to only program DqsRcvEnGrossDelay, this appears
-+						* to have been a misprint as DqsRcvEnFineDelay should be set to zero as well.
-+						*/
-+						current_total_delay[lane] = ((seed_gross[lane] & 0x1f) << 5);
- 					}
--				}
--
--				for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
--					seed_gross[lane] = (seed[lane] >> 5) & 0x1f;
--					seed_fine[lane] = seed[lane] & 0x1f;
  
 -					/*if (seed_gross[lane] == 0)
 -						seed_pre_gross[lane] = 0;
@@ -1075,10 +1064,18 @@ index abb5321..3af3eb2 100644
 -						seed_pre_gross[lane] = 1;
 -					else
 -						seed_pre_gross[lane] = 2;
--
++						/* Calculate phase recovery delays */
++						phase_recovery_delays[lane] = ((seed_pre_gross[lane] & 0x1f) << 5) | (seed_fine[lane] & 0x1f);
+ 
 -					/* Calculate phase recovery delays */
 -					phase_recovery_delays[lane] = ((seed_pre_gross[lane] & 0x1f) << 5) | (seed_fine[lane] & 0x1f);
--
++						/* Set the gross delay.
++						* NOTE: While the BKDG states to only program DqsRcvEnGrossDelay, this appears
++						* to have been a misprint as DqsRcvEnFineDelay should be set to zero as well.
++						*/
++						current_total_delay[lane] = ((seed_gross[lane] & 0x1f) << 5);
++					}
+ 
 -					/* Set the gross delay.
 -					 * NOTE: While the BKDG states to only program DqsRcvEnGrossDelay, this appears
 -					 * to have been a misprint as DqsRcvEnFineDelay should be set to zero as well.
@@ -1093,39 +1090,37 @@ index abb5321..3af3eb2 100644
 -				 * Program PhRecFineDly and PhRecGrossDly
 -				 */
 -				write_dram_phase_recovery_control_registers(phase_recovery_delays, dev, Channel, dimm, index_reg);
--
--				/* 2.10.5.8.2 (2) / 2.10.5.8.2.1 (7)
--				 * Program the DQS Receiver Enable delay values for each lane
--				 */
--				write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg);
 +					/* 2.10.5.8.2 (2) / 2.10.5.8.2.1 (7)
 +					 * Program the DQS Receiver Enable delay values for each lane
 +					 */
 +					write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg);
- 	
--				/* 2.10.5.8.2 (3)
--				 * Program DqsRcvTrEn = 1
--				 */
--				dword = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008);
--				dword |= (0x1 << 13);
--				Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008, dword);
--
--				/* 2.10.5.8.2 (4)
--				 * Issue 192 read requests to the target rank
+ 
+-				/* 2.10.5.8.2 (2) / 2.10.5.8.2.1 (7)
+-				 * Program the DQS Receiver Enable delay values for each lane
 -				 */
--				generate_dram_receiver_enable_training_pattern_fam15(pMCTstat, pDCTstat, Channel, Receiver + (rank & 0x1));
+-				write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg);
 +					/* 2.10.5.8.2 (3)
 +					 * Program DqsRcvTrEn = 1
 +					 */
 +					dword = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008);
 +					dword |= (0x1 << 13);
 +					Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008, dword);
-+	
+ 
+-				/* 2.10.5.8.2 (3)
+-				 * Program DqsRcvTrEn = 1
+-				 */
+-				dword = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008);
+-				dword |= (0x1 << 13);
+-				Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008, dword);
 +					/* 2.10.5.8.2 (4)
 +					 * Issue 192 read requests to the target rank
 +					 */
 +					generate_dram_receiver_enable_training_pattern_fam15(pMCTstat, pDCTstat, Channel, Receiver + (rank & 0x1));
-+	
+ 
+-				/* 2.10.5.8.2 (4)
+-				 * Issue 192 read requests to the target rank
+-				 */
+-				generate_dram_receiver_enable_training_pattern_fam15(pMCTstat, pDCTstat, Channel, Receiver + (rank & 0x1));
 +					/* 2.10.5.8.2 (5)
 +					 * Program DqsRcvTrEn = 0
 +					 */
@@ -1191,7 +1186,7 @@ index abb5321..3af3eb2 100644
  
  				if (rank == 0) {
  					/* Back up the Rank 0 delays for later use */
-@@ -1396,7 +1419,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
+@@ -1395,7 +1418,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
  
  #if DQS_TRAIN_DEBUG > 0
  			for (lane = 0; lane < 8; lane++)
@@ -1200,7 +1195,7 @@ index abb5321..3af3eb2 100644
  #endif
  		}
  	}
-@@ -1816,15 +1839,23 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
+@@ -1815,15 +1838,23 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
  }
  
  void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
@@ -1226,7 +1221,7 @@ index abb5321..3af3eb2 100644
  		pDCTstat = pDCTstatA + Node;
  		if (!pDCTstat->NodePresent)
  			continue;
-@@ -1848,6 +1879,8 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
+@@ -1847,6 +1878,8 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
  					if (!pDCTstat->DIMMValidDCT[dct])
  						continue;
  
@@ -1235,7 +1230,7 @@ index abb5321..3af3eb2 100644
  					/* Back up D18F2x9C_x0000_0004_dct[1:0] */
  					datc_backup = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000004);
  
-@@ -1986,6 +2019,8 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
+@@ -1985,6 +2018,8 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
  
  					/* Restore D18F2x9C_x0000_0004_dct[1:0] */
  					Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000004, datc_backup);
@@ -1244,7 +1239,7 @@ index abb5321..3af3eb2 100644
  				}
  			} else {
  				fenceDynTraining_D(pMCTstat, pDCTstat, 0);
-@@ -1998,7 +2033,7 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
+@@ -1997,7 +2032,7 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
  }
  
  static uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat,
@@ -1306,7 +1301,7 @@ index 6b63ba0..3153e46 100644
  }
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index fb3b3d8..3391dcf 100644
+index e5e4031..73b231e 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 @@ -35,9 +35,9 @@ u32 swapBankBits(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t MRSValue);
@@ -1710,10 +1705,10 @@ index fb3b3d8..3391dcf 100644
 +					pDCTData->WLSeedGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
 +					pDCTData->WLSeedFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
 +					pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_PreGross;
-+	
++
 +					pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_PreGross;
 +					pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
-+	
++
 +					printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f));
 +				}
 +			} else {
@@ -1748,7 +1743,7 @@ index fb3b3d8..3391dcf 100644
 -				} else {
 -					RegisterDelay = 0;
 +						Seed_Gross = 2;
-+	
++
 +					/* The BKDG-recommended algorithm causes problems with registered DIMMs on some systems
 +					* due to the long register delays causing premature total delay wrap-around.
 +					* Attempt to work around this...
@@ -1757,10 +1752,10 @@ index fb3b3d8..3391dcf 100644
 +					SeedTotal += RegisterDelay;
 +					Seed_Gross = SeedTotal / 32;
 +					Seed_Fine = SeedTotal & 0x1f;
-+	
++
 +					pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
 +					pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
-+	
++
 +					printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f));
  				}
 -				SeedTotalPreScaling = ((pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) |
@@ -1777,7 +1772,8 @@ index fb3b3d8..3391dcf 100644
 -					Seed_Gross = 1;
 -				else
 -					Seed_Gross = 2;
--
++			}
+ 
 -				/* The BKDG-recommended algorithm causes problems with registered DIMMs on some systems
 -				 * due to the long register delays causing premature total delay wrap-around.
 -				 * Attempt to work around this...
@@ -1786,10 +1782,6 @@ index fb3b3d8..3391dcf 100644
 -				SeedTotal += RegisterDelay;
 -				Seed_Gross = SeedTotal / 32;
 -				Seed_Fine = SeedTotal & 0x1f;
-+			}
- 
--				pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
--				pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
 +			/* Save initial seeds for upper nibble pass */
 +			for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
 +				pDCTData->WLSeedPreGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane];
@@ -1803,18 +1795,20 @@ index fb3b3d8..3391dcf 100644
 +					pDCTData->WLSeedGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane];
 +					pDCTData->WLSeedFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[MAX_BYTE_LANES*dimm+ByteLane];
 +					pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane];
-+	
+ 
+-				pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
+-				pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
 +					pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane];
 +					pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[MAX_BYTE_LANES*dimm+ByteLane];
-+
+ 
+-				printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f));
 +					printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f));
 +				}
 +			} else {
 +				for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
 +					pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane];
 +					pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[MAX_BYTE_LANES*dimm+ByteLane];
- 
--				printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f));
++
 +					printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f));
 +				}
  			}
@@ -1889,5 +1883,5 @@ index 12e7c4a..3337c14 100644
  								/* per byte Lane Per Logical DIMM*/
  	u8 WLFineDelayFirstPass[MAX_BYTE_LANES*MAX_LDIMMS];	/* First-Pass Write Levelization Fine Delay */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0087-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch b/resources/libreboot/patch/kgpe-d16/0087-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch
new file mode 100644
index 0000000..2037f44
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0087-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch
@@ -0,0 +1,1931 @@
+From 0489e5c40921fd2ec7c7b5adb7ae69d180af8f9c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Thu, 30 Jul 2015 14:07:15 -0500
+Subject: [PATCH 087/139] cpu/amd/family_10h-family_15h: Fix Family 15h
+ multiple package support
+
+TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
+and several different RDIMM configurations.
+
+Change-Id: I171197c90f72d3496a385465937b7666cbf7e308
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/car/cache_as_ram.inc                   |  17 ++-
+ src/cpu/amd/family_10h-family_15h/defaults.h       | 101 +++++++++++++--
+ src/cpu/amd/family_10h-family_15h/fidvid.c         |  81 ++++++------
+ src/cpu/amd/family_10h-family_15h/init_cpus.c      |  66 +++++++++-
+ src/cpu/amd/quadcore/quadcore.c                    |  19 +--
+ src/cpu/amd/quadcore/quadcore_id.c                 |   1 -
+ src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
+ src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
+ src/mainboard/amd/dbm690t/romstage.c               |   2 +-
+ src/mainboard/amd/mahogany/romstage.c              |   2 +-
+ src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
+ src/mainboard/amd/pistachio/romstage.c             |   2 +-
+ src/mainboard/amd/serengeti_cheetah/romstage.c     |   2 +-
+ .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
+ src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
+ src/mainboard/arima/hdama/romstage.c               |   2 +-
+ src/mainboard/asrock/939a785gmh/romstage.c         |   2 +-
+ src/mainboard/asus/a8n_e/romstage.c                |   2 +-
+ src/mainboard/asus/a8v-e_deluxe/romstage.c         |   2 +-
+ src/mainboard/asus/a8v-e_se/romstage.c             |   2 +-
+ src/mainboard/asus/k8v-x/romstage.c                |   2 +-
+ src/mainboard/asus/kfsn4-dre/romstage.c            |   2 +-
+ src/mainboard/asus/kgpe-d16/romstage.c             |  46 +++++--
+ src/mainboard/asus/m2n-e/romstage.c                |   2 +-
+ src/mainboard/asus/m2v-mx_se/romstage.c            |   2 +-
+ src/mainboard/asus/m2v/romstage.c                  |   2 +-
+ src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
+ src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
+ src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
+ src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
+ src/mainboard/broadcom/blast/romstage.c            |   2 +-
+ src/mainboard/gigabyte/ga_2761gxdk/romstage.c      |   2 +-
+ src/mainboard/gigabyte/m57sli/romstage.c           |   2 +-
+ src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
+ src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
+ src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
+ src/mainboard/hp/dl145_g1/romstage.c               |   2 +-
+ src/mainboard/hp/dl145_g3/romstage.c               |   2 +-
+ src/mainboard/hp/dl165_g6_fam10/romstage.c         |   2 +-
+ src/mainboard/ibm/e325/romstage.c                  |   2 +-
+ src/mainboard/ibm/e326/romstage.c                  |   2 +-
+ src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
+ src/mainboard/iwill/dk8_htx/romstage.c             |   2 +-
+ src/mainboard/iwill/dk8s2/romstage.c               |   2 +-
+ src/mainboard/iwill/dk8x/romstage.c                |   2 +-
+ src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
+ src/mainboard/kontron/kt690/romstage.c             |   2 +-
+ src/mainboard/msi/ms7135/romstage.c                |   2 +-
+ src/mainboard/msi/ms7260/romstage.c                |   2 +-
+ src/mainboard/msi/ms9185/romstage.c                |   2 +-
+ src/mainboard/msi/ms9282/romstage.c                |   2 +-
+ src/mainboard/msi/ms9652_fam10/romstage.c          |   2 +-
+ src/mainboard/newisys/khepri/romstage.c            |   2 +-
+ src/mainboard/nvidia/l1_2pvv/romstage.c            |   2 +-
+ src/mainboard/siemens/sitemp_g1p1/romstage.c       |   2 +-
+ src/mainboard/sunw/ultra40/romstage.c              |   2 +-
+ src/mainboard/supermicro/h8dme/romstage.c          |   2 +-
+ src/mainboard/supermicro/h8dmr/romstage.c          |   2 +-
+ src/mainboard/supermicro/h8dmr_fam10/romstage.c    |   2 +-
+ src/mainboard/supermicro/h8qme_fam10/romstage.c    |   2 +-
+ src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
+ src/mainboard/technexion/tim5690/romstage.c        |   2 +-
+ src/mainboard/technexion/tim8690/romstage.c        |   2 +-
+ src/mainboard/tyan/s2850/romstage.c                |   2 +-
+ src/mainboard/tyan/s2875/romstage.c                |   2 +-
+ src/mainboard/tyan/s2880/romstage.c                |   2 +-
+ src/mainboard/tyan/s2881/romstage.c                |   2 +-
+ src/mainboard/tyan/s2882/romstage.c                |   2 +-
+ src/mainboard/tyan/s2885/romstage.c                |   2 +-
+ src/mainboard/tyan/s2891/romstage.c                |   2 +-
+ src/mainboard/tyan/s2892/romstage.c                |   2 +-
+ src/mainboard/tyan/s2895/romstage.c                |   2 +-
+ src/mainboard/tyan/s2912/romstage.c                |   2 +-
+ src/mainboard/tyan/s2912_fam10/romstage.c          |   2 +-
+ src/mainboard/tyan/s4880/romstage.c                |   2 +-
+ src/mainboard/tyan/s4882/romstage.c                |   2 +-
+ src/mainboard/winent/mb6047/romstage.c             |   2 +-
+ src/northbridge/amd/amdht/h3finit.c                |  57 ++++++++-
+ src/northbridge/amd/amdht/h3ncmn.c                 |  30 ++++-
+ src/northbridge/amd/amdht/ht_wrapper.c             | 141 +++++++++++++++++++--
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c        |   1 +
+ 81 files changed, 528 insertions(+), 172 deletions(-)
+
+diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
+index 5db9224..6bfb0e6 100644
+--- a/src/cpu/amd/car/cache_as_ram.inc
++++ b/src/cpu/amd/car/cache_as_ram.inc
+@@ -525,8 +525,23 @@ CAR_FAM10_ap:
+ 	/* Fam10h NB config bit 54 was not set */
+ 	rolb	%cl, %bl
+ roll_cfg:
++	jmp_if_not_fam15h(ap_apicid_ready)
++	cmp	$0x5, %ecx
++	jne	ap_apicid_ready
+ 
+-	/* Calculate stack pointer. */
++	/* This is a multi-node CPU
++	 * Adjust the maximum APIC ID to a more reasonable value
++	 * given that no 32-core Family 15h processors exist
++	 */
++	movl	%ebx, %ecx
++	and	$0x0f, %ecx		/* Get lower 4 bits of CPU number */
++	and	$0x60, %ebx		/* Get node ID */
++	shrl	$0x1, %ebx		/* Shift node ID part of APIC ID down by 1 */
++	or	%ecx, %ebx		/* Recombine node ID and CPU number */
++
++ap_apicid_ready:
++
++	/* Calculate stack pointer using adjusted APIC ID stored in ebx */
+ 	movl	$CacheSizeAPStack, %eax
+ 	mull	%ebx
+ 	movl	$(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
+index 24f87ba..513d169 100644
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
+@@ -244,18 +244,50 @@ static const struct {
+ 	{ 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
+ 	  AMD_PTYPE_SVR, 0x00200000, 0x00600000 },	/* [22:21] DsNpReqLmt0 = 01b */
+ 
+-	{ 0, 0x84, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
++	{ 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+ 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+ 
+-	{ 0, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
++	{ 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+ 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+ 
+-	{ 0, 0xC4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
++	{ 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+ 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+ 
+-	{ 0, 0xE4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
++	{ 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+ 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
+ 
++	/* FIXME
++	 * Non-C32 packages only
++	 */
++	{ 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	/* FIXME
++	 * C32 package only
++	 */
++#if 0
++	{ 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++
++	{ 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
++	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
++#endif
++
+ 	/* Link Global Retry Control Register */
+ 	{ 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
+ 	  0x00073900, 0x00073F00 },
+@@ -614,38 +646,79 @@ static const struct {
+ 	{ 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+ 	  0x00004400, 0x00006400 },	/* HT_PHY_DLL_REG */
+ 
+-	{ 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
++					   completeness */
++
++	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
++					   completeness */
++
++	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	  0x0000006D, 0x000000FF },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
++
++	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
++	  0x0000006D, 0x000000FF }, 	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
++
++	/* Link Phy Receiver Loop Filter Registers */
++	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
++					   [21:14] LfcMin = 10h */
++
++	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
++					   [21:14] LfcMin = 10h */
++
++	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
++					   [21:14] LfcMin = 08h */
++
++	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
++					   [21:14] LfcMin = 08h */
++
++	{ 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
++					  [20:16] RttIndex = 04h */
++
++/* FIXME
++ * Causes lockups for some reason when more than one package is installed
++ * Debug and reactivate!
++ */
++// #if 0
++	{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+ 	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
+ 					   completeness */
+ 
+-	{ 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+ 	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
+ 					   completeness */
+ 
+-	{ 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
+ 	  0x0000006D, 0x000000FF },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
+ 
+-	{ 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
++	{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
+ 	  0x0000006D, 0x000000FF }, 	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
+ 
+ 	/* Link Phy Receiver Loop Filter Registers */
+-	{ 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+ 	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
+ 					   [21:14] LfcMin = 10h */
+ 
+-	{ 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	{ 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
+ 	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
+ 					   [21:14] LfcMin = 10h */
+ 
+-	{ 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
+ 	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
+ 					   [21:14] LfcMin = 08h */
+ 
+-	{ 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
++	{ 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
+ 	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
+ 					   [21:14] LfcMin = 08h */
+ 
+-	{ 0xC0, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
++	{ 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+ 	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
+-								   [20:16] RttIndex = 04h */
++					  [20:16] RttIndex = 04h */
++// #endif
+ };
+diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
+index 0e870e3..471456a 100644
+--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
+@@ -633,44 +633,45 @@ static void prep_fid_change(void)
+ }
+ 
+ static void waitCurrentPstate(u32 target_pstate) {
+-  msr_t initial_msr = rdmsr(TSC_MSR);
+-  msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
+-  msr_t tsc_msr;
+-  u8 timedout ;
+-
+-  /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
+-   * P1 that is a copy of P0, therefore has the same NB DID but the
+-   * TSC will count twice per tick, so we have to wait for twice the
+-   * count to achieve the desired timeout. But I'm likely to
+-   * misunderstand this...
+-   */
+-  u32 corrected_timeout = (    (pstate_msr.lo==1)
+-			    && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
+-                          WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT  ;
+-  msr_t timeout;
+-
+-  timeout.lo = initial_msr.lo + corrected_timeout ;
+-  timeout.hi = initial_msr.hi;
+-  if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
+-     timeout.hi++;
+-  }
+-
+-  // assuming TSC ticks at 1.25 ns per tick (800 MHz)
+-  do {
+-      pstate_msr = rdmsr(CUR_PSTATE_MSR);
+-      tsc_msr = rdmsr(TSC_MSR);
+-      timedout = (tsc_msr.hi > timeout.hi)
+-        	|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
+-  } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
+-
+-  if (pstate_msr.lo != target_pstate) {
+-    msr_t limit_msr = rdmsr(0xc0010061);
+-    printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo);
+-
+-    do { // should we just go on instead ?
+-      pstate_msr = rdmsr(CUR_PSTATE_MSR);
+-    } while ( pstate_msr.lo != target_pstate  ) ;
+-  }
++	msr_t initial_msr = rdmsr(TSC_MSR);
++	msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
++	msr_t tsc_msr;
++	u8 timedout ;
++
++	/* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
++	* P1 that is a copy of P0, therefore has the same NB DID but the
++	* TSC will count twice per tick, so we have to wait for twice the
++	* count to achieve the desired timeout. But I'm likely to
++	* misunderstand this...
++	*/
++	u32 corrected_timeout = ((pstate_msr.lo==1)
++				&& (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
++				WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT;
++	msr_t timeout;
++
++	timeout.lo = initial_msr.lo + corrected_timeout ;
++	timeout.hi = initial_msr.hi;
++	if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
++		timeout.hi++;
++	}
++
++	// assuming TSC ticks at 1.25 ns per tick (800 MHz)
++	do {
++		pstate_msr = rdmsr(CUR_PSTATE_MSR);
++		tsc_msr = rdmsr(TSC_MSR);
++		timedout = (tsc_msr.hi > timeout.hi)
++			|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
++	} while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
++
++	if (pstate_msr.lo != target_pstate) {
++		msr_t limit_msr = rdmsr(0xc0010061);
++		printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n",
++			cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo);
++
++		do { // should we just go on instead ?
++			pstate_msr = rdmsr(CUR_PSTATE_MSR);
++		} while ( pstate_msr.lo != target_pstate  ) ;
++	}
+ }
+ 
+ static void set_pstate(u32 nonBoostedPState) {
+@@ -1063,13 +1064,13 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
+ 	   APs and BSP */
+ 	ap_apicidx.num = 0;
+ 
+-	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
++	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, -1, store_ap_apicid, &ap_apicidx);
+ 
+ 	for (i = 0; i < ap_apicidx.num; i++) {
+ 		init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
+ 	}
+ #else
+-	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
++	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv);
+ #endif
+ 
+ 	print_debug_fv("common_fid = ", fv.common_fid);
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 0044dc6..986c024 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+@@ -59,6 +59,8 @@ static void set_EnableCf8ExtCfg(void)
+ static void set_EnableCf8ExtCfg(void) { }
+ #endif
+ 
++// #define DEBUG_HT_SETUP 1
++// #define FAM10_AP_NODE_SEQUENTIAL_START 1
+ 
+ typedef void (*process_ap_t) (u32 apicid, void *gp);
+ 
+@@ -143,8 +145,8 @@ uint32_t get_boot_apic_id(uint8_t node, uint32_t core) {
+ //core range = 1 : core 0 only
+ //core range = 2 : cores other than core0
+ 
+-static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
+-			void *gp)
++static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
++			process_ap_t process_ap, void *gp)
+ {
+ 	// here assume the OS don't change our apicid
+ 	u32 ap_apicid;
+@@ -165,6 +167,9 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
+ 	}
+ 
+ 	for (i = 0; i < nodes; i++) {
++		if ((node >= 0) && (i != node))
++			continue;
++
+ 		cores_found = get_core_num_in_bsp(i);
+ 
+ 		u32 jstart, jend;
+@@ -280,7 +285,7 @@ void wait_all_other_cores_started(u32 bsp_apicid)
+ {
+ 	// all aps other than core0
+ 	printk(BIOS_DEBUG, "started ap apicid: ");
+-	for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0);
++	for_each_ap(bsp_apicid, 2, -1, wait_ap_started, (void *)0);
+ 	printk(BIOS_DEBUG, "\n");
+ }
+ 
+@@ -373,8 +378,10 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
+ 	/* NB_CFG MSR is shared between cores, so we need make sure
+ 	   core0 is done at first --- use wait_all_core0_started  */
+ 	if (id.coreid == 0) {
+-		set_apicid_cpuid_lo();	/* only set it on core0 */
+-		set_EnableCf8ExtCfg();	/* only set it on core0 */
++		/* Set InitApicIdCpuIdLo / EnableCf8ExtCfg on core0 only */
++		if (!is_fam15h())
++			set_apicid_cpuid_lo();
++		set_EnableCf8ExtCfg();
+ #if CONFIG_ENABLE_APIC_EXT_ID
+ 		enable_apic_ext_id(id.nodeid);
+ #endif
+@@ -427,6 +434,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
+ 	}
+ 	// Mark the core as started.
+ 	lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED);
++	printk(BIOS_DEBUG, "CPU APICID %02x start flag set\n", apicid);
+ 
+ 	if (apicid != bsp_apicid) {
+ 		/* Setup each AP's cores MSRs.
+@@ -588,6 +596,34 @@ static void setup_remote_node(u8 node)
+ }
+ #endif				/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
+ 
++//it is running on core0 of node0
++static void start_other_cores(uint32_t bsp_apicid)
++{
++	u32 nodes;
++	u32 nodeid;
++
++	// disable multi_core
++	if (read_option(multi_core, 0) != 0)  {
++		printk(BIOS_DEBUG, "Skip additional core init\n");
++		return;
++	}
++
++	nodes = get_nodes();
++
++	for (nodeid = 0; nodeid < nodes; nodeid++) {
++		u32 cores = get_core_num_in_bsp(nodeid);
++		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1\n", nodeid, cores);
++		if (cores > 0) {
++			real_start_other_core(nodeid, cores);
++#ifdef FAM10_AP_NODE_SEQUENTIAL_START
++			printk(BIOS_DEBUG, "waiting for core start on node %d...\n", nodeid);
++			for_each_ap(bsp_apicid, 2, nodeid, wait_ap_started, (void *)0);
++			printk(BIOS_DEBUG, "...started\n");
++#endif
++		}
++	}
++}
++
+ static void AMD_Errata281(u8 node, uint64_t revision, u32 platform)
+ {
+ 	/* Workaround for Transaction Scheduling Conflict in
+@@ -847,6 +883,10 @@ static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry)
+ 
+ 	phyBase = ((u32) link << 3) | 0x180;
+ 
++	/* Determine if link is connected and abort if not */
++	if (!(pci_read_config32(NODE_PCI(node, 0), 0x98 + (link * 0x20)) & 0x1))
++		return;
++
+ 	/* Get the portal control register's initial value
+ 	 * and update it to access the desired phy register
+ 	 */
+@@ -1008,10 +1048,11 @@ static void cpuSetAMDPCI(u8 node)
+ 	 * Hypertransport initialization has taken place.  Also note
+ 	 * that it is run for the first core on each node
+ 	 */
+-	u8 i, j;
++	uint8_t i;
++	uint8_t j;
+ 	u32 platform;
+ 	u32 val;
+-	u8 offset;
++	uint8_t offset;
+ 	uint32_t dword;
+ 	uint64_t revision;
+ 
+@@ -1038,6 +1079,17 @@ static void cpuSetAMDPCI(u8 node)
+ 		}
+ 	}
+ 
++#ifdef DEBUG_HT_SETUP
++	/* Dump link settings */
++	for (i = 0; i < 4; i++) {
++		for (j = 0; j < 4; j++) {
++			printk(BIOS_DEBUG, "Node %d link %d: type register: %08x control register: %08x extended control sublink 0: %08x 1: %08x\n", i, j,
++				pci_read_config32(NODE_PCI(i, 0), 0x98 + (j * 0x20)), pci_read_config32(NODE_PCI(i, 0), 0x84 + (j * 0x20)),
++				pci_read_config32(NODE_PCI(i, 0), 0x170 + (j * 0x4)), pci_read_config32(NODE_PCI(i, 0), 0x180 + (j * 0x4)));
++		}
++	}
++#endif
++
+ 	for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
+ 		if ((fam10_htphy_default[i].revision & revision) &&
+ 		    (fam10_htphy_default[i].platform & platform)) {
+diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
+index 8a9b5ed..9c31eac 100644
+--- a/src/cpu/amd/quadcore/quadcore.c
++++ b/src/cpu/amd/quadcore/quadcore.c
+@@ -31,21 +31,6 @@
+ uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
+ uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
+ 
+-static inline uint8_t is_fam15h(void)
+-{
+-	uint8_t fam15h = 0;
+-	uint32_t family;
+-
+-	family = cpuid_eax(0x80000001);
+-	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
+-
+-	if (family >= 0x6f)
+-		/* Family 15h or later */
+-		fam15h = 1;
+-
+-	return fam15h;
+-}
+-
+ static u32 get_core_num_in_bsp(u32 nodeid)
+ {
+ 	u32 dword;
+@@ -141,6 +126,7 @@ static void real_start_other_core(uint32_t nodeid, uint32_t cores)
+ 	}
+ }
+ 
++#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
+ //it is running on core0 of node0
+ static void start_other_cores(void)
+ {
+@@ -157,9 +143,10 @@ static void start_other_cores(void)
+ 
+ 	for (nodeid = 0; nodeid < nodes; nodeid++) {
+ 		u32 cores = get_core_num_in_bsp(nodeid);
+-		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1 \n", nodeid, cores);
++		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1\n", nodeid, cores);
+ 		if (cores > 0) {
+ 			real_start_other_core(nodeid, cores);
+ 		}
+ 	}
+ }
++#endif
+diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
+index c0537b3..1f5cbd8 100644
+--- a/src/cpu/amd/quadcore/quadcore_id.c
++++ b/src/cpu/amd/quadcore/quadcore_id.c
+@@ -108,7 +108,6 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
+ 			id.nodeid = apicid & 0x7;
+ 		}
+ 	}
+-
+ 	if (fam15h && dual_node) {
+ 		/* Coreboot expects each separate processor die to be on a different nodeid.
+ 		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
+diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
+index ab717fd..591faab 100644
+--- a/src/mainboard/advansus/a785e-i/romstage.c
++++ b/src/mainboard/advansus/a785e-i/romstage.c
+@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
+index 5e2cf82..95384ac 100644
+--- a/src/mainboard/amd/bimini_fam10/romstage.c
++++ b/src/mainboard/amd/bimini_fam10/romstage.c
+@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
+index 1f77afa..29edf30 100644
+--- a/src/mainboard/amd/dbm690t/romstage.c
++++ b/src/mainboard/amd/dbm690t/romstage.c
+@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
+index 542ee60..a52a69f 100644
+--- a/src/mainboard/amd/mahogany/romstage.c
++++ b/src/mainboard/amd/mahogany/romstage.c
+@@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
+index 025a8bb..aac6b4e 100644
+--- a/src/mainboard/amd/mahogany_fam10/romstage.c
++++ b/src/mainboard/amd/mahogany_fam10/romstage.c
+@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+  #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+  #endif
+diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
+index ca2edae..3ba011e 100644
+--- a/src/mainboard/amd/pistachio/romstage.c
++++ b/src/mainboard/amd/pistachio/romstage.c
+@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
+index 7da7925..20a34bf 100644
+--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
++++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
+@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	 */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+index 5063439..6d36575 100644
+--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
++++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+@@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+  #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+  #endif
+diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
+index e37bc08..c9a9928 100644
+--- a/src/mainboard/amd/tilapia_fam10/romstage.c
++++ b/src/mainboard/amd/tilapia_fam10/romstage.c
+@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c
+index d1e1c5f..0b6a833 100644
+--- a/src/mainboard/arima/hdama/romstage.c
++++ b/src/mainboard/arima/hdama/romstage.c
+@@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 	/* This is needed to be able to call udelay().  It could be moved to
+diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
+index 09c5b18..48862fd 100644
+--- a/src/mainboard/asrock/939a785gmh/romstage.c
++++ b/src/mainboard/asrock/939a785gmh/romstage.c
+@@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
+index d1485bf..5c89a83 100644
+--- a/src/mainboard/asus/a8n_e/romstage.c
++++ b/src/mainboard/asus/a8n_e/romstage.c
+@@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched. */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
+index dc1d6ff..cf713ee 100644
+--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
++++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
+@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched. */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 	init_timer();
+diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
+index 0531cd3..eba2acf 100644
+--- a/src/mainboard/asus/a8v-e_se/romstage.c
++++ b/src/mainboard/asus/a8v-e_se/romstage.c
+@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched. */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 	init_timer();
+diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
+index 45103fd..f1100dd 100644
+--- a/src/mainboard/asus/k8v-x/romstage.c
++++ b/src/mainboard/asus/k8v-x/romstage.c
+@@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched. */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 	init_timer();
+diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
+index dd5c7dc..1307e57 100644
+--- a/src/mainboard/asus/kfsn4-dre/romstage.c
++++ b/src/mainboard/asus/kfsn4-dre/romstage.c
+@@ -288,7 +288,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ 		/* Core0 on each node is configured. Now setup any additional cores. */
+ 		printk(BIOS_DEBUG, "start_other_cores()\n");
+-		start_other_cores();
++		start_other_cores(bsp_apicid);
+ 		post_code(0x37);
+ 		wait_all_other_cores_started(bsp_apicid);
+ 	}
+diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
+index 9ea7cec..3504126 100644
+--- a/src/mainboard/asus/kgpe-d16/romstage.c
++++ b/src/mainboard/asus/kgpe-d16/romstage.c
+@@ -97,7 +97,18 @@ static void switch_spd_mux(uint8_t channel)
+ 	pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
+ }
+ 
+-static const uint8_t spd_addr[] = {
++static const uint8_t spd_addr_fam15[] = {
++	// Socket 0 Node 0 ("Node 0")
++	RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
++	// Socket 0 Node 1 ("Node 1")
++	RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
++	// Socket 1 Node 0 ("Node 2")
++	RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
++	// Socket 1 Node 1 ("Node 3")
++	RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
++};
++
++static const uint8_t spd_addr_fam10[] = {
+ 	// Socket 0 Node 0 ("Node 0")
+ 	RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
+ 	// Socket 0 Node 1 ("Node 1")
+@@ -117,10 +128,10 @@ static void activate_spd_rom(const struct mem_controller *ctrl) {
+ 		switch_spd_mux(0x2);
+ 	} else if (ctrl->node_id == 1) {
+ 		printk(BIOS_DEBUG, "enable_spd_node1()\n");
+-		switch_spd_mux((sysinfo->nodes <= 2)?0x2:0x3);
++		switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3);
+ 	} else if (ctrl->node_id == 2) {
+ 		printk(BIOS_DEBUG, "enable_spd_node2()\n");
+-		switch_spd_mux((sysinfo->nodes <= 2)?0x3:0x2);
++		switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2);
+ 	} else if (ctrl->node_id == 3) {
+ 		printk(BIOS_DEBUG, "enable_spd_node3()\n");
+ 		switch_spd_mux(0x3);
+@@ -306,18 +317,25 @@ void initialize_romstage_console_lock(void)
+ 
+ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ {
++	uint32_t esp;
++	__asm__ volatile (
++		"movl %%esp, %0"
++		: "=r" (esp)
++		);
++
+ 	struct sys_info *sysinfo = &sysinfo_car;
+ 
+ 	uint32_t bsp_apicid = 0, val;
+ 	uint8_t byte;
+ 	msr_t msr;
+ 
+-	timestamp_init(timestamp_get());
+-	timestamp_add_now(TS_START_ROMSTAGE);
+-
+ 	int s3resume = acpi_is_wakeup_s3();
+ 
+ 	if (!cpu_init_detectedx && boot_cpu()) {
++		/* Initial timestamp */
++		timestamp_init(timestamp_get());
++		timestamp_add_now(TS_START_ROMSTAGE);
++
+ 		/* Initialize the printk spinlock */
+ 		initialize_romstage_console_lock();
+ 
+@@ -344,6 +362,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 		pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte);
+ 	}
+ 
++	printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp);
++
+ 	post_code(0x30);
+ 
+ 	if (bist == 0)
+@@ -397,7 +417,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ 		/* Core0 on each node is configured. Now setup any additional cores. */
+ 		printk(BIOS_DEBUG, "start_other_cores()\n");
+-		start_other_cores();
++		start_other_cores(bsp_apicid);
+ 		post_code(0x37);
+ 		wait_all_other_cores_started(bsp_apicid);
+ 	}
+@@ -455,7 +475,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	/* It's the time to set ctrl in sysinfo now; */
+ 	printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes);
+-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
++	if (is_fam15h())
++		fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15);
++	else
++		fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10);
+ 	post_code(0x3D);
+ 
+ #if 0
+@@ -527,5 +550,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+  */
+ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+ {
++	/* Force BUID to 0 */
++	static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF};
++	if ((node == 0) && (link == 1)) {	/* BSP SB link */
++		*List = swaplist;
++		return 1;
++	}
++
+ 	return 0;
+ }
+\ No newline at end of file
+diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
+index 306c124..351a411 100644
+--- a/src/mainboard/asus/m2n-e/romstage.c
++++ b/src/mainboard/asus/m2n-e/romstage.c
+@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * started, esp for two way system (there may be APIC ID conflicts in
+ 	 * that case).
+ 	 */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
+index 89e24a4..4364c6c 100644
+--- a/src/mainboard/asus/m2v-mx_se/romstage.c
++++ b/src/mainboard/asus/m2v-mx_se/romstage.c
+@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched. */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 	init_timer();
+diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
+index 8c99080..60cb1d4 100644
+--- a/src/mainboard/asus/m2v/romstage.c
++++ b/src/mainboard/asus/m2v/romstage.c
+@@ -247,7 +247,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched. */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 	init_timer();
+diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
+index 82b96bf..75894d8 100644
+--- a/src/mainboard/asus/m4a78-em/romstage.c
++++ b/src/mainboard/asus/m4a78-em/romstage.c
+@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+  #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+  #endif
+diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
+index 30975fa..f81cb95 100644
+--- a/src/mainboard/asus/m4a785-m/romstage.c
++++ b/src/mainboard/asus/m4a785-m/romstage.c
+@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+  #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+  #endif
+diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
+index 4edaba2..9914025 100644
+--- a/src/mainboard/asus/m5a88-v/romstage.c
++++ b/src/mainboard/asus/m5a88-v/romstage.c
+@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
+index 447012b..c57454d 100644
+--- a/src/mainboard/avalue/eax-785e/romstage.c
++++ b/src/mainboard/avalue/eax-785e/romstage.c
+@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
+index d7ba383..a7c0a84 100644
+--- a/src/mainboard/broadcom/blast/romstage.c
++++ b/src/mainboard/broadcom/blast/romstage.c
+@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+         wait_all_core0_started();
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+         wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+index 008a23f..8045164 100644
+--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
++++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+@@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+          * So here need to make sure last core0 is started, esp for two way system,
+          * (there may be apic id conflicts in that case)
+          */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
+index fe97e68..e1c2fe3 100644
+--- a/src/mainboard/gigabyte/m57sli/romstage.c
++++ b/src/mainboard/gigabyte/m57sli/romstage.c
+@@ -157,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+          * So here need to make sure last core0 is started, esp for two way system,
+          * (there may be apic id conflicts in that case)
+          */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
+index 444e59d..ae661e8 100644
+--- a/src/mainboard/gigabyte/ma785gm/romstage.c
++++ b/src/mainboard/gigabyte/ma785gm/romstage.c
+@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
+index 705d7c5..968aa8f 100644
+--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
++++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
+@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
+index 5d21801..7e18724 100644
+--- a/src/mainboard/gigabyte/ma78gm/romstage.c
++++ b/src/mainboard/gigabyte/ma78gm/romstage.c
+@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
+index 8b5b428..e2b215b 100644
+--- a/src/mainboard/hp/dl145_g1/romstage.c
++++ b/src/mainboard/hp/dl145_g1/romstage.c
+@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
+index d8e8a16..d6e72d2 100644
+--- a/src/mainboard/hp/dl145_g3/romstage.c
++++ b/src/mainboard/hp/dl145_g3/romstage.c
+@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	*/
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
+index 26c0bb9..e70d274 100644
+--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
++++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
+@@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
+index 48e7de8..960b46b 100644
+--- a/src/mainboard/ibm/e325/romstage.c
++++ b/src/mainboard/ibm/e325/romstage.c
+@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+         // automatically set that for you, but you might meet tight space
+         needs_reset |= ht_setup_chains_x();
+diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
+index a27a218..1b88035 100644
+--- a/src/mainboard/ibm/e326/romstage.c
++++ b/src/mainboard/ibm/e326/romstage.c
+@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+         // automatically set that for you, but you might meet tight space
+         needs_reset |= ht_setup_chains_x();
+diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
+index 321eea6..89cfe83 100644
+--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
++++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
+@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+  #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+  #endif
+diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
+index 9b5b38d..a1e45f0 100644
+--- a/src/mainboard/iwill/dk8_htx/romstage.c
++++ b/src/mainboard/iwill/dk8_htx/romstage.c
+@@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	 */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
+index 601c649..d140baf 100644
+--- a/src/mainboard/iwill/dk8s2/romstage.c
++++ b/src/mainboard/iwill/dk8s2/romstage.c
+@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	 */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
+index 273e9f1..bdac810 100644
+--- a/src/mainboard/iwill/dk8x/romstage.c
++++ b/src/mainboard/iwill/dk8x/romstage.c
+@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	 */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
+index 93dd2ce..6106b66 100644
+--- a/src/mainboard/jetway/pa78vm5/romstage.c
++++ b/src/mainboard/jetway/pa78vm5/romstage.c
+@@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+  #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+  #endif
+diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
+index d8db6aa..7210dae 100644
+--- a/src/mainboard/kontron/kt690/romstage.c
++++ b/src/mainboard/kontron/kt690/romstage.c
+@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
+index 68cddad..34dbb8a 100644
+--- a/src/mainboard/msi/ms7135/romstage.c
++++ b/src/mainboard/msi/ms7135/romstage.c
+@@ -139,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
+index 15f389a..be82fd0 100644
+--- a/src/mainboard/msi/ms7260/romstage.c
++++ b/src/mainboard/msi/ms7260/romstage.c
+@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * started, esp for two way system (there may be APIC ID conflicts in
+ 	 * that case).
+ 	 */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
+index 795a890..fc5cfd6 100644
+--- a/src/mainboard/msi/ms9185/romstage.c
++++ b/src/mainboard/msi/ms9185/romstage.c
+@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+         * So here need to make sure last core0 is started, esp for two way system,
+         * (there may be apic id conflicts in that case)
+         */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ //bx_a010-     wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
+index f5b75cc..05d8aee 100644
+--- a/src/mainboard/msi/ms9282/romstage.c
++++ b/src/mainboard/msi/ms9282/romstage.c
+@@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	//wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
+index 5da971f..f552db5 100644
+--- a/src/mainboard/msi/ms9652_fam10/romstage.c
++++ b/src/mainboard/msi/ms9652_fam10/romstage.c
+@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
+ 	wait_all_other_cores_started(bsp_apicid);
+diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
+index bf8a0a2..5174f32 100644
+--- a/src/mainboard/newisys/khepri/romstage.c
++++ b/src/mainboard/newisys/khepri/romstage.c
+@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+         wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
+index b5731c8..3725c04 100644
+--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
++++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
+@@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	 */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
+index 1b2501f..96cec72 100644
+--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
++++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
+@@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
+index ecb7fe7..13aa272 100644
+--- a/src/mainboard/sunw/ultra40/romstage.c
++++ b/src/mainboard/sunw/ultra40/romstage.c
+@@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+         wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
+index c10aba4..b9082a3 100644
+--- a/src/mainboard/supermicro/h8dme/romstage.c
++++ b/src/mainboard/supermicro/h8dme/romstage.c
+@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	 */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
+index 1e5582c..f31f586 100644
+--- a/src/mainboard/supermicro/h8dmr/romstage.c
++++ b/src/mainboard/supermicro/h8dmr/romstage.c
+@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+          * So here need to make sure last core0 is started, esp for two way system,
+          * (there may be apic id conflicts in that case)
+          */
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+index 1425546..333a213 100644
+--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+@@ -171,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
+index 4721eba..8caf615 100644
+--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
+@@ -238,7 +238,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
+index 858aca0..0e5adcd 100644
+--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
++++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
+@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
+index 27c0024..f3f3117 100644
+--- a/src/mainboard/technexion/tim5690/romstage.c
++++ b/src/mainboard/technexion/tim5690/romstage.c
+@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
+index 4830bf9..368eb0e 100644
+--- a/src/mainboard/technexion/tim8690/romstage.c
++++ b/src/mainboard/technexion/tim8690/romstage.c
+@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* It is said that we should start core1 after all core0 launched */
+ 	wait_all_core0_started();
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ #endif
+ 	wait_all_aps_started(bsp_apicid);
+ 
+diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
+index bb91a2a..9b5aff6 100644
+--- a/src/mainboard/tyan/s2850/romstage.c
++++ b/src/mainboard/tyan/s2850/romstage.c
+@@ -88,7 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+         needs_reset |= ht_setup_chains_x();
+ 
+diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
+index e63734e..41ae094 100644
+--- a/src/mainboard/tyan/s2875/romstage.c
++++ b/src/mainboard/tyan/s2875/romstage.c
+@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+         needs_reset |= ht_setup_chains_x();
+ 
+diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
+index dba58f2..c632b62 100644
+--- a/src/mainboard/tyan/s2880/romstage.c
++++ b/src/mainboard/tyan/s2880/romstage.c
+@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+         // automatically set that for you, but you might meet tight space
+         needs_reset |= ht_setup_chains_x();
+diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
+index b97ba18..c134f2d 100644
+--- a/src/mainboard/tyan/s2881/romstage.c
++++ b/src/mainboard/tyan/s2881/romstage.c
+@@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+         wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
+index dba58f2..c632b62 100644
+--- a/src/mainboard/tyan/s2882/romstage.c
++++ b/src/mainboard/tyan/s2882/romstage.c
+@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+         // automatically set that for you, but you might meet tight space
+         needs_reset |= ht_setup_chains_x();
+diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
+index fdf9606..81e3817 100644
+--- a/src/mainboard/tyan/s2885/romstage.c
++++ b/src/mainboard/tyan/s2885/romstage.c
+@@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+         wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
+index 93189f1..7d170b5 100644
+--- a/src/mainboard/tyan/s2891/romstage.c
++++ b/src/mainboard/tyan/s2891/romstage.c
+@@ -112,7 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
+index 881972d..460c909 100644
+--- a/src/mainboard/tyan/s2892/romstage.c
++++ b/src/mainboard/tyan/s2892/romstage.c
+@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
+index 086df63..5f3169a 100644
+--- a/src/mainboard/tyan/s2895/romstage.c
++++ b/src/mainboard/tyan/s2895/romstage.c
+@@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	wait_all_core0_started();
+ 
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ 
+ 	needs_reset |= ht_setup_chains_x();
+diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
+index c608bb9..bbe2e43 100644
+--- a/src/mainboard/tyan/s2912/romstage.c
++++ b/src/mainboard/tyan/s2912/romstage.c
+@@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 	 * So here need to make sure last core0 is started, esp for two way system,
+ 	 * (there may be apic id conflicts in that case)
+ 	 */
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
+index cdf51b1..0fe004e 100644
+--- a/src/mainboard/tyan/s2912_fam10/romstage.c
++++ b/src/mainboard/tyan/s2912_fam10/romstage.c
+@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ #if CONFIG_LOGICAL_CPUS
+ 	/* Core0 on each node is configured. Now setup any additional cores. */
+ 	printk(BIOS_DEBUG, "start_other_cores()\n");
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	post_code(0x37);
+ 	wait_all_other_cores_started(bsp_apicid);
+ #endif
+diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
+index 5c0b128..fcf9568 100644
+--- a/src/mainboard/tyan/s4880/romstage.c
++++ b/src/mainboard/tyan/s4880/romstage.c
+@@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+ #endif
+ 	// automatically set that for you, but you might meet tight space
+         needs_reset |= ht_setup_chains_x();
+diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
+index ed84ab6..f2ea852 100644
+--- a/src/mainboard/tyan/s4882/romstage.c
++++ b/src/mainboard/tyan/s4882/romstage.c
+@@ -108,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+         wait_all_core0_started();
+ #if CONFIG_LOGICAL_CPUS
+         // It is said that we should start core1 after all core0 launched
+-        start_other_cores();
++        start_other_cores(bsp_apicid);
+         wait_all_other_cores_started(bsp_apicid);
+ #endif
+ 
+diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c
+index 20eb92e..76e6393 100644
+--- a/src/mainboard/winent/mb6047/romstage.c
++++ b/src/mainboard/winent/mb6047/romstage.c
+@@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+ 
+ 	wait_all_core0_started();
+ 	// It is said that we should start core1 after all core0 launched
+-	start_other_cores();
++	start_other_cores(bsp_apicid);
+ 	wait_all_other_cores_started(bsp_apicid);
+ 
+ #if CONFIG_SET_FIDVID
+diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
+index 849f4a8..82bf885 100644
+--- a/src/northbridge/amd/amdht/h3finit.c
++++ b/src/northbridge/amd/amdht/h3finit.c
+@@ -389,13 +389,49 @@ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat)
+  */
+ static void htDiscoveryFloodFill(sMainData *pDat)
+ {
+-	u8 currentNode = 0;
+-	u8 currentLink;
++	uint8_t currentNode = 0;
++	uint8_t currentLink;
++	uint8_t currentLinkID;
++
++	/* NOTE
++	 * Each node inside a dual node (socket G34) processor must share
++	 * an adjacent node ID.  Alter the link scan order such that the
++	 * other internal node is always scanned first...
++	 */
++	uint8_t currentLinkScanOrder_Default[8] = {0, 1, 2, 3, 4, 5, 6, 7};
++	uint8_t currentLinkScanOrder_G34_Fam10[8] = {1, 0, 2, 3, 4, 5, 6, 7};
++	uint8_t currentLinkScanOrder_G34_Fam15[8] = {2, 0, 1, 3, 4, 5, 6, 7};
++
++	uint8_t fam15h = 0;
++	uint8_t rev_gte_d = 0;
++	uint8_t dual_node = 0;
++	uint32_t f3xe8;
++	uint32_t family;
++	uint32_t model;
++
++	f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
++
++	family = model = cpuid_eax(0x80000001);
++	model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
++	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
++
++	if (family >= 0x6f) {
++		/* Family 15h or later */
++		fam15h = 1;
++	}
++
++	if ((model >= 0x8) || fam15h)
++		/* Revision D or later */
++		rev_gte_d = 1;
++
++	if (rev_gte_d)
++		 /* Check for dual node capability */
++		if (f3xe8 & 0x20000000)
++			dual_node = 1;
+ 
+ 	/* Entries are always added in pairs, the even indices are the 'source'
+ 	 * side closest to the BSP, the odd indices are the 'destination' side
+ 	 */
+-
+ 	while (currentNode <= pDat->NodesDiscovered)
+ 	{
+ 		u32 temp;
+@@ -423,11 +459,24 @@ static void htDiscoveryFloodFill(sMainData *pDat)
+ 		/* Enable routing tables on currentNode*/
+ 		pDat->nb->enableRoutingTables(currentNode, pDat->nb);
+ 
+-		for (currentLink = 0; currentLink < pDat->nb->maxLinks; currentLink++)
++		for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++)
+ 		{
+ 			BOOL linkfound;
+ 			u8 token;
+ 
++			if (currentLinkID < 8) {
++				if (dual_node) {
++					if (fam15h)
++						currentLink = currentLinkScanOrder_G34_Fam15[currentLinkID];
++					else
++						currentLink = currentLinkScanOrder_G34_Fam10[currentLinkID];
++				} else {
++					currentLink = currentLinkScanOrder_Default[currentLinkID];
++				}
++			} else {
++				currentLink = currentLinkID;
++			}
++
+ 			if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(currentNode, currentLink))
+ 				continue;
+ 
+diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
+index 8f9177f..1026d0e 100644
+--- a/src/northbridge/amd/amdht/h3ncmn.c
++++ b/src/northbridge/amd/amdht/h3ncmn.c
+@@ -51,8 +51,9 @@
+ #define REG_NODE_ID_0X60		0x60
+ #define REG_UNIT_ID_0X64		0x64
+ #define REG_LINK_TRANS_CONTROL_0X68	0x68
+-#define REG_LINK_INIT_CONTROL_0X6C	0x6C
++#define REG_LINK_INIT_CONTROL_0X6C	0x6c
+ #define REG_HT_CAP_BASE_0X80		0x80
++#define REG_NORTHBRIDGE_CFG_3X8C	0x8c
+ #define REG_HT_LINK_RETRY0_0X130	0x130
+ #define REG_HT_TRAFFIC_DIST_0X164	0x164
+ #define REG_HT_LINK_EXT_CONTROL0_0X170	0x170
+@@ -91,6 +92,21 @@
+  ***			FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS		***
+  ***************************************************************************/
+ 
++static inline uint8_t is_fam15h(void)
++{
++	uint8_t fam15h = 0;
++	uint32_t family;
++
++	family = cpuid_eax(0x80000001);
++	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
++
++	if (family >= 0x6f)
++		/* Family 15h or later */
++		fam15h = 1;
++
++	return fam15h;
++}
++
+ /***************************************************************************//**
+  *
+  * SBDFO
+@@ -219,8 +235,18 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb)
+ 
+ static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb)
+ {
+-	u32 temp = nodeID;
++	u32 temp;
+ 	ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes));
++	if (is_fam15h()) {
++		temp = 1;
++		AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node),
++					makePCIBusFromNode(node),
++					makePCIDeviceFromNode(node),
++					CPU_NB_FUNC_03,
++					REG_NORTHBRIDGE_CFG_3X8C),
++					22, 22, &temp);
++	}
++	temp = nodeID;
+ 	AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node),
+ 				makePCIBusFromNode(node),
+ 				makePCIDeviceFromNode(node),
+diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
+index c0ccc69..a4aaa12 100644
+--- a/src/northbridge/amd/amdht/ht_wrapper.c
++++ b/src/northbridge/amd/amdht/ht_wrapper.c
+@@ -92,16 +92,132 @@ static  u32 get_nodes(void)
+  */
+ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
+ {
+-	u8 i;
++	uint8_t i;
++	uint8_t log_level;
++	uint8_t dump_event_detail;
+ 
+-	printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
+-	printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
++	printk(BIOS_DEBUG, "AMD_CB_EventNotify(): ");
+ 
+-	for (i = 0; i < *pEventData0; i++) {
+-		printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
++	/* Decode event */
++	dump_event_detail = 1;
++	switch (evtClass) {
++		case HT_EVENT_CLASS_CRITICAL:
++			log_level = BIOS_DEBUG;
++			printk(log_level, "CRITICAL");
++			break;
++		case HT_EVENT_CLASS_ERROR:
++			log_level = BIOS_DEBUG;
++			printk(log_level, "ERROR");
++			break;
++		case HT_EVENT_CLASS_HW_FAULT:
++			log_level = BIOS_DEBUG;
++			printk(log_level, "HARDWARE FAULT");
++			break;
++		case HT_EVENT_CLASS_WARNING:
++			log_level = BIOS_DEBUG;
++			printk(log_level, "WARNING");
++			break;
++		case HT_EVENT_CLASS_INFO:
++			log_level = BIOS_DEBUG;
++			printk(log_level, "INFO");
++			break;
++		default:
++			log_level = BIOS_DEBUG;
++			printk(log_level, "UNKNOWN");
++			break;
+ 	}
+-	printk(BIOS_DEBUG, "\n");
++	printk(log_level, ": ");
+ 
++	switch(event) {
++		case HT_EVENT_COH_EVENTS:
++			printk(log_level, "HT_EVENT_COH_EVENTS");
++			break;
++		case HT_EVENT_COH_NO_TOPOLOGY:
++			printk(log_level, "HT_EVENT_COH_NO_TOPOLOGY");
++			break;
++		case HT_EVENT_COH_LINK_EXCEED:
++			printk(log_level, "HT_EVENT_COH_LINK_EXCEED");
++			break;
++		case HT_EVENT_COH_FAMILY_FEUD:
++			printk(log_level, "HT_EVENT_COH_FAMILY_FEUD");
++			break;
++		case HT_EVENT_COH_NODE_DISCOVERED:
++			{
++				printk(log_level, "HT_EVENT_COH_NODE_DISCOVERED");
++				sHtEventCohNodeDiscovered *evt = (sHtEventCohNodeDiscovered*)pEventData0;
++				printk(log_level, ": node %d link %d new node: %d",
++					evt->node, evt->link, evt->newNode);
++				dump_event_detail = 0;
++				break;
++			}
++		case HT_EVENT_COH_MPCAP_MISMATCH:
++			printk(log_level, "HT_EVENT_COH_MPCAP_MISMATCH");
++			break;
++		case HT_EVENT_NCOH_EVENTS:
++			printk(log_level, "HT_EVENT_NCOH_EVENTS");
++			break;
++		case HT_EVENT_NCOH_BUID_EXCEED:
++			printk(log_level, "HT_EVENT_NCOH_BUID_EXCEED");
++			break;
++		case HT_EVENT_NCOH_LINK_EXCEED:
++			printk(log_level, "HT_EVENT_NCOH_LINK_EXCEED");
++			break;
++		case HT_EVENT_NCOH_BUS_MAX_EXCEED:
++			printk(log_level, "HT_EVENT_NCOH_BUS_MAX_EXCEED");
++			break;
++		case HT_EVENT_NCOH_CFG_MAP_EXCEED:
++			printk(log_level, "HT_EVENT_NCOH_CFG_MAP_EXCEED");
++			break;
++		case HT_EVENT_NCOH_DEVICE_FAILED:
++			{
++				printk(log_level, "HT_EVENT_NCOH_DEVICE_FAILED");
++				sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0;
++				printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d",
++					evt->node, evt->link, evt->depth, evt->attemptedBUID);
++				dump_event_detail = 0;
++				break;
++			}
++		case HT_EVENT_NCOH_AUTO_DEPTH:
++			{
++				printk(log_level, "HT_EVENT_NCOH_AUTO_DEPTH");
++				sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0;
++				printk(log_level, ": node %d link %d depth: %d",
++					evt->node, evt->link, evt->depth);
++				dump_event_detail = 0;
++				break;
++			}
++		case HT_EVENT_OPT_EVENTS:
++			printk(log_level, "HT_EVENT_OPT_EVENTS");
++			break;
++		case HT_EVENT_OPT_REQUIRED_CAP_RETRY:
++			printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_RETRY");
++			break;
++		case HT_EVENT_OPT_REQUIRED_CAP_GEN3:
++			printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_GEN3");
++			break;
++		case HT_EVENT_HW_EVENTS:
++			printk(log_level, "HT_EVENT_HW_EVENTS");
++			break;
++		case HT_EVENT_HW_SYNCHFLOOD:
++			printk(log_level, "HT_EVENT_HW_SYNCHFLOOD");
++			break;
++		case HT_EVENT_HW_HTCRC:
++			printk(log_level, "HT_EVENT_HW_HTCRC");
++			break;
++		default:
++			printk(log_level, "HT_EVENT_UNKNOWN");
++			break;
++	}
++	printk(log_level, "\n");
++
++	if (dump_event_detail) {
++		printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
++
++		for (i = 0; i < *pEventData0; i++) {
++			printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
++		}
++		printk(BIOS_DEBUG, "\n");
++	}
+ }
+ 
+ /**
+@@ -210,9 +326,10 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
+ 				for (node = 0; node < node_count; node++) {
+ 					f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8);
+ 					uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30);
+-					printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number);
++					printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link", node, internal_node_number);
+ 					if (internal_node_number == 0) {
+ 						uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x98:0xd8) & 0x1;
++						printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected);
+ 						if (package_link_3_connected) {
+ 							/* Set WidthIn and WidthOut to 0 */
+ 							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4);
+@@ -234,15 +351,21 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
+ 						}
+ 					} else if (internal_node_number == 1) {
+ 						uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xf8:0xb8) & 0x1;
++						printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected);
+ 						if (package_link_3_connected) {
+ 							/* Set WidthIn and WidthOut to 0 */
+ 							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4);
+ 							dword &= ~0x77000000;
+ 							pci_write_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4, dword);
+ 							/* Set Ganged to 1 */
+-							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174);
++							/* WARNING
++							 * The Family 15h BKDG states that 0x18c should be set,
++							 * however this is in error.  0x17c is the correct control
++							 * register (sublink 0) for these processors...
++							 */
++							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174);
+ 							dword |= 0x00000001;
+-							pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174, dword);
++							pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174, dword);
+ 						} else {
+ 							/* Set ConnDly to 1 */
+ 							dword = pci_read_config32(NODE_PCI(node, 0), 0x16c);
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+index 5a57dc0..0b61106 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+@@ -5441,6 +5441,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc
+ 		cpu_divisor = (0x1 << cpu_did);
+ 		pMCTstat->TSCFreq = (100 * (cpu_fid + 0x10)) / cpu_divisor;
+ 
++		printk(BIOS_DEBUG, "mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15\n");
+ 		mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat);
+ 	} else {
+ 		/* K10 BKDG v3.62 section 2.8.9.2 */
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdfam10-Add-probe-filter-support.patch b/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdfam10-Add-probe-filter-support.patch
index 6689711..09531d0 100644
--- a/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdfam10-Add-probe-filter-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdfam10-Add-probe-filter-support.patch
@@ -1,17 +1,19 @@
-From 92b74cb17d6494327b0fb83af52769aaeef0b083 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From c2436d732bdb97abdc4b4784598bc6c5d467a61f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 2 Aug 2015 21:06:39 -0500
-Subject: [PATCH 090/146] northbridge/amd/amdfam10: Add probe filter support
+Subject: [PATCH 088/139] northbridge/amd/amdfam10: Add probe filter support
 
+Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/init_cpus.c        |   13 +++
- src/northbridge/amd/amdfam10/northbridge.c |  144 +++++++++++++++++++++++++++-
+ src/cpu/amd/family_10h-family_15h/init_cpus.c |  13 +++
+ src/northbridge/amd/amdfam10/northbridge.c    | 144 +++++++++++++++++++++++++-
  2 files changed, 156 insertions(+), 1 deletion(-)
 
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index e7f146f..f716e07 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 986c024..2bc54dc 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -445,6 +445,19 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
  
  		cpuSetAMDMSR(id.nodeid);
@@ -33,7 +35,7 @@ index e7f146f..f716e07 100644
  #if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY
  		// Run on all AP for proper FID/VID setup.
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index 7cbb732..2c8ee08 100644
+index 95e902d..cdb8afa 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
 @@ -30,10 +30,13 @@
@@ -47,10 +49,10 @@ index 7cbb732..2c8ee08 100644
  #include <cpu/amd/mtrr.h>
  #include <cpu/amd/amdfam10_sysconf.h>
 +#include <cpu/amd/model_10xxx_msr.h>
- #include <cpu/amd/model_10xxx/ram_calc.h>
+ #include <cpu/amd/family_10h-family_15h/ram_calc.h>
  
  #if CONFIG_LOGICAL_CPUS
-@@ -1523,7 +1526,7 @@ static void cpu_bus_scan(device_t dev)
+@@ -1527,7 +1530,7 @@ static void cpu_bus_scan(device_t dev)
  		if(i>=32) {
  			busn--;
  			devn-=32;
@@ -59,7 +61,7 @@ index 7cbb732..2c8ee08 100644
  		}
  #endif
  
-@@ -1643,8 +1646,147 @@ static void cpu_bus_scan(device_t dev)
+@@ -1647,8 +1650,147 @@ static void cpu_bus_scan(device_t dev)
  	}
  }
  
@@ -208,5 +210,5 @@ index 7cbb732..2c8ee08 100644
  #if CONFIG_AMD_SB_CIMX
  	sb_After_Pci_Init();
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0091-cpu-amd-model_10xxx-Bring-initial-HT-register-config.patch b/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-family_10h-family_15h-Bring-initial-HT-regis.patch
index 953f0a1..4b5845b 100644
--- a/resources/libreboot/patch/kgpe-d16/0091-cpu-amd-model_10xxx-Bring-initial-HT-register-config.patch
+++ b/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-family_10h-family_15h-Bring-initial-HT-regis.patch
@@ -1,17 +1,19 @@
-From 7d6c926721b9cc634841b385cd48ae38a146e875 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5fb316c1ccf4427fbd86458e85c3bda2076f6fa0 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 2 Aug 2015 21:18:29 -0500
-Subject: [PATCH 091/146] cpu/amd/model_10xxx: Bring initial HT register
- configuration in line with BKDG
+Subject: [PATCH 089/139] cpu/amd/family_10h-family_15h: Bring initial HT
+ register configuration in line with BKDG
 
+Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/defaults.h |  168 ++++++++++++++++++++++++++++--------
+ src/cpu/amd/family_10h-family_15h/defaults.h | 168 +++++++++++++++++++++------
  1 file changed, 133 insertions(+), 35 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index 513d169..1080cfc 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -388,44 +388,140 @@ static const struct {
  					   [2] SyncOnUcEccEn = 1 */
  
@@ -242,5 +244,5 @@ index 513d169..1080cfc 100644
 +					   [20:16] RttIndex = 04h */
  };
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-model_10xxx-Fix-Family-15h-multiple-package-.patch b/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-model_10xxx-Fix-Family-15h-multiple-package-.patch
deleted file mode 100644
index 2235324..0000000
--- a/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-model_10xxx-Fix-Family-15h-multiple-package-.patch
+++ /dev/null
@@ -1,948 +0,0 @@
-From 37de124d5fb295bd2d39201a9c3a0a0805a38327 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Thu, 30 Jul 2015 14:07:15 -0500
-Subject: [PATCH 089/146] cpu/amd/model_10xxx: Fix Family 15h multiple package
- support
-
-TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
-and several different RDIMM configurations.
----
- src/cpu/amd/car/cache_as_ram.inc            |   17 +++-
- src/cpu/amd/model_10xxx/defaults.h          |  101 ++++++++++++++++---
- src/cpu/amd/model_10xxx/fidvid.c            |   81 +++++++--------
- src/cpu/amd/model_10xxx/init_cpus.c         |   66 +++++++++++--
- src/cpu/amd/quadcore/quadcore.c             |   19 +---
- src/cpu/amd/quadcore/quadcore_id.c          |    1 -
- src/mainboard/asus/kgpe-d16/romstage.c      |   46 +++++++--
- src/northbridge/amd/amdht/h3finit.c         |   57 ++++++++++-
- src/northbridge/amd/amdht/h3ncmn.c          |   30 +++++-
- src/northbridge/amd/amdht/ht_wrapper.c      |  141 +++++++++++++++++++++++++--
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |    1 +
- 11 files changed, 458 insertions(+), 102 deletions(-)
-
-diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
-index 9a51e3c..7d71171 100644
---- a/src/cpu/amd/car/cache_as_ram.inc
-+++ b/src/cpu/amd/car/cache_as_ram.inc
-@@ -525,8 +525,23 @@ CAR_FAM10_ap:
- 	/* Fam10h NB config bit 54 was not set */
- 	rolb	%cl, %bl
- roll_cfg:
-+	jmp_if_not_fam15h(ap_apicid_ready)
-+	cmp	$0x5, %ecx
-+	jne	ap_apicid_ready
- 
--	/* Calculate stack pointer. */
-+	/* This is a multi-node CPU
-+	 * Adjust the maximum APIC ID to a more reasonable value
-+	 * given that no 32-core Family 15h processors exist
-+	 */
-+	movl	%ebx, %ecx
-+	and	$0x0f, %ecx		/* Get lower 4 bits of CPU number */
-+	and	$0x60, %ebx		/* Get node ID */
-+	shrl	$0x1, %ebx		/* Shift node ID part of APIC ID down by 1 */
-+	or	%ecx, %ebx		/* Recombine node ID and CPU number */
-+
-+ap_apicid_ready:
-+
-+	/* Calculate stack pointer using adjusted APIC ID stored in ebx */
- 	movl	$CacheSizeAPStack, %eax
- 	mull	%ebx
- 	movl	$(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
-index 24f87ba..513d169 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
-@@ -244,18 +244,50 @@ static const struct {
- 	{ 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
- 	  AMD_PTYPE_SVR, 0x00200000, 0x00600000 },	/* [22:21] DsNpReqLmt0 = 01b */
- 
--	{ 0, 0x84, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
-+	{ 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
- 
--	{ 0, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
-+	{ 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
- 
--	{ 0, 0xC4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
-+	{ 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
- 
--	{ 0, 0xE4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
-+	{ 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
- 
-+	/* FIXME
-+	 * Non-C32 packages only
-+	 */
-+	{ 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+
-+	{ 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+
-+	{ 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+
-+	{ 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00000000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+
-+	/* FIXME
-+	 * C32 package only
-+	 */
-+#if 0
-+	{ 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+
-+	{ 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+
-+	{ 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+
-+	{ 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
-+	  0x00002000, 0x00002000 },	/* [13] LdtStopTriEn = 1 */
-+#endif
-+
- 	/* Link Global Retry Control Register */
- 	{ 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 	  0x00073900, 0x00073F00 },
-@@ -614,38 +646,79 @@ static const struct {
- 	{ 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 	  0x00004400, 0x00006400 },	/* HT_PHY_DLL_REG */
- 
--	{ 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
-+					   completeness */
-+
-+	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
-+					   completeness */
-+
-+	{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
-+	  0x0000006D, 0x000000FF },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
-+
-+	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
-+	  0x0000006D, 0x000000FF }, 	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
-+
-+	/* Link Phy Receiver Loop Filter Registers */
-+	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
-+					   [21:14] LfcMin = 10h */
-+
-+	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
-+					   [21:14] LfcMin = 10h */
-+
-+	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
-+	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
-+					   [21:14] LfcMin = 08h */
-+
-+	{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
-+	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
-+					   [21:14] LfcMin = 08h */
-+
-+	{ 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
-+	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
-+					  [20:16] RttIndex = 04h */
-+
-+/* FIXME
-+ * Causes lockups for some reason when more than one package is installed
-+ * Debug and reactivate!
-+ */
-+// #if 0
-+	{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
- 					   completeness */
- 
--	{ 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 	  0x00000000, 0x000000FF },	/* Provide clear setting for logical
- 					   completeness */
- 
--	{ 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
-+	{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 	  0x0000006D, 0x000000FF },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
- 
--	{ 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
-+	{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
- 	  0x0000006D, 0x000000FF }, 	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
- 
- 	/* Link Phy Receiver Loop Filter Registers */
--	{ 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
- 					   [21:14] LfcMin = 10h */
- 
--	{ 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	{ 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 	  0x08040000, 0x3FFFC000 },	/* [29:22] LfcMax = 20h,
- 					   [21:14] LfcMin = 10h */
- 
--	{ 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
-+	{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
- 					   [21:14] LfcMin = 08h */
- 
--	{ 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
-+	{ 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 	  0x04020000, 0x3FFFC000 },	/* [29:22] LfcMax = 10h,
- 					   [21:14] LfcMin = 08h */
- 
--	{ 0xC0, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
-+	{ 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
--								   [20:16] RttIndex = 04h */
-+					  [20:16] RttIndex = 04h */
-+// #endif
- };
-diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
-index 0e870e3..fe1cfb4 100644
---- a/src/cpu/amd/model_10xxx/fidvid.c
-+++ b/src/cpu/amd/model_10xxx/fidvid.c
-@@ -633,44 +633,45 @@ static void prep_fid_change(void)
- }
- 
- static void waitCurrentPstate(u32 target_pstate) {
--  msr_t initial_msr = rdmsr(TSC_MSR);
--  msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
--  msr_t tsc_msr;
--  u8 timedout ;
--
--  /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
--   * P1 that is a copy of P0, therefore has the same NB DID but the
--   * TSC will count twice per tick, so we have to wait for twice the
--   * count to achieve the desired timeout. But I'm likely to
--   * misunderstand this...
--   */
--  u32 corrected_timeout = (    (pstate_msr.lo==1)
--			    && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
--                          WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT  ;
--  msr_t timeout;
--
--  timeout.lo = initial_msr.lo + corrected_timeout ;
--  timeout.hi = initial_msr.hi;
--  if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
--     timeout.hi++;
--  }
--
--  // assuming TSC ticks at 1.25 ns per tick (800 MHz)
--  do {
--      pstate_msr = rdmsr(CUR_PSTATE_MSR);
--      tsc_msr = rdmsr(TSC_MSR);
--      timedout = (tsc_msr.hi > timeout.hi)
--        	|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
--  } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
--
--  if (pstate_msr.lo != target_pstate) {
--    msr_t limit_msr = rdmsr(0xc0010061);
--    printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo);
--
--    do { // should we just go on instead ?
--      pstate_msr = rdmsr(CUR_PSTATE_MSR);
--    } while ( pstate_msr.lo != target_pstate  ) ;
--  }
-+	msr_t initial_msr = rdmsr(TSC_MSR);
-+	msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
-+	msr_t tsc_msr;
-+	u8 timedout ;
-+	
-+	/* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
-+	* P1 that is a copy of P0, therefore has the same NB DID but the
-+	* TSC will count twice per tick, so we have to wait for twice the
-+	* count to achieve the desired timeout. But I'm likely to
-+	* misunderstand this...
-+	*/
-+	u32 corrected_timeout = ((pstate_msr.lo==1)
-+				&& (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
-+				WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT;
-+	msr_t timeout;
-+	
-+	timeout.lo = initial_msr.lo + corrected_timeout ;
-+	timeout.hi = initial_msr.hi;
-+	if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
-+		timeout.hi++;
-+	}
-+	
-+	// assuming TSC ticks at 1.25 ns per tick (800 MHz)
-+	do {
-+		pstate_msr = rdmsr(CUR_PSTATE_MSR);
-+		tsc_msr = rdmsr(TSC_MSR);
-+		timedout = (tsc_msr.hi > timeout.hi)
-+			|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
-+	} while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
-+	
-+	if (pstate_msr.lo != target_pstate) {
-+		msr_t limit_msr = rdmsr(0xc0010061);
-+		printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n",
-+			cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo);
-+		
-+		do { // should we just go on instead ?
-+			pstate_msr = rdmsr(CUR_PSTATE_MSR);
-+		} while ( pstate_msr.lo != target_pstate  ) ;
-+	}
- }
- 
- static void set_pstate(u32 nonBoostedPState) {
-@@ -1063,13 +1064,13 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
- 	   APs and BSP */
- 	ap_apicidx.num = 0;
- 
--	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
-+	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, -1, store_ap_apicid, &ap_apicidx);
- 
- 	for (i = 0; i < ap_apicidx.num; i++) {
- 		init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
- 	}
- #else
--	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
-+	for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv);
- #endif
- 
- 	print_debug_fv("common_fid = ", fv.common_fid);
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 0d1f043..e7f146f 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
-@@ -59,6 +59,8 @@ static void set_EnableCf8ExtCfg(void)
- static void set_EnableCf8ExtCfg(void) { }
- #endif
- 
-+// #define DEBUG_HT_SETUP 1
-+// #define FAM10_AP_NODE_SEQUENTIAL_START 1
- 
- typedef void (*process_ap_t) (u32 apicid, void *gp);
- 
-@@ -143,8 +145,8 @@ uint32_t get_boot_apic_id(uint8_t node, uint32_t core) {
- //core range = 1 : core 0 only
- //core range = 2 : cores other than core0
- 
--static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
--			void *gp)
-+static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
-+			process_ap_t process_ap, void *gp)
- {
- 	// here assume the OS don't change our apicid
- 	u32 ap_apicid;
-@@ -165,6 +167,9 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
- 	}
- 
- 	for (i = 0; i < nodes; i++) {
-+		if ((node >= 0) && (i != node))
-+			continue;
-+
- 		cores_found = get_core_num_in_bsp(i);
- 
- 		u32 jstart, jend;
-@@ -280,7 +285,7 @@ void wait_all_other_cores_started(u32 bsp_apicid)
- {
- 	// all aps other than core0
- 	printk(BIOS_DEBUG, "started ap apicid: ");
--	for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0);
-+	for_each_ap(bsp_apicid, 2, -1, wait_ap_started, (void *)0);
- 	printk(BIOS_DEBUG, "\n");
- }
- 
-@@ -373,8 +378,10 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
- 	/* NB_CFG MSR is shared between cores, so we need make sure
- 	   core0 is done at first --- use wait_all_core0_started  */
- 	if (id.coreid == 0) {
--		set_apicid_cpuid_lo();	/* only set it on core0 */
--		set_EnableCf8ExtCfg();	/* only set it on core0 */
-+		/* Set InitApicIdCpuIdLo / EnableCf8ExtCfg on core0 only */
-+		if (!is_fam15h())
-+			set_apicid_cpuid_lo();
-+		set_EnableCf8ExtCfg();
- #if CONFIG_ENABLE_APIC_EXT_ID
- 		enable_apic_ext_id(id.nodeid);
- #endif
-@@ -427,6 +434,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
- 	}
- 	// Mark the core as started.
- 	lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED);
-+	printk(BIOS_DEBUG, "CPU APICID %02x start flag set\n", apicid);
- 
- 	if (apicid != bsp_apicid) {
- 		/* Setup each AP's cores MSRs.
-@@ -588,6 +596,34 @@ static void setup_remote_node(u8 node)
- }
- #endif				/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
- 
-+//it is running on core0 of node0
-+static void start_other_cores(uint32_t bsp_apicid)
-+{
-+	u32 nodes;
-+	u32 nodeid;
-+
-+	// disable multi_core
-+	if (read_option(multi_core, 0) != 0)  {
-+		printk(BIOS_DEBUG, "Skip additional core init\n");
-+		return;
-+	}
-+
-+	nodes = get_nodes();
-+
-+	for (nodeid = 0; nodeid < nodes; nodeid++) {
-+		u32 cores = get_core_num_in_bsp(nodeid);
-+		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1\n", nodeid, cores);
-+		if (cores > 0) {
-+			real_start_other_core(nodeid, cores);
-+#ifdef FAM10_AP_NODE_SEQUENTIAL_START
-+			printk(BIOS_DEBUG, "waiting for core start on node %d...\n", nodeid);
-+			for_each_ap(bsp_apicid, 2, nodeid, wait_ap_started, (void *)0);
-+			printk(BIOS_DEBUG, "...started\n");
-+#endif
-+		}
-+	}
-+}
-+
- static void AMD_Errata281(u8 node, uint64_t revision, u32 platform)
- {
- 	/* Workaround for Transaction Scheduling Conflict in
-@@ -847,6 +883,10 @@ static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry)
- 
- 	phyBase = ((u32) link << 3) | 0x180;
- 
-+	/* Determine if link is connected and abort if not */
-+	if (!(pci_read_config32(NODE_PCI(node, 0), 0x98 + (link * 0x20)) & 0x1))
-+		return;
-+
- 	/* Get the portal control register's initial value
- 	 * and update it to access the desired phy register
- 	 */
-@@ -1005,10 +1045,11 @@ static void cpuSetAMDPCI(u8 node)
- 	 * Hypertransport initialization has taken place.  Also note
- 	 * that it is run for the first core on each node
- 	 */
--	u8 i, j;
-+	uint8_t i;
-+	uint8_t j;
- 	u32 platform;
- 	u32 val;
--	u8 offset;
-+	uint8_t offset;
- 	uint32_t dword;
- 	uint64_t revision;
- 
-@@ -1035,6 +1076,17 @@ static void cpuSetAMDPCI(u8 node)
- 		}
- 	}
- 
-+#ifdef DEBUG_HT_SETUP
-+	/* Dump link settings */
-+	for (i = 0; i < 4; i++) {
-+		for (j = 0; j < 4; j++) {
-+			printk(BIOS_DEBUG, "Node %d link %d: type register: %08x control register: %08x extended control sublink 0: %08x 1: %08x\n", i, j,
-+				pci_read_config32(NODE_PCI(i, 0), 0x98 + (j * 0x20)), pci_read_config32(NODE_PCI(i, 0), 0x84 + (j * 0x20)),
-+				pci_read_config32(NODE_PCI(i, 0), 0x170 + (j * 0x4)), pci_read_config32(NODE_PCI(i, 0), 0x180 + (j * 0x4)));
-+		}
-+	}
-+#endif
-+
- 	for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
- 		if ((fam10_htphy_default[i].revision & revision) &&
- 		    (fam10_htphy_default[i].platform & platform)) {
-diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
-index 8a9b5ed..9c31eac 100644
---- a/src/cpu/amd/quadcore/quadcore.c
-+++ b/src/cpu/amd/quadcore/quadcore.c
-@@ -31,21 +31,6 @@
- uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
- uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
- 
--static inline uint8_t is_fam15h(void)
--{
--	uint8_t fam15h = 0;
--	uint32_t family;
--
--	family = cpuid_eax(0x80000001);
--	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
--
--	if (family >= 0x6f)
--		/* Family 15h or later */
--		fam15h = 1;
--
--	return fam15h;
--}
--
- static u32 get_core_num_in_bsp(u32 nodeid)
- {
- 	u32 dword;
-@@ -141,6 +126,7 @@ static void real_start_other_core(uint32_t nodeid, uint32_t cores)
- 	}
- }
- 
-+#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
- //it is running on core0 of node0
- static void start_other_cores(void)
- {
-@@ -157,9 +143,10 @@ static void start_other_cores(void)
- 
- 	for (nodeid = 0; nodeid < nodes; nodeid++) {
- 		u32 cores = get_core_num_in_bsp(nodeid);
--		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1 \n", nodeid, cores);
-+		printk(BIOS_DEBUG, "init node: %02x  cores: %02x pass 1\n", nodeid, cores);
- 		if (cores > 0) {
- 			real_start_other_core(nodeid, cores);
- 		}
- 	}
- }
-+#endif
-diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
-index c0537b3..1f5cbd8 100644
---- a/src/cpu/amd/quadcore/quadcore_id.c
-+++ b/src/cpu/amd/quadcore/quadcore_id.c
-@@ -108,7 +108,6 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
- 			id.nodeid = apicid & 0x7;
- 		}
- 	}
--
- 	if (fam15h && dual_node) {
- 		/* Coreboot expects each separate processor die to be on a different nodeid.
- 		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
-diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
-index 0df2447..acc8308 100644
---- a/src/mainboard/asus/kgpe-d16/romstage.c
-+++ b/src/mainboard/asus/kgpe-d16/romstage.c
-@@ -97,7 +97,18 @@ static void switch_spd_mux(uint8_t channel)
- 	pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
- }
- 
--static const uint8_t spd_addr[] = {
-+static const uint8_t spd_addr_fam15[] = {
-+	// Socket 0 Node 0 ("Node 0")
-+	RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
-+	// Socket 0 Node 1 ("Node 1")
-+	RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
-+	// Socket 1 Node 0 ("Node 2")
-+	RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
-+	// Socket 1 Node 1 ("Node 3")
-+	RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
-+};
-+
-+static const uint8_t spd_addr_fam10[] = {
- 	// Socket 0 Node 0 ("Node 0")
- 	RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
- 	// Socket 0 Node 1 ("Node 1")
-@@ -117,10 +128,10 @@ static void activate_spd_rom(const struct mem_controller *ctrl) {
- 		switch_spd_mux(0x2);
- 	} else if (ctrl->node_id == 1) {
- 		printk(BIOS_DEBUG, "enable_spd_node1()\n");
--		switch_spd_mux((sysinfo->nodes <= 2)?0x2:0x3);
-+		switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3);
- 	} else if (ctrl->node_id == 2) {
- 		printk(BIOS_DEBUG, "enable_spd_node2()\n");
--		switch_spd_mux((sysinfo->nodes <= 2)?0x3:0x2);
-+		switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2);
- 	} else if (ctrl->node_id == 3) {
- 		printk(BIOS_DEBUG, "enable_spd_node3()\n");
- 		switch_spd_mux(0x3);
-@@ -306,18 +317,25 @@ void initialize_romstage_console_lock(void)
- 
- void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
- {
-+	uint32_t esp;
-+	__asm__ volatile (
-+		"movl %%esp, %0"
-+		: "=r" (esp)
-+		);
-+
- 	struct sys_info *sysinfo = &sysinfo_car;
- 
- 	uint32_t bsp_apicid = 0, val;
- 	uint8_t byte;
- 	msr_t msr;
- 
--	timestamp_init(timestamp_get());
--	timestamp_add_now(TS_START_ROMSTAGE);
--
- 	int s3resume = acpi_is_wakeup_s3();
- 
- 	if (!cpu_init_detectedx && boot_cpu()) {
-+		/* Initial timestamp */
-+		timestamp_init(timestamp_get());
-+		timestamp_add_now(TS_START_ROMSTAGE);
-+
- 		/* Initialize the printk spinlock */
- 		initialize_romstage_console_lock();
- 
-@@ -344,6 +362,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
- 		pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte);
- 	}
- 
-+	printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp);
-+
- 	post_code(0x30);
- 
- 	if (bist == 0)
-@@ -397,7 +417,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
- 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
- 		/* Core0 on each node is configured. Now setup any additional cores. */
- 		printk(BIOS_DEBUG, "start_other_cores()\n");
--		start_other_cores();
-+		start_other_cores(bsp_apicid);
- 		post_code(0x37);
- 		wait_all_other_cores_started(bsp_apicid);
- 	}
-@@ -455,7 +475,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
- 
- 	/* It's the time to set ctrl in sysinfo now; */
- 	printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes);
--	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-+	if (is_fam15h())
-+		fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15);
-+	else
-+		fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10);
- 	post_code(0x3D);
- 
- #if 0
-@@ -527,5 +550,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-  */
- BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
- {
-+	/* Force BUID to 0 */
-+	static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF};
-+	if ((node == 0) && (link == 1)) {	/* BSP SB link */
-+		*List = swaplist;
-+		return 1;
-+	}
-+
- 	return 0;
- }
-\ No newline at end of file
-diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
-index 849f4a8..82bf885 100644
---- a/src/northbridge/amd/amdht/h3finit.c
-+++ b/src/northbridge/amd/amdht/h3finit.c
-@@ -389,13 +389,49 @@ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat)
-  */
- static void htDiscoveryFloodFill(sMainData *pDat)
- {
--	u8 currentNode = 0;
--	u8 currentLink;
-+	uint8_t currentNode = 0;
-+	uint8_t currentLink;
-+	uint8_t currentLinkID;
-+
-+	/* NOTE
-+	 * Each node inside a dual node (socket G34) processor must share
-+	 * an adjacent node ID.  Alter the link scan order such that the
-+	 * other internal node is always scanned first...
-+	 */
-+	uint8_t currentLinkScanOrder_Default[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-+	uint8_t currentLinkScanOrder_G34_Fam10[8] = {1, 0, 2, 3, 4, 5, 6, 7};
-+	uint8_t currentLinkScanOrder_G34_Fam15[8] = {2, 0, 1, 3, 4, 5, 6, 7};
-+
-+	uint8_t fam15h = 0;
-+	uint8_t rev_gte_d = 0;
-+	uint8_t dual_node = 0;
-+	uint32_t f3xe8;
-+	uint32_t family;
-+	uint32_t model;
-+
-+	f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
-+
-+	family = model = cpuid_eax(0x80000001);
-+	model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
-+	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-+
-+	if (family >= 0x6f) {
-+		/* Family 15h or later */
-+		fam15h = 1;
-+	}
-+
-+	if ((model >= 0x8) || fam15h)
-+		/* Revision D or later */
-+		rev_gte_d = 1;
-+
-+	if (rev_gte_d)
-+		 /* Check for dual node capability */
-+		if (f3xe8 & 0x20000000)
-+			dual_node = 1;
- 
- 	/* Entries are always added in pairs, the even indices are the 'source'
- 	 * side closest to the BSP, the odd indices are the 'destination' side
- 	 */
--
- 	while (currentNode <= pDat->NodesDiscovered)
- 	{
- 		u32 temp;
-@@ -423,11 +459,24 @@ static void htDiscoveryFloodFill(sMainData *pDat)
- 		/* Enable routing tables on currentNode*/
- 		pDat->nb->enableRoutingTables(currentNode, pDat->nb);
- 
--		for (currentLink = 0; currentLink < pDat->nb->maxLinks; currentLink++)
-+		for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++)
- 		{
- 			BOOL linkfound;
- 			u8 token;
- 
-+			if (currentLinkID < 8) {
-+				if (dual_node) {
-+					if (fam15h)
-+						currentLink = currentLinkScanOrder_G34_Fam15[currentLinkID];
-+					else
-+						currentLink = currentLinkScanOrder_G34_Fam10[currentLinkID];
-+				} else {
-+					currentLink = currentLinkScanOrder_Default[currentLinkID];
-+				}
-+			} else {
-+				currentLink = currentLinkID;
-+			}
-+
- 			if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(currentNode, currentLink))
- 				continue;
- 
-diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
-index 8f9177f..1026d0e 100644
---- a/src/northbridge/amd/amdht/h3ncmn.c
-+++ b/src/northbridge/amd/amdht/h3ncmn.c
-@@ -51,8 +51,9 @@
- #define REG_NODE_ID_0X60		0x60
- #define REG_UNIT_ID_0X64		0x64
- #define REG_LINK_TRANS_CONTROL_0X68	0x68
--#define REG_LINK_INIT_CONTROL_0X6C	0x6C
-+#define REG_LINK_INIT_CONTROL_0X6C	0x6c
- #define REG_HT_CAP_BASE_0X80		0x80
-+#define REG_NORTHBRIDGE_CFG_3X8C	0x8c
- #define REG_HT_LINK_RETRY0_0X130	0x130
- #define REG_HT_TRAFFIC_DIST_0X164	0x164
- #define REG_HT_LINK_EXT_CONTROL0_0X170	0x170
-@@ -91,6 +92,21 @@
-  ***			FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS		***
-  ***************************************************************************/
- 
-+static inline uint8_t is_fam15h(void)
-+{
-+	uint8_t fam15h = 0;
-+	uint32_t family;
-+
-+	family = cpuid_eax(0x80000001);
-+	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-+
-+	if (family >= 0x6f)
-+		/* Family 15h or later */
-+		fam15h = 1;
-+
-+	return fam15h;
-+}
-+
- /***************************************************************************//**
-  *
-  * SBDFO
-@@ -219,8 +235,18 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb)
- 
- static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb)
- {
--	u32 temp = nodeID;
-+	u32 temp;
- 	ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes));
-+	if (is_fam15h()) {
-+		temp = 1;
-+		AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node),
-+					makePCIBusFromNode(node),
-+					makePCIDeviceFromNode(node),
-+					CPU_NB_FUNC_03,
-+					REG_NORTHBRIDGE_CFG_3X8C),
-+					22, 22, &temp);
-+	}
-+	temp = nodeID;
- 	AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node),
- 				makePCIBusFromNode(node),
- 				makePCIDeviceFromNode(node),
-diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
-index 0c6b474..772db1c 100644
---- a/src/northbridge/amd/amdht/ht_wrapper.c
-+++ b/src/northbridge/amd/amdht/ht_wrapper.c
-@@ -90,16 +90,132 @@ static  u32 get_nodes(void)
-  */
- static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
- {
--	u8 i;
-+	uint8_t i;
-+	uint8_t log_level;
-+	uint8_t dump_event_detail;
- 
--	printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
--	printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
-+	printk(BIOS_DEBUG, "AMD_CB_EventNotify(): ");
- 
--	for (i = 0; i < *pEventData0; i++) {
--		printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
-+	/* Decode event */
-+	dump_event_detail = 1;
-+	switch (evtClass) {
-+		case HT_EVENT_CLASS_CRITICAL:
-+			log_level = BIOS_DEBUG;
-+			printk(log_level, "CRITICAL");
-+			break;
-+		case HT_EVENT_CLASS_ERROR:
-+			log_level = BIOS_DEBUG;
-+			printk(log_level, "ERROR");
-+			break;
-+		case HT_EVENT_CLASS_HW_FAULT:
-+			log_level = BIOS_DEBUG;
-+			printk(log_level, "HARDWARE FAULT");
-+			break;
-+		case HT_EVENT_CLASS_WARNING:
-+			log_level = BIOS_DEBUG;
-+			printk(log_level, "WARNING");
-+			break;
-+		case HT_EVENT_CLASS_INFO:
-+			log_level = BIOS_DEBUG;
-+			printk(log_level, "INFO");
-+			break;
-+		default:
-+			log_level = BIOS_DEBUG;
-+			printk(log_level, "UNKNOWN");
-+			break;
- 	}
--	printk(BIOS_DEBUG, "\n");
-+	printk(log_level, ": ");
- 
-+	switch(event) {
-+		case HT_EVENT_COH_EVENTS:
-+			printk(log_level, "HT_EVENT_COH_EVENTS");
-+			break;
-+		case HT_EVENT_COH_NO_TOPOLOGY:
-+			printk(log_level, "HT_EVENT_COH_NO_TOPOLOGY");
-+			break;
-+		case HT_EVENT_COH_LINK_EXCEED:
-+			printk(log_level, "HT_EVENT_COH_LINK_EXCEED");
-+			break;
-+		case HT_EVENT_COH_FAMILY_FEUD:
-+			printk(log_level, "HT_EVENT_COH_FAMILY_FEUD");
-+			break;
-+		case HT_EVENT_COH_NODE_DISCOVERED:
-+			{
-+				printk(log_level, "HT_EVENT_COH_NODE_DISCOVERED");
-+				sHtEventCohNodeDiscovered *evt = (sHtEventCohNodeDiscovered*)pEventData0;
-+				printk(log_level, ": node %d link %d new node: %d",
-+					evt->node, evt->link, evt->newNode);
-+				dump_event_detail = 0;
-+				break;
-+			}
-+		case HT_EVENT_COH_MPCAP_MISMATCH:
-+			printk(log_level, "HT_EVENT_COH_MPCAP_MISMATCH");
-+			break;
-+		case HT_EVENT_NCOH_EVENTS:
-+			printk(log_level, "HT_EVENT_NCOH_EVENTS");
-+			break;
-+		case HT_EVENT_NCOH_BUID_EXCEED:
-+			printk(log_level, "HT_EVENT_NCOH_BUID_EXCEED");
-+			break;
-+		case HT_EVENT_NCOH_LINK_EXCEED:
-+			printk(log_level, "HT_EVENT_NCOH_LINK_EXCEED");
-+			break;
-+		case HT_EVENT_NCOH_BUS_MAX_EXCEED:
-+			printk(log_level, "HT_EVENT_NCOH_BUS_MAX_EXCEED");
-+			break;
-+		case HT_EVENT_NCOH_CFG_MAP_EXCEED:
-+			printk(log_level, "HT_EVENT_NCOH_CFG_MAP_EXCEED");
-+			break;
-+		case HT_EVENT_NCOH_DEVICE_FAILED:
-+			{
-+				printk(log_level, "HT_EVENT_NCOH_DEVICE_FAILED");
-+				sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0;
-+				printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d",
-+					evt->node, evt->link, evt->depth, evt->attemptedBUID);
-+				dump_event_detail = 0;
-+				break;
-+			}
-+		case HT_EVENT_NCOH_AUTO_DEPTH:
-+			{
-+				printk(log_level, "HT_EVENT_NCOH_AUTO_DEPTH");
-+				sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0;
-+				printk(log_level, ": node %d link %d depth: %d",
-+					evt->node, evt->link, evt->depth);
-+				dump_event_detail = 0;
-+				break;
-+			}
-+		case HT_EVENT_OPT_EVENTS:
-+			printk(log_level, "HT_EVENT_OPT_EVENTS");
-+			break;
-+		case HT_EVENT_OPT_REQUIRED_CAP_RETRY:
-+			printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_RETRY");
-+			break;
-+		case HT_EVENT_OPT_REQUIRED_CAP_GEN3:
-+			printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_GEN3");
-+			break;
-+		case HT_EVENT_HW_EVENTS:
-+			printk(log_level, "HT_EVENT_HW_EVENTS");
-+			break;
-+		case HT_EVENT_HW_SYNCHFLOOD:
-+			printk(log_level, "HT_EVENT_HW_SYNCHFLOOD");
-+			break;
-+		case HT_EVENT_HW_HTCRC:
-+			printk(log_level, "HT_EVENT_HW_HTCRC");
-+			break;
-+		default:
-+			printk(log_level, "HT_EVENT_UNKNOWN");
-+			break;
-+	}
-+	printk(log_level, "\n");
-+
-+	if (dump_event_detail) {
-+		printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
-+
-+		for (i = 0; i < *pEventData0; i++) {
-+			printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
-+		}
-+		printk(BIOS_DEBUG, "\n");
-+	}
- }
- 
- /**
-@@ -208,9 +324,10 @@ static void amd_ht_fixup(struct sys_info *sysinfo) {
- 				for (node = 0; node < node_count; node++) {
- 					f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8);
- 					uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30);
--					printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number);
-+					printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link", node, internal_node_number);
- 					if (internal_node_number == 0) {
- 						uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x98:0xd8) & 0x1;
-+						printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected);
- 						if (package_link_3_connected) {
- 							/* Set WidthIn and WidthOut to 0 */
- 							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4);
-@@ -232,15 +349,21 @@ static void amd_ht_fixup(struct sys_info *sysinfo) {
- 						}
- 					} else if (internal_node_number == 1) {
- 						uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xf8:0xb8) & 0x1;
-+						printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected);
- 						if (package_link_3_connected) {
- 							/* Set WidthIn and WidthOut to 0 */
- 							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4);
- 							dword &= ~0x77000000;
- 							pci_write_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4, dword);
- 							/* Set Ganged to 1 */
--							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174);
-+							/* WARNING
-+							 * The Family 15h BKDG states that 0x18c should be set,
-+							 * however this is in error.  0x17c is the correct control
-+							 * register (sublink 0) for these processors...
-+							 */
-+							dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174);
- 							dword |= 0x00000001;
--							pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174, dword);
-+							pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174, dword);
- 						} else {
- 							/* Set ConnDly to 1 */
- 							dword = pci_read_config32(NODE_PCI(node, 0), 0x16c);
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 55cdd24..b7c8e83 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -5430,6 +5430,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc
- 		cpu_divisor = (0x1 << cpu_did);
- 		pMCTstat->TSCFreq = (100 * (cpu_fid + 0x10)) / cpu_divisor;
- 
-+		printk(BIOS_DEBUG, "mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15\n");
- 		mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat);
- 	} else {
- 		/* K10 BKDG v3.62 section 2.8.9.2 */
--- 
-1.7.9.5
-
diff --git a/resources/libreboot/patch/kgpe-d16/0092-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch b/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch
index 2c1a411..c43e297 100644
--- a/resources/libreboot/patch/kgpe-d16/0092-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch
+++ b/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch
@@ -1,23 +1,25 @@
-From 4875c65838b25b4338a023111fc667e9a9f314ca Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 65404b72da34b2f786af5fa1901531e50f59d0d7 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 2 Aug 2015 21:23:02 -0500
-Subject: [PATCH 092/146] northbridge/amd/amdmct/mct_ddr3: Move K10D
+Subject: [PATCH 090/139] northbridge/amd/amdmct/mct_ddr3: Move K10D
  configuration into separate file
 
+Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/raminit_amdmct.c  |    1 +
- src/northbridge/amd/amdmct/amddefs.h           |    5 +-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |  131 +++++++++++-------------
- src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c |    4 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctprod.c  |   65 ++++++++++++
- 5 files changed, 130 insertions(+), 76 deletions(-)
+ src/northbridge/amd/amdfam10/raminit_amdmct.c  |   1 +
+ src/northbridge/amd/amdmct/amddefs.h           |   5 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 133 ++++++++++++-------------
+ src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c |   4 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctprod.c  |  65 ++++++++++++
+ 5 files changed, 132 insertions(+), 76 deletions(-)
  create mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctprod.c
 
 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-index 4962c2a..ebd22cd 100644
+index cae228f..2cbe6b1 100644
 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
 +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
-@@ -370,6 +370,7 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
+@@ -379,6 +379,7 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
  #include "../amdmct/mct_ddr3/mctdqs_d.c"
  #include "../amdmct/mct_ddr3/mctsrc.c"
  #include "../amdmct/mct_ddr3/mctsdi.c"
@@ -54,7 +56,7 @@ index 7aa4698..60d3c16 100644
 \ No newline at end of file
 +#define AMD_PKGTYPE_C32 5
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index b7c8e83..4d8f3d0 100644
+index 0b61106..1167976 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -182,6 +182,7 @@ static void SyncSetting(struct DCTStatStruc *pDCTstat);
@@ -65,7 +67,7 @@ index b7c8e83..4d8f3d0 100644
  
  static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay,
  			uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
-@@ -2670,13 +2671,11 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
+@@ -2677,13 +2678,13 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
  	}
  
  	for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -76,6 +78,8 @@ index b7c8e83..4d8f3d0 100644
 -			dword = 0x0fe40fc0;	/* BKDG recommended */
 -		dword |= MCCH_FlushWrOnStpGnt;	/* Set for S3 */
 -		Set_NB32(pDCTstat->dev_dct, 0x11c, dword);
++		pDCTstat = pDCTstatA + Node;
++
 +		/* Enable prefetchers */
 +		dword = Get_NB32(pDCTstat->dev_dct, 0x11c);	/* Memory Controller Configuration High */
 +		dword &= ~(0x1 << 13);				/* PrefIoDis = 0 */
@@ -84,7 +88,7 @@ index b7c8e83..4d8f3d0 100644
  	}
  }
  
-@@ -4914,31 +4913,33 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
+@@ -4925,31 +4926,33 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat,
  	Get_TrwtTO(pMCTstat, pDCTstat, dct);
  	Get_TrwtWB(pMCTstat, pDCTstat);
  
@@ -143,7 +147,7 @@ index b7c8e83..4d8f3d0 100644
  }
  
  static void Get_Trdrd(struct MCTStatStruc *pMCTstat,
-@@ -4949,6 +4950,8 @@ static void Get_Trdrd(struct MCTStatStruc *pMCTstat,
+@@ -4960,6 +4963,8 @@ static void Get_Trdrd(struct MCTStatStruc *pMCTstat,
  	Trdrd = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 1;
  	if (Trdrd > 8)
  		Trdrd = 8;
@@ -152,7 +156,7 @@ index b7c8e83..4d8f3d0 100644
  	pDCTstat->Trdrd = Trdrd;
  }
  
-@@ -5259,47 +5262,31 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -5270,47 +5275,31 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  		if (pDCTstat->NodePresent) {
  			mct_PhyController_Config(pMCTstat, pDCTstat, 0);
  			mct_PhyController_Config(pMCTstat, pDCTstat, 1);
@@ -222,7 +226,7 @@ index b7c8e83..4d8f3d0 100644
  				uint8_t wm1;
  				uint8_t wm2;
  
-@@ -5330,11 +5317,11 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -5341,11 +5330,11 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  					break;
  				}
  
@@ -330,5 +334,5 @@ index 0000000..2b62d4c
 +	}
 +}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0093-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch b/resources/libreboot/patch/kgpe-d16/0091-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch
index e360ec8..82d8664 100644
--- a/resources/libreboot/patch/kgpe-d16/0093-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch
+++ b/resources/libreboot/patch/kgpe-d16/0091-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch
@@ -1,14 +1,16 @@
-From 0f4787f41f98a2f4529ec5eff5562fb52649e9d3 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 201dd98f77ab10c305a0a165494f3e10cc105d5d Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 2 Aug 2015 21:28:31 -0500
-Subject: [PATCH 093/146] mainboard/asus/kgpe-d16: Fix I/O link detection
+Subject: [PATCH 091/139] mainboard/asus/kgpe-d16: Fix I/O link detection
 
+Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/romstage.c |    3 ++-
+ src/mainboard/asus/kgpe-d16/romstage.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
-index acc8308..13fb485 100644
+index 3504126..2b222f5 100644
 --- a/src/mainboard/asus/kgpe-d16/romstage.c
 +++ b/src/mainboard/asus/kgpe-d16/romstage.c
 @@ -552,7 +552,8 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
@@ -22,5 +24,5 @@ index acc8308..13fb485 100644
  		return 1;
  	}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0094-cpu-amd-model_10xxx-Set-northbridge-throttle-values.patch b/resources/libreboot/patch/kgpe-d16/0092-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch
index fda9408..2f8039b 100644
--- a/resources/libreboot/patch/kgpe-d16/0094-cpu-amd-model_10xxx-Set-northbridge-throttle-values.patch
+++ b/resources/libreboot/patch/kgpe-d16/0092-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch
@@ -1,17 +1,20 @@
-From c6ca802a248f85f59723fbbc14aaa0c49165dbc5 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 0e421105b63947e3a3dcbf7bf970e17af4519e6c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 2 Aug 2015 21:31:17 -0500
-Subject: [PATCH 094/146] cpu/amd/model_10xxx: Set northbridge throttle values
+Subject: [PATCH 092/139] cpu/amd/family_10h-family_15h: Set northbridge
+ throttle values
 
+Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/init_cpus.c        |   21 +--------
- src/cpu/amd/model_10xxx/model_10xxx_init.c |   66 ++++++++++++++++++++++++++++
+ src/cpu/amd/family_10h-family_15h/init_cpus.c      | 21 +------
+ .../amd/family_10h-family_15h/model_10xxx_init.c   | 66 ++++++++++++++++++++++
  2 files changed, 67 insertions(+), 20 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index f716e07..6122acd 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 2bc54dc..9aadbcf 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -877,6 +877,7 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
  		else
  			linktype |= HTPHY_LINKTYPE_UNGANGED;
@@ -47,10 +50,10 @@ index f716e07..6122acd 100644
  	/* Revision C0 and above */
  	if (revision & AMD_OR_C0) {
  		uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc);
-diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
+diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
 index 8a61f13..7319539 100644
---- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
-+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
+--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
++++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
 @@ -54,6 +54,28 @@ static inline uint8_t is_fam15h(void)
  	return fam15h;
  }
@@ -132,5 +135,5 @@ index 8a61f13..7319539 100644
  	msr = rdmsr(NB_CFG_MSR);
  	msr.hi &= ~(1 << (46 - 32));
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch b/resources/libreboot/patch/kgpe-d16/0093-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch
index 842202e..b446e30 100644
--- a/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch
+++ b/resources/libreboot/patch/kgpe-d16/0093-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch
@@ -1,17 +1,19 @@
-From 6212e218fbd616d7ddeb74fffd883741ba40a6d6 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From a50e4e220003702aaa83f8b852aa819975e07788 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 2 Aug 2015 21:31:48 -0500
-Subject: [PATCH 095/146] cpu/amd/model_10xxx: Fix incorrect revision
+Subject: [PATCH 093/139] cpu/amd/family_10h-family_15h: Fix incorrect revision
  detection
 
+Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/fidvid.c |   10 +++++-----
+ src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +++++-----
  1 file changed, 5 insertions(+), 5 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
-index fe1cfb4..1d55275 100644
---- a/src/cpu/amd/model_10xxx/fidvid.c
-+++ b/src/cpu/amd/model_10xxx/fidvid.c
+diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
+index 471456a..ed8cafa 100644
+--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
 @@ -375,7 +375,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
  	pci_write_config32(dev, 0xd8, dtemp);
  }
@@ -58,5 +60,5 @@ index fe1cfb4..1d55275 100644
  		/* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */
  		pci_write_config32(dev, 0x80, 0xe20be281);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0096-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch b/resources/libreboot/patch/kgpe-d16/0094-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch
index c14e469..55957a1 100644
--- a/resources/libreboot/patch/kgpe-d16/0096-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch
+++ b/resources/libreboot/patch/kgpe-d16/0094-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch
@@ -1,23 +1,25 @@
-From 5f98c8dc52acec481b51efa118af100351812241 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 60d2c9d712e8d53b871961ca50d1a9d06a65051f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 2 Aug 2015 21:36:24 -0500
-Subject: [PATCH 096/146] northbridge/amd/amdht: Add support for HT3 2.8GHz
- and up link frequencies
+Subject: [PATCH 094/139] northbridge/amd/amdht: Add support for HT3 2.8GHz and
+ up link frequencies
 
+Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/defaults.h      |    8 ++-
- src/mainboard/asus/kgpe-d16/cmos.layout |   30 ++++-----
- src/northbridge/amd/amdht/h3ffeat.h     |    6 +-
- src/northbridge/amd/amdht/h3finit.c     |   93 ++++++++++++++++-----------
- src/northbridge/amd/amdht/h3finit.h     |   18 ++++--
- src/northbridge/amd/amdht/h3ncmn.c      |  104 ++++++++++++++++++++++++-------
- src/northbridge/amd/amdht/h3ncmn.h      |    3 +-
+ src/cpu/amd/family_10h-family_15h/defaults.h |   8 ++-
+ src/mainboard/asus/kgpe-d16/cmos.layout      |  30 ++++----
+ src/northbridge/amd/amdht/h3ffeat.h          |   6 +-
+ src/northbridge/amd/amdht/h3finit.c          |  93 ++++++++++++++----------
+ src/northbridge/amd/amdht/h3finit.h          |  18 +++--
+ src/northbridge/amd/amdht/h3ncmn.c           | 104 ++++++++++++++++++++-------
+ src/northbridge/amd/amdht/h3ncmn.h           |   3 +-
  7 files changed, 177 insertions(+), 85 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index 1080cfc..bff2efd 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -290,7 +290,13 @@ static const struct {
  
  	/* Link Global Retry Control Register */
@@ -555,5 +557,5 @@ index 7f8f4d1..5795e9a 100644
  	void (*setLinkData)(sMainData *pDat, cNorthBridge *nb);
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0097-amd-model_10xxx-Fix-poor-performance-on-Family-15h-C.patch b/resources/libreboot/patch/kgpe-d16/0095-amd-family_10h-family_15h-Fix-poor-performance-on-Fa.patch
index 9f21a62..2cb270a 100644
--- a/resources/libreboot/patch/kgpe-d16/0097-amd-model_10xxx-Fix-poor-performance-on-Family-15h-C.patch
+++ b/resources/libreboot/patch/kgpe-d16/0095-amd-family_10h-family_15h-Fix-poor-performance-on-Fa.patch
@@ -1,18 +1,20 @@
-From 4dbb7204da39a6f47acb6875538acb4880f3a49b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 7a203388d1cc86037723fb307efa37cfb9dd87ea Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 7 Aug 2015 19:04:49 -0500
-Subject: [PATCH 097/146] amd/model_10xxx: Fix poor performance on Family 15h
- CPUs
+Subject: [PATCH 095/139] amd/family_10h-family_15h: Fix poor performance on
+ Family 15h CPUs
 
+Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/defaults.h  |   13 +++++++---
- src/cpu/amd/model_10xxx/init_cpus.c |   45 ++++++++++++++++++++++++++++++++---
+ src/cpu/amd/family_10h-family_15h/defaults.h  | 13 ++++++--
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 45 +++++++++++++++++++++++++--
  2 files changed, 52 insertions(+), 6 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index bff2efd..4868c5c 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -535,15 +535,15 @@ static const struct {
  	{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
  	  0x00800756, 0x00F3FFFF },
@@ -46,10 +48,10 @@ index bff2efd..4868c5c 100644
  	/* ACPI Power State Control Reg1 */
  	{ 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
  	  0xE6002200, 0xFFFFFFFF },
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 6122acd..15ed259 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 9aadbcf..d1a93e7 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -847,8 +847,9 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
   */
  static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
@@ -77,7 +79,7 @@ index 6122acd..15ed259 100644
  			linktype |= HTPHY_LINKTYPE_HT3;
  		else
  			linktype |= HTPHY_LINKTYPE_HT1;
-@@ -1147,6 +1153,39 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1150,6 +1156,39 @@ static void cpuSetAMDPCI(u8 node)
  		pci_write_config32(NODE_PCI(node, 3), 0xd4, dword);
  	}
  
@@ -86,7 +88,7 @@ index 6122acd..15ed259 100644
 +		uint8_t cu_enabled;
 +		uint8_t compute_unit_count = 0;
 +		uint8_t compute_unit_buffer_count;
-+		
++
 +		/* Determine the number of active compute units on this node */
 +		f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80);
 +		cu_enabled = f5x80 & 0xf;
@@ -118,5 +120,5 @@ index 6122acd..15ed259 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0098-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch b/resources/libreboot/patch/kgpe-d16/0096-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch
index 11d5471..0688150 100644
--- a/resources/libreboot/patch/kgpe-d16/0098-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch
+++ b/resources/libreboot/patch/kgpe-d16/0096-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch
@@ -1,20 +1,22 @@
-From 71ffed0eabd830bba3170a8d9a8bf9f735306a34 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 144073db29e770d85d01cbd6b093793aa951862f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 7 Aug 2015 19:05:29 -0500
-Subject: [PATCH 098/146] amd/amdmct/mct_ddr3: Fix poor performance on Family
+Subject: [PATCH 096/139] amd/amdmct/mct_ddr3: Fix poor performance on Family
  15h CPUs
 
+Change-Id: Ib6bc197e43e40ba2b923b1eb1229bacafc8be360
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |  370 ++++++++++++++++++++----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |    1 +
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   65 ++++-
- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c  |   49 +++-
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |  195 ++++++++++++-
- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    |    4 +
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 370 +++++++++++++++++++++----
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |   1 +
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |  65 ++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctproc.c  |  49 +++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   | 195 ++++++++++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    |   4 +
  6 files changed, 604 insertions(+), 80 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 4d8f3d0..539d0e8 100644
+index 1167976..2ca65ca 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -36,6 +36,8 @@
@@ -54,7 +56,7 @@ index 4d8f3d0..539d0e8 100644
  }
  
  static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds) {
-@@ -1996,6 +2003,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2002,6 +2009,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		/* Disable training mode */
  		uint8_t lane;
  		uint8_t dimm;
@@ -62,7 +64,7 @@ index 4d8f3d0..539d0e8 100644
  		uint8_t receiver;
  		uint8_t max_lane;
  		uint8_t ecc_enabled;
-@@ -2010,21 +2018,37 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2016,21 +2024,37 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		uint16_t twrwrdd;
  		uint16_t cdd_twrwrdd;
  		uint16_t twrrd;
@@ -100,7 +102,7 @@ index 4d8f3d0..539d0e8 100644
  		ecc_enabled = !!(pMCTstat->GStatus & 1 << GSB_ECCDIMMs);
  		if (ecc_enabled)
  			max_lane = 9;
-@@ -2058,6 +2082,24 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2064,6 +2088,24 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		else
  			write_odt_delay = 0;
  
@@ -113,7 +115,7 @@ index 4d8f3d0..539d0e8 100644
 +
 +		if (pDCTstat->Status & (1 << SB_LoadReduced)) {
 +			/* LRDIMM */
-+	
++
 +			/* TODO
 +			 * Implement LRDIMM support
 +			 * See Fam15h BKDG Rev. 3.14 section 2.10.5.5
@@ -125,7 +127,7 @@ index 4d8f3d0..539d0e8 100644
  		/* TODO:
  		 * Adjust trdrdsddc if four-rank DIMMs are installed per
  		 * section 2.10.5.5.1 of the Family 15h BKDG.
-@@ -2093,7 +2135,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2099,7 +2141,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		}
  
  		/* Convert the difference to MEMCLKs */
@@ -134,7 +136,7 @@ index 4d8f3d0..539d0e8 100644
  
  		/* Calculate Trdrddd */
  		delay = (read_odt_delay + 3) * 2;
-@@ -2140,7 +2182,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2145,7 +2187,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		}
  
  		/* Convert the difference to MEMCLKs */
@@ -143,7 +145,7 @@ index 4d8f3d0..539d0e8 100644
  
  		/* Calculate Twrwrdd */
  		delay = (write_odt_delay + 3) * 2;
-@@ -2159,6 +2201,107 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2164,6 +2206,107 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		dword &= ~(0x1 << 18);					/* DisAutoRefresh = 0 */
  		Set_NB32_DCT(dev, dct, 0x8c, dword);			/* DRAM Timing High */
  
@@ -251,7 +253,7 @@ index 4d8f3d0..539d0e8 100644
  		dword = Get_NB32_DCT(dev, dct, 0x94);			/* DRAM Configuration High */
  		dword |= (0xf << 24);					/* DcqBypassMax = 0xf */
  		dword |= (0x1 << 22);					/* BankSwizzleMode = 1 */
-@@ -2211,15 +2354,98 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2216,15 +2359,98 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  			}
  		}
  
@@ -291,7 +293,7 @@ index 4d8f3d0..539d0e8 100644
 +		/* Fam15h BKDG section 2.10.5.5.3 */
 +		if (pDCTstat->Status & (1 << SB_LoadReduced)) {
 +			/* LRDIMM */
-+	
++
 +			/* TODO
 +			 * Implement LRDIMM support
 +			 * See Fam15h BKDG Rev. 3.14 section 2.10.5.5
@@ -358,7 +360,7 @@ index 4d8f3d0..539d0e8 100644
  
  		dword = Get_NB32_DCT(dev, dct, 0xa4);			/* DRAM Controller Temperature Throttle */
  		dword &= ~(0x1 << 11);					/* BwCapEn = 0 */
-@@ -2230,6 +2456,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2235,6 +2461,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		dword = Get_NB32_DCT(dev, dct, 0x110);			/* DRAM Controller Select Low */
  		dword &= ~(0x1 << 2);					/* DctSelIntLvEn = interleave_channels */
  		dword |= (interleave_channels & 0x1) << 2;
@@ -366,7 +368,7 @@ index 4d8f3d0..539d0e8 100644
  		Set_NB32_DCT(dev, dct, 0x110, dword);			/* DRAM Controller Select Low */
  
  		/* NOTE
-@@ -2237,22 +2464,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2242,22 +2469,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		 * otherwise semi-random lockups will occur due to misconfigured scrubbing hardware!
  		 */
  
@@ -389,7 +391,7 @@ index 4d8f3d0..539d0e8 100644
  		/* Fam15h BKDG section 2.10.5.5.2 */
  		dword = Get_NB32_DCT(dev, dct, 0x214);			/* DRAM Timing 4 */
  		dword &= ~(0xf << 16);					/* TwrwrSdSc = 0x1 */
-@@ -2265,8 +2476,14 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2270,8 +2481,14 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  
  		/* Fam15h BKDG section 2.10.5.5.3 */
  		dword = Get_NB32_DCT(dev, dct, 0x218);			/* DRAM Timing 5 */
@@ -404,7 +406,7 @@ index 4d8f3d0..539d0e8 100644
  		Set_NB32_DCT(dev, dct, 0x218, dword);			/* DRAM Timing 5 */
  
  		/* Fam15h BKDG section 2.10.5.5.4 */
-@@ -2277,12 +2494,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2282,12 +2499,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		dword |= ((((dword >> 8) & 0x1f) + 1) << 16);
  		Set_NB32_DCT(dev, dct, 0x21c, dword);			/* DRAM Timing 6 */
  
@@ -417,7 +419,7 @@ index 4d8f3d0..539d0e8 100644
  		/* Enable prefetchers */
  		dword = Get_NB32(dev, 0x11c);				/* Memory Controller Configuration High */
  		dword &= ~(0x1 << 13);					/* PrefIoDis = 0 */
-@@ -2371,6 +2582,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+@@ -2376,6 +2587,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
  
  		mct_TrainDQSPos_D(pMCTstat, pDCTstatA);
  
@@ -426,7 +428,7 @@ index 4d8f3d0..539d0e8 100644
  		if (is_fam15h())
  			exit_training_mode_fam15(pMCTstat, pDCTstatA);
  		else
-@@ -2944,6 +3157,13 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat,
+@@ -2953,6 +3166,13 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat,
  	}
  
  	while(reg < reg_end) {
@@ -440,7 +442,7 @@ index 4d8f3d0..539d0e8 100644
  		if ((reg & 0xFF) == 0x90) {
  			if (pDCTstat->LogicalCPUID & AMD_DR_Dx) {
  				val = Get_NB32_DCT(dev, dct, reg); /* get DRAMConfigLow */
-@@ -3062,14 +3282,30 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3071,14 +3291,30 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  
  	/* Convert  DRAM CycleTiming values and store into DCT structure */
  	byte = pDCTstat->DIMMAutoSpeed;
@@ -479,7 +481,7 @@ index 4d8f3d0..539d0e8 100644
  
  	/* Notes:
  	 1. All secondary time values given in SPDs are in binary with units of ns.
-@@ -3102,7 +3338,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3111,7 +3347,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  		val = Max_TrpT;
  	pDCTstat->Trp = val;
  
@@ -488,7 +490,7 @@ index 4d8f3d0..539d0e8 100644
  	pDCTstat->DIMMTrrd = Trrd;
  	val = Trrd / tCK16x;
  	if (Trrd % tCK16x) {	/* round up number of busclocks */
-@@ -3220,21 +3456,31 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3229,21 +3465,31 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  
  		dword = Get_NB32_DCT(dev, dct, 0x200);				/* DRAM Timing 0 */
  		dword &= ~(0x3f1f1f1f);
@@ -528,7 +530,7 @@ index 4d8f3d0..539d0e8 100644
  		dword = Get_NB32_DCT(dev, dct, 0x208);				/* DRAM Timing 2 */
  		dword &= ~(0x07070707);
  		dword |= (pDCTstat->Trfc[3] & 0x7) << 24;			/* Trfc3 */
-@@ -3245,14 +3491,14 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3254,14 +3500,14 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  
  		dword = Get_NB32_DCT(dev, dct, 0x20c);				/* DRAM Timing 3 */
  		dword &= ~(0x00000f00);
@@ -545,7 +547,7 @@ index 4d8f3d0..539d0e8 100644
  		Set_NB32_DCT(dev, dct, 0x22c, dword);				/* DRAM Timing 10 */
  
  		if (pDCTstat->Speed > mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
-@@ -3848,6 +4094,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3857,6 +4103,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  		}
  	}
  
@@ -554,7 +556,7 @@ index 4d8f3d0..539d0e8 100644
  	printk(BIOS_DEBUG, "AutoConfig_D: DramControl:     %08x\n", DramControl);
  	printk(BIOS_DEBUG, "AutoConfig_D: DramTimingLo:    %08x\n", DramTimingLo);
  	printk(BIOS_DEBUG, "AutoConfig_D: DramConfigMisc:  %08x\n", DramConfigMisc);
-@@ -3859,7 +4107,6 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
+@@ -3868,7 +4116,6 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
  	Set_NB32_DCT(dev, dct, 0x78, DramControl);
  	Set_NB32_DCT(dev, dct, 0x88, DramTimingLo);
  	Set_NB32_DCT(dev, dct, 0xa0, DramConfigMisc);
@@ -562,7 +564,7 @@ index 4d8f3d0..539d0e8 100644
  	Set_NB32_DCT(dev, dct, 0xa8, DramConfigMisc2);
  	Set_NB32_DCT(dev, dct, 0x90, DramConfigLo);
  	ProgDramMRSReg_D(pMCTstat, pDCTstat, dct);
-@@ -5226,6 +5473,16 @@ static void mct_PhyController_Config(struct MCTStatStruc *pMCTstat,
+@@ -5239,6 +5486,16 @@ static void mct_PhyController_Config(struct MCTStatStruc *pMCTstat,
  	u32 dev = pDCTstat->dev_dct;
  
  	if (pDCTstat->LogicalCPUID & (AMD_DR_DAC2_OR_C3 | AMD_RB_C3 | AMD_FAM15_ALL)) {
@@ -579,7 +581,7 @@ index 4d8f3d0..539d0e8 100644
  		if (pDCTstat->Dimmx4Present == 0) {
  			/* Set bit7 RxDqsUDllPowerDown to register F2x[1, 0]98_x0D0F0F13 for
  			 * additional power saving when x4 DIMMs are not present.
-@@ -5270,8 +5527,9 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -5283,8 +5540,9 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  				mct_ExtMCTConfig_Dx(pDCTstat);
  			} else {
  				/* Family 15h CPUs */
@@ -591,7 +593,7 @@ index 4d8f3d0..539d0e8 100644
  				Set_NB32(pDCTstat->dev_dct, 0x11c, val);
  
  				val = Get_NB32(pDCTstat->dev_dct, 0x1b0);
-@@ -6511,8 +6769,8 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
+@@ -6524,8 +6782,8 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
  
  	dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84);
  	if (is_fam15h()) {
@@ -614,7 +616,7 @@ index 486b16c..ec5658e 100644
  void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
  void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index bc9ac4b..eedff67 100644
+index c70fa6d..c520515 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -24,6 +24,9 @@ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_
@@ -765,7 +767,7 @@ index bc9ac4b..eedff67 100644
  					/* Calculate and program MaxRdLatency */
 -					Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct);
 +					Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0);
- 	
+ 
  					/* 2.10.5.8.3 (4 B) */
  					dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1);
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -848,10 +850,10 @@ index 738304e..3da28b3 100644
  		val = ((~val) & 0xff) + 1;
  		val += 6;
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index 3af3eb2..b71b327 100644
+index 707e6a9..3ede104 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-@@ -1425,7 +1425,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
+@@ -1424,7 +1424,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
  	}
  
  	/* Calculate and program MaxRdLatency */
@@ -860,7 +862,7 @@ index 3af3eb2..b71b327 100644
  
  	if(_DisableDramECC) {
  		mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
-@@ -1488,6 +1488,199 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
+@@ -1487,6 +1487,199 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
  	printk(BIOS_DEBUG, "TrainRcvrEn: Done\n\n");
  }
  
@@ -1083,5 +1085,5 @@ index 3153e46..28cc8f6 100644
  
  /*
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0099-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch b/resources/libreboot/patch/kgpe-d16/0097-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch
index 32121d3..57d5ede 100644
--- a/resources/libreboot/patch/kgpe-d16/0099-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch
+++ b/resources/libreboot/patch/kgpe-d16/0097-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch
@@ -1,11 +1,13 @@
-From e4453fd27b842d13276b0e043280031de7f52140 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From b9bcbf70cef87afd830e156d5081839fc066b89c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 7 Aug 2015 19:05:45 -0500
-Subject: [PATCH 099/146] northbridge/amd/amdht: Fix poor performance on
- Family 15h CPUs
+Subject: [PATCH 097/139] northbridge/amd/amdht: Fix poor performance on Family
+ 15h CPUs
 
+Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdht/h3ncmn.c |    4 ++++
+ src/northbridge/amd/amdht/h3ncmn.c | 4 ++++
  1 file changed, 4 insertions(+)
 
 diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
@@ -24,5 +26,5 @@ index e03e5eb..e377ff2 100644
  				AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2);
  			AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch b/resources/libreboot/patch/kgpe-d16/0098-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch
index 014029d..f107a68 100644
--- a/resources/libreboot/patch/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch
+++ b/resources/libreboot/patch/kgpe-d16/0098-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch
@@ -1,12 +1,14 @@
-From 3a8253f5cd0093c33294f8c8399acaa60100b880 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 4d494c630bc75c675cae9cae68d6d0b44fcd1e22 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 7 Aug 2015 19:06:09 -0500
-Subject: [PATCH 100/146] northbridge/amd/amdfam10: Fix poor performance on
+Subject: [PATCH 098/139] northbridge/amd/amdfam10: Fix poor performance on
  Family 15h CPUs
 
+Change-Id: I193749bc767b7c1139de7cd67622a7b03298009b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/nb_control.c  |    4 ++--
- src/northbridge/amd/amdfam10/northbridge.c |   21 +++++++++++++++++++++
+ src/northbridge/amd/amdfam10/nb_control.c  |  4 ++--
+ src/northbridge/amd/amdfam10/northbridge.c | 21 +++++++++++++++++++++
  2 files changed, 23 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c
@@ -27,10 +29,10 @@ index f95b6f8..8e8dd57 100644
  	printk(BIOS_DEBUG, "done.\n");
  }
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index 2c8ee08..a60daf9 100644
+index cdb8afa..9f132c7 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -1755,6 +1755,8 @@ static void detect_and_enable_probe_filter(device_t dev)
+@@ -1759,6 +1759,8 @@ static void detect_and_enable_probe_filter(device_t dev)
  
  		disable_cache();
  		asm("wbinvd");
@@ -39,7 +41,7 @@ index 2c8ee08..a60daf9 100644
  		for (i = 0; i < sysconf.nodes; i++) {
  			device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
  
-@@ -1771,6 +1773,25 @@ static void detect_and_enable_probe_filter(device_t dev)
+@@ -1775,6 +1777,25 @@ static void detect_and_enable_probe_filter(device_t dev)
  			do {
  			} while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19)));
  		}
@@ -66,5 +68,5 @@ index 2c8ee08..a60daf9 100644
  
  		/* Reenable L3 and DRAM scrubbers */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0101-cpu-amd-model_10xxx-Configure-NB-register-2.patch b/resources/libreboot/patch/kgpe-d16/0099-cpu-amd-family_10h-family_15h-Configure-NB-register-.patch
index ba82f44..2cbd57e 100644
--- a/resources/libreboot/patch/kgpe-d16/0101-cpu-amd-model_10xxx-Configure-NB-register-2.patch
+++ b/resources/libreboot/patch/kgpe-d16/0099-cpu-amd-family_10h-family_15h-Configure-NB-register-.patch
@@ -1,16 +1,19 @@
-From 29c6cf2af61d3e131fc1c8bbcebe9335bcd2e776 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From fd637f3c6c5a176a18cf44bbd163dd61cabd8fb1 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 7 Aug 2015 23:58:28 -0500
-Subject: [PATCH 101/146] cpu/amd/model_10xxx: Configure NB register 2
+Subject: [PATCH 099/139] cpu/amd/family_10h-family_15h: Configure NB register
+ 2
 
+Change-Id: I55cfc96a197514212b2a4c344d3513396ebc2ad4
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/defaults.h |    8 ++++++++
+ src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++
  1 file changed, 8 insertions(+)
 
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index 4868c5c..5ab4335 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -621,6 +621,14 @@ static const struct {
  					   [5] DisPciCfgCpuMstAbtRsp = 1,
  					   [1] SyncFloodOnUsPwDataErr = 1 */
@@ -27,5 +30,5 @@ index 4868c5c..5ab4335 100644
  	 *  System software should set F3x188[22] to 1b. */
  	{ 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0102-cpu-amd-model_10xxx-Set-up-link-XCS-token-counts-on-.patch b/resources/libreboot/patch/kgpe-d16/0100-cpu-amd-family_10h-family_15h-Set-up-link-XCS-token-.patch
index 4b746b8..d37c376 100644
--- a/resources/libreboot/patch/kgpe-d16/0102-cpu-amd-model_10xxx-Set-up-link-XCS-token-counts-on-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0100-cpu-amd-family_10h-family_15h-Set-up-link-XCS-token-.patch
@@ -1,18 +1,20 @@
-From 8cc7e05b370f7b24a694da4d30cfe719d45d6da9 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From e1db05e5568333c634db8052d4dc37d60b61121f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 7 Aug 2015 23:59:17 -0500
-Subject: [PATCH 102/146] cpu/amd/model_10xxx: Set up link XCS token counts on
- Family 15h
+Subject: [PATCH 100/139] cpu/amd/family_10h-family_15h: Set up link XCS token
+ counts on Family 15h
 
+Change-Id: I4cf6549234041c395a18a89332d95f20a596fc3e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/init_cpus.c |  304 +++++++++++++++++++++++++++++++++++
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 304 ++++++++++++++++++++++++++
  1 file changed, 304 insertions(+)
 
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 15ed259..7e39c6d 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
-@@ -1053,6 +1053,12 @@ static void cpuSetAMDPCI(u8 node)
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index d1a93e7..10c676f 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+@@ -1056,6 +1056,12 @@ static void cpuSetAMDPCI(u8 node)
  	uint32_t dword;
  	uint64_t revision;
  
@@ -25,11 +27,10 @@ index 15ed259..7e39c6d 100644
  	printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
  
  	revision = mctGetLogicalCPUID(node);
-@@ -1158,6 +1164,15 @@ static void cpuSetAMDPCI(u8 node)
- 		uint8_t cu_enabled;
+@@ -1162,6 +1168,15 @@ static void cpuSetAMDPCI(u8 node)
  		uint8_t compute_unit_count = 0;
  		uint8_t compute_unit_buffer_count;
-+
+ 
 +		uint32_t f3xe8;
 +		uint8_t dual_node = 0;
 +
@@ -38,10 +39,11 @@ index 15ed259..7e39c6d 100644
 +		/* Check for dual node capability */
 +		if (f3xe8 & 0x20000000)
 +			dual_node = 1;
- 		
++
  		/* Determine the number of active compute units on this node */
  		f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80);
-@@ -1184,6 +1199,295 @@ static void cpuSetAMDPCI(u8 node)
+ 		cu_enabled = f5x80 & 0xf;
+@@ -1187,6 +1202,295 @@ static void cpuSetAMDPCI(u8 node)
  		dword &= ~(0x1f << 4);			/* L3FreeListCBC = compute_unit_buffer_count */
  		dword |= (compute_unit_buffer_count << 4);
  		pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword);
@@ -338,5 +340,5 @@ index 15ed259..7e39c6d 100644
  
  	printk(BIOS_DEBUG, " done\n");
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch b/resources/libreboot/patch/kgpe-d16/0101-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch
index f7e950f..ef1533d 100644
--- a/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0101-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch
@@ -1,18 +1,20 @@
-From 71edc36237fef86f4ee712b1d6edc0191b38714c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From bb67f00d05bf8ff2d9643100878e3743302d43c1 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 7 Aug 2015 23:59:33 -0500
-Subject: [PATCH 103/146] northbridge/amd/amdmct/mct_ddr3: Force retraining on
+Subject: [PATCH 101/139] northbridge/amd/amdmct/mct_ddr3: Force retraining on
  every boot
 
+Change-Id: I017e0dd5120110124d5b5d5276befef6f7740614
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   10 ++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 10 ++++++++++
  1 file changed, 10 insertions(+)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 539d0e8..166cd3d 100644
+index 2ca65ca..330f37f 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1729,6 +1729,16 @@ restartinit:
+@@ -1735,6 +1735,16 @@ restartinit:
  					allow_config_restore = 0;
  		}
  
@@ -30,5 +32,5 @@ index 539d0e8..166cd3d 100644
  			struct DCTStatStruc *pDCTstat;
  			pDCTstat = pDCTstatA + Node;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0104-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch b/resources/libreboot/patch/kgpe-d16/0102-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch
index b81057a..a1d226e 100644
--- a/resources/libreboot/patch/kgpe-d16/0104-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch
+++ b/resources/libreboot/patch/kgpe-d16/0102-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch
@@ -1,10 +1,12 @@
-From 7998b24deb6711af2bea484fc010a163bfece9af Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 26dce9855e0edd8faae94f12d81ed59322d318ae Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 8 Aug 2015 02:40:58 -0500
-Subject: [PATCH 104/146] northbridge/amd/amdfam10: Fix invalid NUMA table
+Subject: [PATCH 102/139] northbridge/amd/amdfam10: Fix invalid NUMA table
 
+Change-Id: I99c200382b52a99687daf266a84873d9ae2df025
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/acpi.c |    3 ++-
+ src/northbridge/amd/amdfam10/acpi.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)
 
 diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
@@ -22,5 +24,5 @@ index 92433bb..23cf086 100644
  
  static unsigned long acpi_fill_srat(unsigned long current)
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0105-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch b/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch
index e838e00..15836d4 100644
--- a/resources/libreboot/patch/kgpe-d16/0105-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch
+++ b/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch
@@ -1,18 +1,20 @@
-From 6433fa7492f9fd6ff776af5e3db901fcc6f55136 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 1f667d55b99e81e636572d9f3ac9498ef782536c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 8 Aug 2015 20:29:27 -0500
-Subject: [PATCH 105/146] northbridge/amd/amdfam10: Add Family 15h cache
+Subject: [PATCH 103/139] northbridge/amd/amdfam10: Add Family 15h cache
  partitioning support
 
+Change-Id: Ie4e28dd886aaa1c586b0919c5fe87ef1696f47e9
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/northbridge.c |   94 ++++++++++++++++++++++++++++
+ src/northbridge/amd/amdfam10/northbridge.c | 94 ++++++++++++++++++++++++++++++
  1 file changed, 94 insertions(+)
 
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index a60daf9..74b8709 100644
+index 9f132c7..8ad5200 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -1805,9 +1805,103 @@ static void detect_and_enable_probe_filter(device_t dev)
+@@ -1809,9 +1809,103 @@ static void detect_and_enable_probe_filter(device_t dev)
  	}
  }
  
@@ -53,12 +55,12 @@ index a60daf9..74b8709 100644
 +				compute_unit_count = 3;
 +			if (cu_enabled == 0xf)
 +				compute_unit_count = 4;
-+	
++
 +			/* Disable BAN mode */
 +			dword = pci_read_config32(f3x_dev, 0x1b8);
 +			dword &= ~(0x7 << 19);	/* L3BanMode = 0x0 */
 +			pci_write_config32(f3x_dev, 0x1b8, dword);
-+	
++
 +			/* Set up cache mapping */
 +			dword = pci_read_config32(f4x_dev, 0x1d4);
 +			if (compute_unit_count == 1) {
@@ -89,7 +91,7 @@ index a60daf9..74b8709 100644
 +				dword |= 0x1;
 +			}
 +			pci_write_config32(f4x_dev, 0x1d4, dword);
-+	
++
 +			/* Enable cache partitioning */
 +			pci_write_config32(f4x_dev, 0x1d4, dword);
 +			if (compute_unit_count == 1) {
@@ -117,5 +119,5 @@ index a60daf9..74b8709 100644
  #if CONFIG_AMD_SB_CIMX
  	sb_After_Pci_Init();
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0106-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch b/resources/libreboot/patch/kgpe-d16/0104-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch
index 9454823..829e470 100644
--- a/resources/libreboot/patch/kgpe-d16/0106-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch
+++ b/resources/libreboot/patch/kgpe-d16/0104-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch
@@ -1,18 +1,20 @@
-From cd93f46100c1141dba544518c552645cc657406a Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From bcdb6fab80939ee9b9d599343460edcb31fd386f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 8 Aug 2015 20:29:55 -0500
-Subject: [PATCH 106/146] amd/amdmct/mct_ddr3: Set prefetch double stride to
+Subject: [PATCH 104/139] amd/amdmct/mct_ddr3: Set prefetch double stride to
  improve performance
 
+Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |    1 +
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 166cd3d..a9c148d 100644
+index 330f37f..de6c79c 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -5550,6 +5550,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -5563,6 +5563,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  				val &= ~(0x7 << 8);		/* CohPrefPrbLmt = 0x1 */
  				val |= (0x1 << 8);
  				val |= (0x1 << 12);		/* EnSplitDctLimits = 0x1 */
@@ -21,5 +23,5 @@ index 166cd3d..a9c148d 100644
  				val |= (0x7 << 25);		/* PrefFiveConf = 0x7 */
  				val &= ~(0xf << 28);		/* DcqBwThrotWm = 0x0 */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-model_10xxx-Set-up-Family-15h-Link-Base-Chan.patch b/resources/libreboot/patch/kgpe-d16/0105-cpu-amd-family_10h-family_15h-Set-up-Family-15h-Link.patch
index 1659deb..bcf7c48 100644
--- a/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-model_10xxx-Set-up-Family-15h-Link-Base-Chan.patch
+++ b/resources/libreboot/patch/kgpe-d16/0105-cpu-amd-family_10h-family_15h-Set-up-Family-15h-Link.patch
@@ -1,18 +1,20 @@
-From 20658b7ba96f2a132ef78bf7a57c6b714ee5a57b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 442969b0213becab817ad626597c1c7eeaf15ebc Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 8 Aug 2015 20:30:36 -0500
-Subject: [PATCH 107/146] cpu/amd/model_10xxx: Set up Family 15h Link Base
- Channel Buffer Count registers
+Subject: [PATCH 105/139] cpu/amd/family_10h-family_15h: Set up Family 15h Link
+ Base Channel Buffer Count registers
 
+Change-Id: I8d616a64a5a9cf0b51288535f5050c6866d0996b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/init_cpus.c |  159 ++++++++++++++++++++++++++++++++++-
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 159 +++++++++++++++++++++++++-
  1 file changed, 155 insertions(+), 4 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 7e39c6d..025fe10 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
-@@ -1200,6 +1200,161 @@ static void cpuSetAMDPCI(u8 node)
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 10c676f..63ad346 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+@@ -1203,6 +1203,161 @@ static void cpuSetAMDPCI(u8 node)
  		dword |= (compute_unit_buffer_count << 4);
  		pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword);
  
@@ -174,7 +176,7 @@ index 7e39c6d..025fe10 100644
  		/* Set up the Link to XCS Token Counts */
  		uint8_t isoc_rsp_tok_1;
  		uint8_t isoc_preq_tok_1;
-@@ -1217,10 +1372,6 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1220,10 +1375,6 @@ static void cpuSetAMDPCI(u8 node)
  		uint8_t preq_tok_0;
  		uint8_t req_tok_0;
  
@@ -186,5 +188,5 @@ index 7e39c6d..025fe10 100644
  			if (AMD_CpuFindCapability(node, link, &offset)) {
  				ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0108-cpu-amd-model_10xxx-Set-up-cache-controls-on-Family-.patch b/resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch
index 7720666..8cfb82c 100644
--- a/resources/libreboot/patch/kgpe-d16/0108-cpu-amd-model_10xxx-Set-up-cache-controls-on-Family-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch
@@ -1,17 +1,19 @@
-From 6b299238948c1cdde372472e3854a79eb6233564 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From c4c97a2bf72bf0547a6c587a7096620a0e28773d Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 8 Aug 2015 20:31:03 -0500
-Subject: [PATCH 108/146] cpu/amd/model_10xxx: Set up cache controls on Family
- 15h to improve performance
+Subject: [PATCH 106/139] cpu/amd/family_10h-family_15h: Set up cache controls
+ on Family 15h to improve performance
 
+Change-Id: I3df571d8091c07ac1ee29bf16b5a68585fa9eed4
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/defaults.h |   10 ++++++++--
+ src/cpu/amd/family_10h-family_15h/defaults.h | 10 ++++++++--
  1 file changed, 8 insertions(+), 2 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index 5ab4335..ce25b25 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -139,8 +139,9 @@ static const struct {
  	  0x00000000, 1 << (42-32)},	/* Bx [PwcDisableWalkerSharing]=1 */
  
@@ -37,5 +39,5 @@ index 5ab4335..ce25b25 100644
  
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0109-cpu-amd-model_10xxx-Set-up-SRI-to-XCS-Token-Count-re.patch b/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-family_10h-family_15h-Set-up-SRI-to-XCS-Toke.patch
index 434c3af..6d2c7e6 100644
--- a/resources/libreboot/patch/kgpe-d16/0109-cpu-amd-model_10xxx-Set-up-SRI-to-XCS-Token-Count-re.patch
+++ b/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-family_10h-family_15h-Set-up-SRI-to-XCS-Toke.patch
@@ -1,18 +1,20 @@
-From 3ed8b16993e2880820bb5115cd007e618daf02db Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From abac0edc90bff68cf30b60096c0db5214d8ef7f9 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sat, 8 Aug 2015 22:14:59 -0500
-Subject: [PATCH 109/146] cpu/amd/model_10xxx: Set up SRI to XCS Token Count
- registers on Family 15h
+Subject: [PATCH 107/139] cpu/amd/family_10h-family_15h: Set up SRI to XCS
+ Token Count registers on Family 15h
 
+Change-Id: Ic992efad11d8e231ec85c793cf1e478bea0b9d3e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/init_cpus.c |   40 +++++++++++++++++++++++++++++++++++
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 40 +++++++++++++++++++++++++++
  1 file changed, 40 insertions(+)
 
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 025fe10..3990dfc 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
-@@ -1639,6 +1639,46 @@ static void cpuSetAMDPCI(u8 node)
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 63ad346..115338e 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+@@ -1642,6 +1642,46 @@ static void cpuSetAMDPCI(u8 node)
  				pci_write_config32(NODE_PCI(node, 3), (link << 2) + 0x148, dword);
  			}
  		}
@@ -60,5 +62,5 @@ index 025fe10..3990dfc 100644
  
  	printk(BIOS_DEBUG, " done\n");
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0110-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch b/resources/libreboot/patch/kgpe-d16/0108-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch
index 59b8739..b160d2b 100644
--- a/resources/libreboot/patch/kgpe-d16/0110-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch
+++ b/resources/libreboot/patch/kgpe-d16/0108-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch
@@ -1,22 +1,24 @@
-From 7a1d7345b6840705dc4b32f7f6296975e2cdca50 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 4e4d10b69d13a3b15065bb2ee8f8c9b6a7d9ac89 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 9 Aug 2015 02:47:51 -0500
-Subject: [PATCH 110/146] amd/amdfam10: Control Family 15h cache partitioning
+Subject: [PATCH 108/139] amd/amdfam10: Control Family 15h cache partitioning
  and memory performance via nvram
 
+Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/defaults.h          |    5 ++---
- src/cpu/amd/model_10xxx/init_cpus.c         |   13 +++++++++++++
- src/mainboard/asus/kgpe-d16/cmos.default    |    3 +++
- src/mainboard/asus/kgpe-d16/cmos.layout     |    9 +++++++--
- src/northbridge/amd/amdfam10/northbridge.c  |   22 ++++++++++++++++++++++
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   11 ++++++++++-
+ src/cpu/amd/family_10h-family_15h/defaults.h  |  5 ++---
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 13 +++++++++++++
+ src/mainboard/asus/kgpe-d16/cmos.default      |  3 +++
+ src/mainboard/asus/kgpe-d16/cmos.layout       |  9 +++++++--
+ src/northbridge/amd/amdfam10/northbridge.c    | 22 ++++++++++++++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   | 11 ++++++++++-
  6 files changed, 57 insertions(+), 6 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index ce25b25..af59120 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -139,9 +139,8 @@ static const struct {
  	  0x00000000, 1 << (42-32)},	/* Bx [PwcDisableWalkerSharing]=1 */
  
@@ -29,16 +31,16 @@ index ce25b25..af59120 100644
  
  	{ EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL,
  	  0x00000000, 1 << (54-32),
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 3990dfc..faf5305 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 115338e..2234197 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -981,6 +981,13 @@ void cpuSetAMDMSR(uint8_t node_id)
  
  	/* Revision C0 and above */
  	if (revision & AMD_OR_C0) {
 +		uint8_t enable_experimental_memory_speed_boost;
-+	
++
 +		/* Check to see if cache partitioning is allowed */
 +		enable_experimental_memory_speed_boost = 0;
 +		if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS)
@@ -59,7 +61,7 @@ index 3990dfc..faf5305 100644
 +		}
  	}
  
- 	if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
+ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
 index 9b30b00..0a898bd 100644
 --- a/src/mainboard/asus/kgpe-d16/cmos.default
@@ -102,10 +104,10 @@ index ec803b6..010d4db 100644
  checksums
  
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index 74b8709..e374ed4 100644
+index 8ad5200..58b0079 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -1650,6 +1650,17 @@ static void detect_and_enable_probe_filter(device_t dev)
+@@ -1654,6 +1654,17 @@ static void detect_and_enable_probe_filter(device_t dev)
  {
  	uint32_t dword;
  
@@ -123,7 +125,7 @@ index 74b8709..e374ed4 100644
  	uint8_t fam15h = 0;
  	uint8_t rev_gte_d = 0;
  	uint8_t dual_node = 0;
-@@ -1810,6 +1821,17 @@ static void detect_and_enable_cache_partitioning(device_t dev)
+@@ -1814,6 +1825,17 @@ static void detect_and_enable_cache_partitioning(device_t dev)
  	uint8_t i;
  	uint32_t dword;
  
@@ -142,10 +144,10 @@ index 74b8709..e374ed4 100644
  		printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n");
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index a9c148d..b869647 100644
+index de6c79c..42630b9 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -5537,6 +5537,14 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -5550,6 +5550,14 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  				mct_ExtMCTConfig_Dx(pDCTstat);
  			} else {
  				/* Family 15h CPUs */
@@ -160,7 +162,7 @@ index a9c148d..b869647 100644
  				val = 0x0ce00f00;		/* FlushWrOnStpGnt = 0x0 */
  				val |= 0x10 << 2;		/* MctWrLimit = 0x10 */
  				val |= 0x1;			/* DctWrLimit = 0x1 */
-@@ -5550,7 +5558,8 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
+@@ -5563,7 +5571,8 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
  				val &= ~(0x7 << 8);		/* CohPrefPrbLmt = 0x1 */
  				val |= (0x1 << 8);
  				val |= (0x1 << 12);		/* EnSplitDctLimits = 0x1 */
@@ -171,5 +173,5 @@ index a9c148d..b869647 100644
  				val |= (0x7 << 25);		/* PrefFiveConf = 0x7 */
  				val &= ~(0xf << 28);		/* DcqBwThrotWm = 0x0 */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0111-northbridge-amd-amdht-Add-isochronous-setup-support-.patch b/resources/libreboot/patch/kgpe-d16/0109-northbridge-amd-amdht-Add-isochronous-setup-support-.patch
index f75f4c5..f4d5b49 100644
--- a/resources/libreboot/patch/kgpe-d16/0111-northbridge-amd-amdht-Add-isochronous-setup-support-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0109-northbridge-amd-amdht-Add-isochronous-setup-support-.patch
@@ -1,22 +1,24 @@
-From 98bfc674fb1fad135400503f6f3f4074b4fb7bfa Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From e94372dfb597ff2d28047e5d63d22ee33e1db0c7 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 11 Aug 2015 17:47:48 -0500
-Subject: [PATCH 111/146] northbridge/amd/amdht: Add isochronous setup support
+Subject: [PATCH 109/139] northbridge/amd/amdht: Add isochronous setup support
  for coherent fabric
 
+Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/init_cpus.c |   59 +++++++++++++++++++++++++++++++++++
- src/northbridge/amd/amdht/h3ffeat.h |    3 ++
- src/northbridge/amd/amdht/h3finit.c |   34 +++++++++++++++++++-
- src/northbridge/amd/amdht/h3finit.h |    4 ++-
- src/northbridge/amd/amdht/h3ncmn.c  |   26 +++++++++++++--
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 59 +++++++++++++++++++++++++++
+ src/northbridge/amd/amdht/h3ffeat.h           |  3 ++
+ src/northbridge/amd/amdht/h3finit.c           | 34 ++++++++++++++-
+ src/northbridge/amd/amdht/h3finit.h           |  4 +-
+ src/northbridge/amd/amdht/h3ncmn.c            | 26 +++++++++++-
  5 files changed, 122 insertions(+), 4 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index faf5305..0ac893a 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
-@@ -1694,6 +1694,65 @@ static void cpuSetAMDPCI(u8 node)
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 2234197..7a0701c 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+@@ -1697,6 +1697,65 @@ static void cpuSetAMDPCI(u8 node)
  		pci_write_config32(NODE_PCI(node, 3), 0x140, dword);
  	}
  
@@ -266,5 +268,5 @@ index e377ff2..841fc0c 100644
  			isFound = FALSE;
  			currentPtr = linkBase & (u32)0xFFFFF000; /* Set PCI Offset to 0 */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0112-arch-x86-acpi-Add-IVRS-table-generation-routines.patch b/resources/libreboot/patch/kgpe-d16/0110-arch-x86-acpi-Add-IVRS-table-generation-routines.patch
index 92e241c..ea7cd3a 100644
--- a/resources/libreboot/patch/kgpe-d16/0112-arch-x86-acpi-Add-IVRS-table-generation-routines.patch
+++ b/resources/libreboot/patch/kgpe-d16/0110-arch-x86-acpi-Add-IVRS-table-generation-routines.patch
@@ -1,11 +1,13 @@
-From e8145c0398d63b35ac486bacd181ef26cc7b8707 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From f84ae61b0b82097f318c96ee5c198cf9495568e2 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 11 Aug 2015 17:48:32 -0500
-Subject: [PATCH 112/146] arch/x86/acpi: Add IVRS table generation routines
+Subject: [PATCH 110/139] arch/x86/acpi: Add IVRS table generation routines
 
+Change-Id: Ia5d97d01dc9ddc45f81d998d126d592a915b4a75
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/arch/x86/acpi.c              |   25 +++++++++++++++++++++++++
- src/arch/x86/include/arch/acpi.h |   31 +++++++++++++++++++++++++++++++
+ src/arch/x86/acpi.c              | 25 +++++++++++++++++++++++++
+ src/arch/x86/include/arch/acpi.h | 31 +++++++++++++++++++++++++++++++
  2 files changed, 56 insertions(+)
 
 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
@@ -52,7 +54,7 @@ index 417a322..e73e5f2 100644
  {
  	acpi_hpet_t *hpet;
 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
-index 28f650c..47bb253 100644
+index 28f650c..7d583b8 100644
 --- a/src/arch/x86/include/arch/acpi.h
 +++ b/src/arch/x86/include/arch/acpi.h
 @@ -4,6 +4,7 @@
@@ -90,7 +92,7 @@ index 28f650c..47bb253 100644
 +	struct acpi_table_header header;
 +	uint32_t iv_info;
 +	uint32_t reserved[2];
-+	struct acpi_ivrs_ivhd ivhd; 
++	struct acpi_ivrs_ivhd ivhd;
 +} __attribute__ ((packed)) acpi_ivrs_t;
 +
  enum dev_scope_type {
@@ -115,5 +117,5 @@ index 28f650c..47bb253 100644
  void acpi_create_hpet(acpi_hpet_t *hpet);
  unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0113-southbridge-amd-sr5650-Add-IOMMU-support.patch b/resources/libreboot/patch/kgpe-d16/0111-southbridge-amd-sr5650-Add-IOMMU-support.patch
index 8550e61..54f04d0 100644
--- a/resources/libreboot/patch/kgpe-d16/0113-southbridge-amd-sr5650-Add-IOMMU-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0111-southbridge-amd-sr5650-Add-IOMMU-support.patch
@@ -1,14 +1,16 @@
-From c8e26ec0ca3beda98e31823466cc668aa453a083 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 274c926921dc0f24e15e09beed752f4927220fc6 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 11 Aug 2015 17:49:06 -0500
-Subject: [PATCH 113/146] southbridge/amd/sr5650: Add IOMMU support
+Subject: [PATCH 111/139] southbridge/amd/sr5650: Add IOMMU support
 
+Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/include/device/pci_ids.h             |    1 +
- src/southbridge/amd/sr5650/cmn.h         |    3 +
- src/southbridge/amd/sr5650/early_setup.c |   50 +++-
- src/southbridge/amd/sr5650/sr5650.c      |  479 +++++++++++++++++++++++++++++-
- src/southbridge/amd/sr5650/sr5650.h      |   14 +
+ src/include/device/pci_ids.h             |   1 +
+ src/southbridge/amd/sr5650/cmn.h         |   3 +
+ src/southbridge/amd/sr5650/early_setup.c |  50 +++-
+ src/southbridge/amd/sr5650/sr5650.c      | 479 ++++++++++++++++++++++++++++++-
+ src/southbridge/amd/sr5650/sr5650.h      |  14 +
  5 files changed, 537 insertions(+), 10 deletions(-)
 
 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
@@ -705,5 +707,5 @@ index ebbde41..a3518fb 100644
  void init_gen2(device_t nb_dev, device_t dev, u8 port);
  void sr56x0_lock_hwinitreg(void);
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch b/resources/libreboot/patch/kgpe-d16/0112-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch
index ed6ae69..a20b748 100644
--- a/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch
+++ b/resources/libreboot/patch/kgpe-d16/0112-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch
@@ -1,12 +1,14 @@
-From f2495e7909302bd8cbc0633bde5a9ce60a6336c5 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 95976a8660ad2acc7f4aca0665b195e53c53840c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 13 Aug 2015 17:45:12 -0500
-Subject: [PATCH 114/146] southbridge/amd/sr5650: Hide clock configuration
+Subject: [PATCH 112/139] southbridge/amd/sr5650: Hide clock configuration
  device after setup is complete
 
+Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sr5650/early_setup.c |   16 ++++++++--------
- src/southbridge/amd/sr5650/pcie.c        |    3 +++
+ src/southbridge/amd/sr5650/early_setup.c | 16 ++++++++--------
+ src/southbridge/amd/sr5650/pcie.c        |  3 +++
  2 files changed, 11 insertions(+), 8 deletions(-)
 
 diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
@@ -51,5 +53,5 @@ index 09ce217..360e9cb 100644
  
  /*****************************************
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0115-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch b/resources/libreboot/patch/kgpe-d16/0113-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch
index 2169d97..9e1a042 100644
--- a/resources/libreboot/patch/kgpe-d16/0115-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch
+++ b/resources/libreboot/patch/kgpe-d16/0113-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch
@@ -1,18 +1,20 @@
-From dc91a6e3bdbc54240b7a20ea133ba78c89bafa47 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 6fc24c6bf44b8ea2ad3ca43856500500aa0ffee7 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 11 Aug 2015 17:52:03 -0500
-Subject: [PATCH 115/146] northbridge/amd/amdfam10: Rename mislabeled iommu
+Subject: [PATCH 113/139] northbridge/amd/amdfam10: Rename mislabeled iommu
  nvram option to gart
 
+Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/misc_control.c |   12 ++++++------
+ src/northbridge/amd/amdfam10/misc_control.c | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)
 
 diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
-index 1057ac1..4710876 100644
+index 703ae51..1df570c 100644
 --- a/src/northbridge/amd/amdfam10/misc_control.c
 +++ b/src/northbridge/amd/amdfam10/misc_control.c
-@@ -43,7 +43,7 @@
+@@ -42,7 +42,7 @@
   *
   * @param dev
   *
@@ -21,7 +23,7 @@ index 1057ac1..4710876 100644
   * the northbridge of BSP.
   *
   * The same trick can be used to augment legacy VGA resources which can
-@@ -55,7 +55,7 @@
+@@ -54,7 +54,7 @@
  static void mcf3_read_resources(device_t dev)
  {
  	struct resource *resource;
@@ -30,7 +32,7 @@ index 1057ac1..4710876 100644
  	/* Read the generic PCI resources */
  	pci_dev_read_resources(dev);
  
-@@ -64,13 +64,13 @@ static void mcf3_read_resources(device_t dev)
+@@ -63,13 +63,13 @@ static void mcf3_read_resources(device_t dev)
  		return;
  	}
  
@@ -49,5 +51,5 @@ index 1057ac1..4710876 100644
  		resource->gran  = log2(resource->size);
  		resource->limit = 0xffffffff; /* 4G */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0116-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch b/resources/libreboot/patch/kgpe-d16/0114-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch
index 3427889..e7f0b9e 100644
--- a/resources/libreboot/patch/kgpe-d16/0116-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0114-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch
@@ -1,18 +1,20 @@
-From e63ed74fba45c969ebad74153c4644bcfb6229da Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 215348b2c83c3f1464b0c4d318e5ff6318d82a02 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 11 Aug 2015 17:52:31 -0500
-Subject: [PATCH 116/146] northbridge/amd/amdfam10: Fix gart setup not working
+Subject: [PATCH 114/139] northbridge/amd/amdfam10: Fix gart setup not working
  on Family 15h processors
 
+Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/misc_control.c |   34 ++++++++++++++++++++-------
+ src/northbridge/amd/amdfam10/misc_control.c | 34 ++++++++++++++++++++++-------
  1 file changed, 26 insertions(+), 8 deletions(-)
 
 diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
-index 4710876..61cf1b6 100644
+index 1df570c..4b62c69 100644
 --- a/src/northbridge/amd/amdfam10/misc_control.c
 +++ b/src/northbridge/amd/amdfam10/misc_control.c
-@@ -78,7 +78,7 @@ static void mcf3_read_resources(device_t dev)
+@@ -77,7 +77,7 @@ static void mcf3_read_resources(device_t dev)
  	}
  }
  
@@ -21,7 +23,7 @@ index 4710876..61cf1b6 100644
  {
  	struct resource *resource;
  
-@@ -98,7 +98,7 @@ static void set_agp_aperture(device_t dev)
+@@ -97,7 +97,7 @@ static void set_agp_aperture(device_t dev)
  
  		/* Update the other northbriges */
  		pdev = 0;
@@ -30,7 +32,7 @@ index 4710876..61cf1b6 100644
  			/* Store the GART size but don't enable it */
  			pci_write_config32(pdev, 0x90, gart_acr);
  
-@@ -114,10 +114,19 @@ static void set_agp_aperture(device_t dev)
+@@ -113,10 +113,19 @@ static void set_agp_aperture(device_t dev)
  	}
  }
  
@@ -52,7 +54,7 @@ index 4710876..61cf1b6 100644
  
  	/* Set the generic PCI resources */
  	pci_dev_set_resources(dev);
-@@ -156,9 +165,18 @@ static void misc_control_init(struct device *dev)
+@@ -155,9 +164,18 @@ static void misc_control_init(struct device *dev)
  }
  
  
@@ -73,7 +75,7 @@ index 4710876..61cf1b6 100644
  	.enable_resources = pci_dev_enable_resources,
  	.init             = misc_control_init,
  	.scan_bus         = 0,
-@@ -166,13 +184,13 @@ static struct device_operations mcf3_ops  = {
+@@ -165,13 +183,13 @@ static struct device_operations mcf3_ops  = {
  };
  
  static const struct pci_driver mcf3_driver __pci_driver = {
@@ -90,5 +92,5 @@ index 4710876..61cf1b6 100644
  	.device = 0x1603,
  };
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0117-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch b/resources/libreboot/patch/kgpe-d16/0115-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch
index 05b5bb8..ba0f218 100644
--- a/resources/libreboot/patch/kgpe-d16/0117-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch
+++ b/resources/libreboot/patch/kgpe-d16/0115-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch
@@ -1,15 +1,17 @@
-From fa09be02971b05b8031ebc372ab778613d25da7f Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 7b3c144695ecc58a7bfc35215fd2933aea0051e1 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 11 Aug 2015 17:53:45 -0500
-Subject: [PATCH 117/146] mainboard/asus/kgpe-d16: Add several nvram
+Subject: [PATCH 115/139] mainboard/asus/kgpe-d16: Add several nvram
  configuration options
 
+Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/acpi_tables.c |   37 +++++++++++++++++++++++++++++
- src/mainboard/asus/kgpe-d16/cmos.default  |    3 ++-
- src/mainboard/asus/kgpe-d16/cmos.layout   |    7 +++---
- src/mainboard/asus/kgpe-d16/devicetree.cb |    1 +
- src/mainboard/asus/kgpe-d16/romstage.c    |    2 ++
+ src/mainboard/asus/kgpe-d16/acpi_tables.c | 37 +++++++++++++++++++++++++++++++
+ src/mainboard/asus/kgpe-d16/cmos.default  |  3 ++-
+ src/mainboard/asus/kgpe-d16/cmos.layout   |  7 +++---
+ src/mainboard/asus/kgpe-d16/devicetree.cb |  1 +
+ src/mainboard/asus/kgpe-d16/romstage.c    |  2 ++
  5 files changed, 46 insertions(+), 4 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c
@@ -98,7 +100,7 @@ index 010d4db..310b7b1 100644
  984         16       h       0        check_sum
  # Reserve the extended AMD configuration registers
 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
-index 05b975b..8879c0e 100644
+index ada268b..f87efc6 100644
 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb
 +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
 @@ -15,6 +15,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
@@ -110,7 +112,7 @@ index 05b975b..8879c0e 100644
  						# Slot				# PCI E 1 / PCI E 2
  					end
 diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
-index 13fb485..c91fb1d 100644
+index 2b222f5..fa61f63 100644
 --- a/src/mainboard/asus/kgpe-d16/romstage.c
 +++ b/src/mainboard/asus/kgpe-d16/romstage.c
 @@ -459,6 +459,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -123,5 +125,5 @@ index 13fb485..c91fb1d 100644
  	 * This will be overridden later during RAM initialization
  	 */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch b/resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch
index 0dc6ff3..0e10cc9 100644
--- a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch
+++ b/resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch
@@ -1,11 +1,13 @@
-From da9855ac660e4b527ca0ee754d792ea0ab361fcc Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 5428b15fb1aef85b47fbbb117d943d2525a84692 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 14 Aug 2015 02:50:44 -0500
-Subject: [PATCH 118/146] southbridge/amd/sr5650: Use correct PCI
- configuration block offset
+Subject: [PATCH 116/139] southbridge/amd/sr5650: Use correct PCI configuration
+ block offset
 
+Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sr5650/acpi/sr5650.asl |    4 ++--
+ src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl
@@ -24,5 +26,5 @@ index a6ab114..1e0d5b0 100644
  	/* PIC IRQ mapping registers, C00h-C01h */
  	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch b/resources/libreboot/patch/kgpe-d16/0117-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch
index af853d5..d4a1b9e 100644
--- a/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch
+++ b/resources/libreboot/patch/kgpe-d16/0117-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch
@@ -1,14 +1,50 @@
-From 6eebec9d23f174057319cc373448f887e2779ddd Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 2062da830bac8ed759d18e3b06df0a97fd852ac9 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 14 Aug 2015 15:20:42 -0500
-Subject: [PATCH 119/146] southbridge/amd/sr5650: Add MCFG ACPI table support
+Subject: [PATCH 117/139] southbridge/amd/sr5650: Add MCFG ACPI table support
 
+Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/lpc.c     |    6 ------
- src/southbridge/amd/sb800/lpc.c     |    7 +------
- src/southbridge/amd/sr5650/sr5650.c |   16 ++++++++++++++++
- 3 files changed, 17 insertions(+), 12 deletions(-)
+ src/southbridge/amd/rs780/rs780.c   |  9 +++++++++
+ src/southbridge/amd/rs780/rs780.h   |  1 +
+ src/southbridge/amd/sb700/lpc.c     |  6 ------
+ src/southbridge/amd/sb800/lpc.c     |  7 +------
+ src/southbridge/amd/sr5650/sr5650.c | 16 ++++++++++++++++
+ 5 files changed, 27 insertions(+), 12 deletions(-)
 
+diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
+index c7003c7..6d5e6c7 100644
+--- a/src/southbridge/amd/rs780/rs780.c
++++ b/src/southbridge/amd/rs780/rs780.c
+@@ -353,6 +353,15 @@ void rs780_enable(device_t dev)
+ 	}
+ }
+ 
++unsigned long acpi_fill_mcfg(unsigned long current)
++{
++	/* FIXME
++	 * Leave table blank until proper contents
++	 * are determined.
++	 */
++	return current;
++}
++
+ struct chip_operations southbridge_amd_rs780_ops = {
+ 	CHIP_NAME("ATI RS780")
+ 	.enable_dev = rs780_enable,
+diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
+index dd2743f..a4ede50 100644
+--- a/src/southbridge/amd/rs780/rs780.h
++++ b/src/southbridge/amd/rs780/rs780.h
+@@ -21,6 +21,7 @@
+ #define __RS780_H__
+ 
+ #include <stdint.h>
++#include <arch/acpi.h>
+ #include <device/pci_ids.h>
+ #include "chip.h"
+ #include "rev.h"
 diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
 index 145a01f..fc27bef 100644
 --- a/src/southbridge/amd/sb700/lpc.c
@@ -79,5 +115,5 @@ index b296c47..4622f36 100644
  {
  	uint8_t *p;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0120-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch
index 68a0a03..a1a2049 100644
--- a/resources/libreboot/patch/kgpe-d16/0120-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch
+++ b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch
@@ -1,10 +1,12 @@
-From 1a7a9dae89b53ec363ffbfef448db909b9e150c4 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From cd71955dea67d3bea66627c6e40b8a569af60391 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 18 Aug 2015 17:45:48 -0500
-Subject: [PATCH 120/146] southbridge/amd/sb700: Fix mismatched FADT entries
+Subject: [PATCH 118/139] southbridge/amd/sb700: Fix mismatched FADT entries
 
+Change-Id: Ifa0b61678fe362481891fc015cebe08485b66fc1
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/fadt.c |    4 ++--
+ src/southbridge/amd/sb700/fadt.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c
@@ -30,5 +32,5 @@ index 6b1924f..209e9aa 100644
  	fadt->x_gpe0_blk.resv = 0;
  	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0121-southbridge-amd-sb700-Fix-drifting-system-clock.patch b/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sb700-Fix-drifting-system-clock.patch
index 996ac03..7a15867 100644
--- a/resources/libreboot/patch/kgpe-d16/0121-southbridge-amd-sb700-Fix-drifting-system-clock.patch
+++ b/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sb700-Fix-drifting-system-clock.patch
@@ -1,14 +1,16 @@
-From 4042f73651a2f55642357c98c0476db2a01af830 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From d0f4a06a86fbb28d9a6829fec10e7959eb845ab9 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 28 Aug 2015 15:31:31 -0500
-Subject: [PATCH 121/146] southbridge/amd/sb700: Fix drifting system clock
+Subject: [PATCH 119/139] southbridge/amd/sb700: Fix drifting system clock
 
+Change-Id: I1698c9b9b1840d254115821f3c0e76b7211e9056
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/southbridge/amd/sb700/early_setup.c |   14 +++++++++++---
+ src/southbridge/amd/sb700/early_setup.c | 14 +++++++++++---
  1 file changed, 11 insertions(+), 3 deletions(-)
 
 diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
-index 1f92a4e..f98e5c7 100644
+index da03961..fe8824f 100644
 --- a/src/southbridge/amd/sb700/early_setup.c
 +++ b/src/southbridge/amd/sb700/early_setup.c
 @@ -431,10 +431,10 @@ static void sb700_devices_por_init(void)
@@ -41,5 +43,5 @@ index 1f92a4e..f98e5c7 100644
  
  /*
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch b/resources/libreboot/patch/kgpe-d16/0120-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch
index 8ab3cef..39a7a9f 100644
--- a/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch
+++ b/resources/libreboot/patch/kgpe-d16/0120-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch
@@ -1,18 +1,20 @@
-From ae7424bea090928c8e3ebb69882ae5a8c3f2f82e Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 473fa0658e73ccdc92d376b8855d3e38e2592d3a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 20 Aug 2015 12:49:49 -0500
-Subject: [PATCH 122/146] northbridge/amd/amdmct/mct_ddr3: Add cc6 setup
+Subject: [PATCH 120/139] northbridge/amd/amdmct/mct_ddr3: Add cc6 setup
  information messages
 
+Change-Id: I17660ce5429431e08476b7bba15e381636b64c7d
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   11 +++++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 +++++++++++
  1 file changed, 11 insertions(+)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index b869647..e7ab88e 100644
+index 42630b9..1c3f5a3 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1494,6 +1494,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1496,6 +1496,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
  	if (pMCTstat->GStatus & (1 << GSB_NodeIntlv))
  		interleaved = 1;
  
@@ -21,7 +23,7 @@ index b869647..e7ab88e 100644
  	/* Find highest DRAM range (DramLimitAddr) */
  	max_node = 0;
  	max_range = -1;
-@@ -1517,6 +1519,9 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1519,6 +1521,9 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
  	}
  
  	if (max_range >= 0) {
@@ -31,7 +33,7 @@ index b869647..e7ab88e 100644
  		if (interleaved)
  			/* Move upper limit down by 16M * the number of nodes */
  			max_range_limit -= (0x1000000 * num_nodes);
-@@ -1524,6 +1529,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1526,6 +1531,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
  			/* Move upper limit down by 16M */
  			max_range_limit -= 0x1000000;
  
@@ -40,7 +42,7 @@ index b869647..e7ab88e 100644
  		/* Disable the range */
  		dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8));
  		byte = dword & 0x3;
-@@ -1558,6 +1565,10 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+@@ -1560,6 +1567,10 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
  	dword &= ~(0x3f << 12);				/* CoreSaveStateDestNode = destination_node */
  	dword |= (destination_node & 0x3f) << 12;
  	Set_NB32(pDCTstat->dev_link, 0x128, dword);
@@ -52,5 +54,5 @@ index b869647..e7ab88e 100644
  
  static void lock_dram_config(struct MCTStatStruc *pMCTstat,
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch b/resources/libreboot/patch/kgpe-d16/0121-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch
index 98bf95a..2d12303 100644
--- a/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch
+++ b/resources/libreboot/patch/kgpe-d16/0121-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch
@@ -1,18 +1,20 @@
-From e3c6eaf075a7991c4723e386fb215532fd9af4d0 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From b26909b4b537b7e3b1e5a5b1379ae7745c1e36b3 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 20 Aug 2015 15:53:25 -0500
-Subject: [PATCH 123/146] northbridge/amd/amdfam10: Work around sporadic
+Subject: [PATCH 121/139] northbridge/amd/amdfam10: Work around sporadic
  lockups when CC6 enabled
 
+Change-Id: If31140651f25f9c524a824b2da552ce3690eae18
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/northbridge.c |   14 ++++++++++++++
+ src/northbridge/amd/amdfam10/northbridge.c | 14 ++++++++++++++
  1 file changed, 14 insertions(+)
 
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index e374ed4..a8d9ce6 100644
+index 58b0079..8bd664d 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -812,6 +812,20 @@ static void amdfam10_domain_read_resources(device_t dev)
+@@ -814,6 +814,20 @@ static void amdfam10_domain_read_resources(device_t dev)
  			else
  				qword = 0x1000000;
  
@@ -34,5 +36,5 @@ index e374ed4..a8d9ce6 100644
  			reserved_ram_resource(dev, 8, (max_range_limit + 1) >> 10, qword >> 10);
  		}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch b/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch
index aa99c41..121e37f 100644
--- a/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch
+++ b/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch
@@ -1,18 +1,20 @@
-From a3fb888625af595dda6c2ee181f329259a12cc78 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From c16062b7739a77b084d139468f40f43d66ee26e0 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 27 Aug 2015 13:17:14 -0500
-Subject: [PATCH 124/146] northbridge/amd/amdmct/mct_ddr3: Ensure channel
- clock skew is properly set up
+Subject: [PATCH 122/139] northbridge/amd/amdmct/mct_ddr3: Ensure channel clock
+ skew is properly set up
 
+Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   46 +++++++++++++++------------
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 46 ++++++++++++++++-------------
  1 file changed, 25 insertions(+), 21 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index e7ab88e..78a5255 100644
+index 1c3f5a3..a11b227 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -3042,6 +3042,23 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
+@@ -3051,6 +3051,23 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
  		printk(BIOS_DEBUG, "\t\tDCTInit_D: mct_SPDCalcWidth Done\n");
  		if (AutoCycTiming_D(pMCTstat, pDCTstat, dct) < SC_StopError) {
  			printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoCycTiming_D Done\n");
@@ -36,7 +38,7 @@ index e7ab88e..78a5255 100644
  			if (AutoConfig_D(pMCTstat, pDCTstat, dct) < SC_StopError) {
  				printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n");
  				if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) {
-@@ -3051,8 +3068,6 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
+@@ -3060,8 +3077,6 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
  			}
  		}
  	}
@@ -45,7 +47,7 @@ index e7ab88e..78a5255 100644
  }
  
  static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct)
-@@ -3060,17 +3075,6 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p
+@@ -3069,17 +3084,6 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p
  	uint32_t dword;
  
  	/* Finalize DRAM init on a single node */
@@ -63,7 +65,7 @@ index e7ab88e..78a5255 100644
  	if (!pDCTstat->stopDCT[dct]) {
  		if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) {
  			printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Start\n");
-@@ -3273,28 +3277,28 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3282,28 +3286,28 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  			if (Twtr < val)
  				Twtr = val;
  
@@ -99,7 +101,7 @@ index e7ab88e..78a5255 100644
  			val *= MTB16x;
  			if (Tfaw < val)
  				Tfaw = val;
-@@ -3501,7 +3505,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3510,7 +3514,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  		/* Trfc0-Trfc3 */
  		for (i=0; i<4; i++)
  			if (pDCTstat->Trfc[i] == 0x0)
@@ -109,5 +111,5 @@ index e7ab88e..78a5255 100644
  		dword &= ~(0x07070707);
  		dword |= (pDCTstat->Trfc[3] & 0x7) << 24;			/* Trfc3 */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch b/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch
index 4dd5605..8c307a4 100644
--- a/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch
+++ b/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch
@@ -1,11 +1,13 @@
-From 2255079d463f0a09f74a8d0d64208772de5e0bc5 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 0a77e6cc316cd7dd5f68fb3511b6fdc31153872f Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 27 Aug 2015 13:18:06 -0500
-Subject: [PATCH 125/146] northbridge/amd/amdmct/mct_ddr3: Add DDR3
- termination debug output
+Subject: [PATCH 123/139] northbridge/amd/amdmct/mct_ddr3: Add DDR3 termination
+ debug output
 
+Change-Id: Iabd2e3e20b0e9719080f6bd7be2032c1749994dc
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c |    3 +++
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 3 +++
  1 file changed, 3 insertions(+)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -30,5 +32,5 @@ index 09a5f68..7804a38 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch b/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch
index d6788b5..7040927 100644
--- a/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch
+++ b/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch
@@ -1,11 +1,13 @@
-From 85a652d6f36b200437c86b84cc76304271c14a1e Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 352de00766d75d9b88a6021bfe5558a36923cc40 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 27 Aug 2015 13:18:53 -0500
-Subject: [PATCH 126/146] northbridge/amd/amdmct/mct_ddr3: Fix a minor RDIMM
- CS select error
+Subject: [PATCH 124/139] northbridge/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS
+ select error
 
+Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c |    4 ++--
+ src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
@@ -31,5 +33,5 @@ index 624a543..8fd2523 100644
  
  			/* Resend control word 10 */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch b/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch
index f0af729..39148d3 100644
--- a/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch
+++ b/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch
@@ -1,15 +1,17 @@
-From a89e50c7cef4090f00f530da8161d7d63d111e82 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 30d692e573ecf0a315b564895cf44e78d1b6daa9 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 27 Aug 2015 13:19:34 -0500
-Subject: [PATCH 127/146] northbridge/amd/amdmct/mct_ddr3: Fix odd rank data
+Subject: [PATCH 125/139] northbridge/amd/amdmct/mct_ddr3: Fix odd rank data
  corruption due to incorrect DQS training
 
+Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   25 ++++++++++++++++--------
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 25 +++++++++++++++++--------
  1 file changed, 17 insertions(+), 8 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index eedff67..98d2f11 100644
+index c520515..739a893 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -1324,9 +1324,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
@@ -59,5 +61,5 @@ index eedff67..98d2f11 100644
  
  		for (lane = lane_start; lane < lane_end; lane++) {
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0128-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch b/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch
index 6edf383..6a186e1 100644
--- a/resources/libreboot/patch/kgpe-d16/0128-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch
+++ b/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch
@@ -1,15 +1,17 @@
-From 246b8e4f7eb96fac6aa7f4c3133e48b30ed2637f Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 602d61a1535b24fbb04105e7e4594319641da3df Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 27 Aug 2015 15:10:19 -0500
-Subject: [PATCH 128/146] northbridge/amd/amdmct/mct_ddr3: Use antiphase to
+Subject: [PATCH 126/139] northbridge/amd/amdmct/mct_ddr3: Use antiphase to
  better center DQS window
 
+Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   59 ++++++++++++++++--------
- 1 file changed, 41 insertions(+), 18 deletions(-)
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 57 ++++++++++++++++++--------
+ 1 file changed, 40 insertions(+), 17 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 98d2f11..fa5a124 100644
+index 739a893..d870f17 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -1304,7 +1304,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
@@ -70,8 +72,7 @@ index 98d2f11..fa5a124 100644
  				}
  				last_pos = 0;
  			}
--	
-+
+ 
  			if (best_count > 2) {
 +				uint16_t region_center = (best_pos + (best_count / 2));
 +
@@ -152,5 +153,5 @@ index 98d2f11..fa5a124 100644
  				printk(BIOS_DEBUG, "\n");
  			}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0129-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch b/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch
index febfb9a..d7cedd7 100644
--- a/resources/libreboot/patch/kgpe-d16/0129-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch
+++ b/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch
@@ -1,20 +1,22 @@
-From 36ab0ce442a7394eacffd4770e4c159491414be8 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From aabb2b44191d7a2716dd89a0b9f3488b2d657cb9 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 27 Aug 2015 23:37:38 -0500
-Subject: [PATCH 129/146] northbridge/amd/amdmct/mct_ddr3: Fix broken support
+Subject: [PATCH 127/139] northbridge/amd/amdmct/mct_ddr3: Fix broken support
  for multiple DIMMs on single channel
 
+Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |  340 +++++++++++++++++++-----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |    8 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |    2 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c   |   26 +-
- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   |    4 +
- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |    8 +-
- 6 files changed, 312 insertions(+), 76 deletions(-)
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 336 ++++++++++++++++++++-----
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h    |   8 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   2 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctrci.c   |  26 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c   |   4 +
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  |   8 +-
+ 6 files changed, 310 insertions(+), 74 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index 78a5255..8564fed 100644
+index a11b227..5bc80f4 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
 @@ -1360,6 +1360,224 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
@@ -242,7 +244,7 @@ index 78a5255..8564fed 100644
  static void set_2t_configuration(struct MCTStatStruc *pMCTstat,
  				struct DCTStatStruc *pDCTstat, u8 dct)
  {
-@@ -2294,20 +2512,16 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
+@@ -2299,20 +2517,16 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
  		if (memclk_index <= 0x6) {
  			delay = 0x5;
  			delay2 = 0x3;
@@ -267,7 +269,7 @@ index 78a5255..8564fed 100644
  			delay = 0xa;
  			delay2 = 0x5;
  		}
-@@ -3320,8 +3534,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
+@@ -3329,8 +3543,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
  			tCK16x = 40;
  		else
  			tCK16x = 48;
@@ -277,7 +279,7 @@ index 78a5255..8564fed 100644
  		if (byte == 7)
  			tCK16x = 20;
  		else if (byte == 6)
-@@ -4648,13 +4861,13 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+@@ -4657,13 +4870,13 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
  					else
  						pDCTstat->RegMan1Present |= 1 << i;
  				}
@@ -296,7 +298,7 @@ index 78a5255..8564fed 100644
  			}
  		}
  	}
-@@ -5836,23 +6049,27 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat,
+@@ -5849,23 +6062,27 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat,
  	u32 val;
  	u32 dev = pDCTstat->dev_dct;
  	u32 index_reg = 0x98;
@@ -305,20 +307,18 @@ index 78a5255..8564fed 100644
  
 -	/* Tri-state unused chipselects when motherboard
 -	   termination is available */
--
--	/* FIXME: skip for Ax */
--
--	word = pDCTstat->CSPresent;
--	if (pDCTstat->Status & (1 << SB_Registered)) {
--		word |= (word & 0x55) << 1;
 +	if (is_fam15h()) {
 +		word = fam15h_cs_tristate_enable_code(pDCTstat, dct);
 +	} else {
 +		/* Tri-state unused chipselects when motherboard
 +		termination is available */
-+	
+ 
+-	/* FIXME: skip for Ax */
 +		/* FIXME: skip for Ax */
-+	
+ 
+-	word = pDCTstat->CSPresent;
+-	if (pDCTstat->Status & (1 << SB_Registered)) {
+-		word |= (word & 0x55) << 1;
 +		word = pDCTstat->CSPresent;
 +		if (pDCTstat->Status & (1 << SB_Registered)) {
 +			word |= (word & 0x55) << 1;
@@ -337,7 +337,7 @@ index 78a5255..8564fed 100644
  }
  
  static void SetCKETriState(struct MCTStatStruc *pMCTstat,
-@@ -5861,7 +6078,6 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
+@@ -5874,7 +6091,6 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
  	u32 val;
  	u32 dev;
  	u32 index_reg = 0x98;
@@ -345,7 +345,7 @@ index 78a5255..8564fed 100644
  	u16 word;
  
  	/* Tri-state unused CKEs when motherboard termination is available */
-@@ -5871,15 +6087,13 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
+@@ -5884,15 +6100,13 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
  	dev = pDCTstat->dev_dct;
  	word = pDCTstat->CSPresent;
  
@@ -365,7 +365,7 @@ index 78a5255..8564fed 100644
  }
  
  static void SetODTTriState(struct MCTStatStruc *pMCTstat,
-@@ -5889,42 +6103,44 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
+@@ -5902,42 +6116,44 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
  	u32 dev;
  	u32 index_reg = 0x98;
  	u8 cs;
@@ -396,7 +396,7 @@ index 78a5255..8564fed 100644
 +		/* Tri-state unused ODTs when motherboard termination is available */
 +		max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
 +		odt = 0x0f;	/* ODT tri-state setting */
-+	
++
 +		if (pDCTstat->Status & (1 <<SB_Registered)) {
 +			for (cs = 0; cs < 8; cs += 2) {
 +				if (pDCTstat->CSPresent & (1 << cs)) {
@@ -436,7 +436,7 @@ index 78a5255..8564fed 100644
  }
  
  /* Family 15h */
-@@ -6494,7 +6710,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -6507,7 +6723,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
  		dword |= (read_odt_delay & 0xf);
  		Set_NB32_DCT(dev, dct, 0x240, dword);
  
@@ -472,7 +472,7 @@ index ec5658e..8bc4ec2 100644
  	u8 DqsRcvEnGrossMax;
  	u8 DqsRcvEnGrossMin;
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index fa5a124..9c9a8c2 100644
+index d870f17..553a54a 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -1021,7 +1021,7 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat,
@@ -565,7 +565,7 @@ index 7804a38..5019faa 100644
  	 * chip select on registered DIMMs: */
  	for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel++) {
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
-index 3391dcf..81a0e69 100644
+index 73b231e..5cbadc3 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
 @@ -925,7 +925,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
@@ -598,5 +598,5 @@ index 3391dcf..81a0e69 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0130-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch b/resources/libreboot/patch/kgpe-d16/0128-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch
index 903204c..6bcf1d1 100644
--- a/resources/libreboot/patch/kgpe-d16/0130-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch
+++ b/resources/libreboot/patch/kgpe-d16/0128-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch
@@ -1,7 +1,7 @@
-From e6d5c8b5568e0fd6c149c7202d2084c7451875c5 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From f6d958412705c488a29bfad0aaaf7bc70cdb255a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 28 Aug 2015 19:52:05 -0500
-Subject: [PATCH 130/146] drivers/pc80: Add optional spinlock for nvram CBFS
+Subject: [PATCH 128/139] drivers/pc80: Add optional spinlock for nvram CBFS
  access
 
 When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following:
@@ -22,15 +22,18 @@ multiple APs during startup.  Calls to the nvram read functions get_option and r
 call CBFS functions, which in turn make near-simultaneous requests to the SMBus controller,
 thus placing the SP5100 in an invalid state.  This limitation is not documented in any public
 AMD errata, and was only discovered through considerable debugging effort.
+
+Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/Kconfig                              |    4 +++
- src/arch/x86/include/arch/smp/spinlock.h |    4 ++-
- src/cpu/amd/car/post_cache_as_ram.c      |    3 +++
- src/drivers/pc80/mc146818rtc.c           |   43 ++++++++++++++++++++++++++++--
+ src/Kconfig                              |  4 +++
+ src/arch/x86/include/arch/smp/spinlock.h |  4 ++-
+ src/cpu/amd/car/post_cache_as_ram.c      |  3 +++
+ src/drivers/pc80/mc146818rtc.c           | 43 ++++++++++++++++++++++++++++++--
  4 files changed, 51 insertions(+), 3 deletions(-)
 
 diff --git a/src/Kconfig b/src/Kconfig
-index 2e6b5bc..f1b7ebe 100644
+index 4e46364..b85e381 100644
 --- a/src/Kconfig
 +++ b/src/Kconfig
 @@ -451,6 +451,10 @@ config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
@@ -67,7 +70,7 @@ index 5000779..cf142a9 100644
  
  #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
-index 503a666..291f4f5 100644
+index 2282cee..55bb1be 100644
 --- a/src/cpu/amd/car/post_cache_as_ram.c
 +++ b/src/cpu/amd/car/post_cache_as_ram.c
 @@ -87,6 +87,9 @@ static void prepare_ramstage_region(void *resume_backup_memory)
@@ -168,5 +171,5 @@ index 07fc884..59de0a2 100644
  }
  
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch b/resources/libreboot/patch/kgpe-d16/0129-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch
index 0792398..494181a 100644
--- a/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch
+++ b/resources/libreboot/patch/kgpe-d16/0129-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch
@@ -1,18 +1,20 @@
-From 871017fedbc38dbdaf4fadb1e390046845266b95 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From ff495fb11ccedb64b6eab1853a8e50d30b3da80a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 28 Aug 2015 20:02:45 -0500
-Subject: [PATCH 131/146] mainboard/asus/kgpe-d16: Enable CBFS spinlocks
+Subject: [PATCH 129/139] mainboard/asus/kgpe-d16: Enable CBFS spinlocks
 
+Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/Kconfig    |    1 +
- src/mainboard/asus/kgpe-d16/romstage.c |   17 +++++++++++++++--
+ src/mainboard/asus/kgpe-d16/Kconfig    |  1 +
+ src/mainboard/asus/kgpe-d16/romstage.c | 17 +++++++++++++++--
  2 files changed, 16 insertions(+), 2 deletions(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
-index 761fc93..06116a2 100644
+index 084a412..a9261f9 100644
 --- a/src/mainboard/asus/kgpe-d16/Kconfig
 +++ b/src/mainboard/asus/kgpe-d16/Kconfig
-@@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
  	select SUPERIO_NUVOTON_NCT5572D
  	select PARALLEL_CPU_INIT
  	select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
@@ -21,7 +23,7 @@ index 761fc93..06116a2 100644
  	select HAVE_OPTION_TABLE
  	select HAVE_CMOS_DEFAULT
 diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
-index c91fb1d..3740bb0 100644
+index fa61f63..9998359 100644
 --- a/src/mainboard/asus/kgpe-d16/romstage.c
 +++ b/src/mainboard/asus/kgpe-d16/romstage.c
 @@ -315,6 +315,18 @@ void initialize_romstage_console_lock(void)
@@ -62,5 +64,5 @@ index c91fb1d..3740bb0 100644
 \ No newline at end of file
 +}
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch b/resources/libreboot/patch/kgpe-d16/0130-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch
index a8005e8..b530570 100644
--- a/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0130-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch
@@ -1,19 +1,21 @@
-From 2b8c4a3914e4d0705f10f09ea570e6f8a9d7ef93 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 66525594fa1976aae7d7f97e4b7455fc66e900df Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Fri, 28 Aug 2015 20:48:17 -0500
-Subject: [PATCH 132/146] cpu/amd/microcode: Introduce CBFS access spinlock to
+Subject: [PATCH 130/139] cpu/amd/microcode: Introduce CBFS access spinlock to
  avoid IOMMU failure
 
+Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/Kconfig                              |    4 ++++
- src/arch/x86/include/arch/smp/spinlock.h |    7 ++++++-
- src/cpu/amd/microcode/microcode.c        |   23 +++++++++++++++++++++++
- src/mainboard/asus/kgpe-d16/Kconfig      |    1 +
- src/mainboard/asus/kgpe-d16/romstage.c   |   15 ++++++++++++++-
- 5 files changed, 48 insertions(+), 2 deletions(-)
+ src/Kconfig                              |  4 ++++
+ src/arch/x86/include/arch/smp/spinlock.h |  7 ++++++-
+ src/cpu/amd/microcode/microcode.c        | 24 +++++++++++++++++++++++-
+ src/mainboard/asus/kgpe-d16/Kconfig      |  1 +
+ src/mainboard/asus/kgpe-d16/romstage.c   | 15 ++++++++++++++-
+ 5 files changed, 48 insertions(+), 3 deletions(-)
 
 diff --git a/src/Kconfig b/src/Kconfig
-index f1b7ebe..6b0df6a 100644
+index b85e381..5d5da98 100644
 --- a/src/Kconfig
 +++ b/src/Kconfig
 @@ -455,6 +455,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
@@ -53,12 +55,12 @@ index cf142a9..291c943 100644
  
  #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
 diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
-index ce5b08f..fc6b0f2 100644
+index badd3b7..bf644ab 100644
 --- a/src/cpu/amd/microcode/microcode.c
 +++ b/src/cpu/amd/microcode/microcode.c
-@@ -24,6 +24,12 @@
- #include <cpu/amd/microcode.h>
+@@ -25,6 +25,12 @@
  #include <cbfs.h>
+ #include <arch/io.h>
  
 +#ifdef __PRE_RAM__
 +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
@@ -69,41 +71,43 @@ index ce5b08f..fc6b0f2 100644
  #define UCODE_DEBUG(fmt, args...)	\
  	do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0)
  
-@@ -106,12 +112,29 @@ void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id)
- 		return;
- 	}
+@@ -201,14 +207,30 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
+ 			return;
+ 		}
  
 +#ifdef __PRE_RAM__
 +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
-+	spin_lock(romstage_microcode_cbfs_lock());
++		spin_lock(romstage_microcode_cbfs_lock());
 +#endif
 +#endif
 +
- 	ucode = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE,
- 					CBFS_TYPE_MICROCODE, &ucode_len);
- 	if (!ucode) {
- 		UCODE_DEBUG("microcode file not found. Skipping updates.\n");
+ 		ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i],
+ 						CBFS_TYPE_MICROCODE, &ucode_len);
+ 		if (!ucode) {
+ 			UCODE_DEBUG("microcode file not found. Skipping updates.\n");
+-
 +#ifdef __PRE_RAM__
 +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
-+		spin_unlock(romstage_microcode_cbfs_lock());
++			spin_unlock(romstage_microcode_cbfs_lock());
 +#endif
 +#endif
- 		return;
- 	}
+ 			return;
+ 		}
  
- 	amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
+ 		amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
 +
 +#ifdef __PRE_RAM__
 +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
-+	spin_unlock(romstage_microcode_cbfs_lock());
++		spin_unlock(romstage_microcode_cbfs_lock());
 +#endif
 +#endif
+ 	}
  }
 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
-index 06116a2..5f421db 100644
+index a9261f9..ff9afd3 100644
 --- a/src/mainboard/asus/kgpe-d16/Kconfig
 +++ b/src/mainboard/asus/kgpe-d16/Kconfig
-@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
  	select PARALLEL_CPU_INIT
  	select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
  	select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
@@ -112,7 +116,7 @@ index 06116a2..5f421db 100644
  	select HAVE_OPTION_TABLE
  	select HAVE_CMOS_DEFAULT
 diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
-index 3740bb0..6b5d801 100644
+index 9998359..d1b75b6 100644
 --- a/src/mainboard/asus/kgpe-d16/romstage.c
 +++ b/src/mainboard/asus/kgpe-d16/romstage.c
 @@ -327,6 +327,18 @@ void initialize_romstage_nvram_cbfs_lock(void)
@@ -147,5 +151,5 @@ index 3740bb0..6b5d801 100644
  		/* Nothing special needs to be done to find bus 0 */
  		/* Allow the HT devices to be found */
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0133-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch b/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch
index f314aad..72d834c 100644
--- a/resources/libreboot/patch/kgpe-d16/0133-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch
+++ b/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch
@@ -1,7 +1,7 @@
-From 66fffccceee09c2bffb7ad2de7159cb7e9bbae72 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From a3c83c34f3871be5624259a8a5d76bbae0386720 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 3 Sep 2015 17:39:51 -0500
-Subject: [PATCH 133/146] mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz
+Subject: [PATCH 131/139] mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz
 
 The CPU <--> CPU HT wiring on this board has only been validated
 to 2.6GHz.  While higher frequencies appear to function initially,
@@ -13,12 +13,15 @@ If applications are not being used that stress the coherent fabric,
 then the uptime before hang may be much longer.  Users attempting
 to overclock the HT links are advised to "burn in test" the HT links
 by running memtester locked to a node with no local memory installed.
+
+Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/romstage.c |    5 +++++
+ src/mainboard/asus/kgpe-d16/romstage.c | 5 +++++
  1 file changed, 5 insertions(+)
 
 diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
-index 6b5d801..61b3f09 100644
+index d1b75b6..8f1ec35 100644
 --- a/src/mainboard/asus/kgpe-d16/romstage.c
 +++ b/src/mainboard/asus/kgpe-d16/romstage.c
 @@ -349,6 +349,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -34,5 +37,5 @@ index 6b5d801..61b3f09 100644
  	uint8_t byte;
  	msr_t msr;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0134-cpu-amd-model_10xxx-Apply-missing-Family-15h-errata-.patch b/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-family_10h-family_15h-Apply-missing-Family-1.patch
index 5f3d325..126e45a 100644
--- a/resources/libreboot/patch/kgpe-d16/0134-cpu-amd-model_10xxx-Apply-missing-Family-15h-errata-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-family_10h-family_15h-Apply-missing-Family-1.patch
@@ -1,18 +1,20 @@
-From ac7cef89f29757df10f660a960c16e818d28de03 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 4dede601a2017d8a9696f8f2013a9b2b97d5169e Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 3 Sep 2015 17:43:52 -0500
-Subject: [PATCH 134/146] cpu/amd/model_10xxx: Apply missing Family 15h errata
- fixes
+Subject: [PATCH 132/139] cpu/amd/family_10h-family_15h: Apply missing Family
+ 15h errata fixes
 
+Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/defaults.h          |   12 ++++++++++++
- src/northbridge/amd/amdfam10/misc_control.c |    6 ++++++
+ src/cpu/amd/family_10h-family_15h/defaults.h | 12 ++++++++++++
+ src/northbridge/amd/amdfam10/misc_control.c  |  6 ++++++
  2 files changed, 18 insertions(+)
 
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
 index af59120..7a84fcb 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
 @@ -166,6 +166,14 @@ static const struct {
  	  0x0000000C, 0x00000000,
  	  0x0000000C, 0x00000000},	/* Cx and Dx multiple-link processor */
@@ -40,10 +42,10 @@ index af59120..7a84fcb 100644
  	{ 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
  	  0x00000100, 0x00000100 },	/* [8] = LvtOffsetVal */
 diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
-index 61cf1b6..fcb28c4 100644
+index 4b62c69..a3d6b19 100644
 --- a/src/northbridge/amd/amdfam10/misc_control.c
 +++ b/src/northbridge/amd/amdfam10/misc_control.c
-@@ -80,6 +80,7 @@ static void mcf3_read_resources(device_t dev)
+@@ -79,6 +79,7 @@ static void mcf3_read_resources(device_t dev)
  
  static void set_agp_aperture(device_t dev, uint32_t pci_id)
  {
@@ -51,7 +53,7 @@ index 61cf1b6..fcb28c4 100644
  	struct resource *resource;
  
  	resource = probe_resource(dev, 0x94);
-@@ -110,6 +111,11 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id)
+@@ -109,6 +110,11 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id)
  
  			/* Report the resource has been stored... */
  			report_resource_stored(pdev, resource, " <gart>");
@@ -64,5 +66,5 @@ index 61cf1b6..fcb28c4 100644
  	}
  }
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch b/resources/libreboot/patch/kgpe-d16/0133-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch
index bbacc25..1993cab 100644
--- a/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch
+++ b/resources/libreboot/patch/kgpe-d16/0133-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch
@@ -1,16 +1,18 @@
-From 6ba4ab07522e4a8dea42f12f8eab6edf648d36eb Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From d73cea7b450c1da2d4cd4af9d28f3ea97fb40f9d Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 3 Sep 2015 18:59:53 -0500
-Subject: [PATCH 135/146] northbridge/amd/amdmct/mct_ddr3: Use StopOnError to
+Subject: [PATCH 133/139] northbridge/amd/amdmct/mct_ddr3: Use StopOnError to
  decrease training time
 
+Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   84 +++++++++++++++++-------
- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |    4 +-
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 84 +++++++++++++++++++-------
+ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |  4 +-
  2 files changed, 64 insertions(+), 24 deletions(-)
 
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 9c9a8c2..77ffa42 100644
+index 553a54a..f2a7681 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
 @@ -1121,7 +1121,7 @@ static void stop_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
@@ -204,10 +206,10 @@ index 9c9a8c2..77ffa42 100644
  	uint32_t dev = pDCTstat->dev_dct;
  
 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-index b71b327..13adc39 100644
+index 3ede104..667854a 100644
 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
 +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
-@@ -1618,14 +1618,14 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
+@@ -1617,14 +1617,14 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
  		/* 2.10.5.8.5.1.[2,3]
  		 * Write the DRAM training pattern to the test address
  		 */
@@ -225,5 +227,5 @@ index b71b327..13adc39 100644
  			if (!dword)
  				break;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0136-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch b/resources/libreboot/patch/kgpe-d16/0134-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch
index 5f09063..22a0833 100644
--- a/resources/libreboot/patch/kgpe-d16/0136-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch
+++ b/resources/libreboot/patch/kgpe-d16/0134-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch
@@ -1,10 +1,12 @@
-From 9b4656eda209cd6fd8178d15b90016c05855dfa9 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From b83b06df45933d9b0ab3f8848bf940bbfd00be67 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Thu, 3 Sep 2015 19:27:40 -0500
-Subject: [PATCH 136/146] mainboard/asus/kgpe-d16: Enable GART by default
+Subject: [PATCH 134/139] mainboard/asus/kgpe-d16: Enable GART by default
 
+Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/mainboard/asus/kgpe-d16/cmos.default |    2 +-
+ src/mainboard/asus/kgpe-d16/cmos.default | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -21,5 +23,5 @@ index 83c1fe8..bc4c332 100644
  power_on_after_fail = On
  boot_option = Fallback
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch b/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch
index 5cdfdbb..5d18509 100644
--- a/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch
+++ b/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch
@@ -1,18 +1,20 @@
-From 73ac68361243375696c486a55a48bed2fdffcafc Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 057d4bcc43dfb1eec7fcf53b955592fa30d47fec Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 7 Sep 2015 03:39:15 -0500
-Subject: [PATCH 137/146] northbridge/amd/amdfam10: Fix incorrect channel
+Subject: [PATCH 135/139] northbridge/amd/amdfam10: Fix incorrect channel
  buffer count configuration
 
+Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdfam10/northbridge.c |   13 +++++--------
+ src/northbridge/amd/amdfam10/northbridge.c | 13 +++++--------
  1 file changed, 5 insertions(+), 8 deletions(-)
 
 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index a8d9ce6..fcb26f8 100644
+index 8bd664d..f039a5c 100644
 --- a/src/northbridge/amd/amdfam10/northbridge.c
 +++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -186,17 +186,14 @@ static void ht_route_link(struct bus *link, scan_state mode)
+@@ -188,17 +188,14 @@ static void ht_route_link(struct bus *link, scan_state mode)
  	 * not correctly configured
  	 */
  	busses = pci_read_config32(link->dev, link->cap + 0x14);
@@ -36,5 +38,5 @@ index a8d9ce6..fcb26f8 100644
  
  	if (mode == HT_ROUTE_FINAL) {
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-model_10xxx-Force-iolink-detect-to-either-1-.patch b/resources/libreboot/patch/kgpe-d16/0136-cpu-amd-family_10h-family_15h-Force-iolink-detect-to.patch
index 4a97b59..0f4e5ed 100644
--- a/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-model_10xxx-Force-iolink-detect-to-either-1-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0136-cpu-amd-family_10h-family_15h-Force-iolink-detect-to.patch
@@ -1,18 +1,20 @@
-From b3f2c1bea85b17840326d6f88793a66b128e367b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 587ece004106252847b7d08bf3c21c86c8b2e360 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 7 Sep 2015 18:07:03 -0500
-Subject: [PATCH 138/146] cpu/amd/model_10xxx: Force iolink detect to either 1
- or 0
+Subject: [PATCH 136/139] cpu/amd/family_10h-family_15h: Force iolink detect to
+ either 1 or 0
 
+Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/init_cpus.c |    4 ++--
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 0ac893a..f17a439 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
-@@ -1236,7 +1236,7 @@ static void cpuSetAMDPCI(u8 node)
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index 7a0701c..ff9a033 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+@@ -1239,7 +1239,7 @@ static void cpuSetAMDPCI(u8 node)
  		for (link = 0; link < 4; link++) {
  			if (AMD_CpuFindCapability(node, link, &offset)) {
  				ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1);
@@ -21,7 +23,7 @@ index 0ac893a..f17a439 100644
  
  				if (!iolink && ganged) {
  					if (probe_filter_enabled) {
-@@ -1388,7 +1388,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1391,7 +1391,7 @@ static void cpuSetAMDPCI(u8 node)
  		for (link = 0; link < 4; link++) {
  			if (AMD_CpuFindCapability(node, link, &offset)) {
  				ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1);
@@ -31,5 +33,5 @@ index 0ac893a..f17a439 100644
  				/* Set defaults */
  				isoc_rsp_tok_1 = 0;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0139-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch b/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch
index 8428679..bb4ff3b 100644
--- a/resources/libreboot/patch/kgpe-d16/0139-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch
@@ -1,11 +1,13 @@
-From f668efc985a4ad3c0a2c5b0921f0ef2c4a7f458a Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From 21df09828beb3385b1fe1eaa763578780e444b77 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 7 Sep 2015 18:07:43 -0500
-Subject: [PATCH 139/146] northbridge/amd/amdht: Fix XCS buffer count setup on
+Subject: [PATCH 137/139] northbridge/amd/amdht: Fix XCS buffer count setup on
  AMD Family 15h CPUs
 
+Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/northbridge/amd/amdht/h3ncmn.c |   94 +++++++++++++++++++++++++++++++++++-
+ src/northbridge/amd/amdht/h3ncmn.c | 94 +++++++++++++++++++++++++++++++++++++-
  1 file changed, 92 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
@@ -138,5 +140,5 @@ index 841fc0c..80fe7ce 100644
  		0x00000200,
  		18,
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0140-cpu-amd-model_10xxx-Fix-link-type-detection-and-XCS-.patch b/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-family_10h-family_15h-Fix-link-type-detectio.patch
index 17c6149..18c1420 100644
--- a/resources/libreboot/patch/kgpe-d16/0140-cpu-amd-model_10xxx-Fix-link-type-detection-and-XCS-.patch
+++ b/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-family_10h-family_15h-Fix-link-type-detectio.patch
@@ -1,18 +1,20 @@
-From 9f347bbef949f4a9f402e0ecfac91f7c58bafd84 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+From d08d31fc7f2299fc6c12be09061c62170615d160 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Mon, 7 Sep 2015 22:26:55 -0500
-Subject: [PATCH 140/146] cpu/amd/model_10xxx: Fix link type detection and XCS
- buffer count setup
+Subject: [PATCH 138/139] cpu/amd/family_10h-family_15h: Fix link type
+ detection and XCS buffer count setup
 
+Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
 ---
- src/cpu/amd/model_10xxx/fidvid.c    |    2 +-
- src/cpu/amd/model_10xxx/init_cpus.c |   33 +++++++++++++++++++--------------
+ src/cpu/amd/family_10h-family_15h/fidvid.c    |  2 +-
+ src/cpu/amd/family_10h-family_15h/init_cpus.c | 33 +++++++++++++++------------
  2 files changed, 20 insertions(+), 15 deletions(-)
 
-diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
-index 1d55275..110a299 100644
---- a/src/cpu/amd/model_10xxx/fidvid.c
-+++ b/src/cpu/amd/model_10xxx/fidvid.c
+diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
+index ed8cafa..84315b4 100644
+--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
 @@ -379,7 +379,7 @@ static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) {
          u8 link0isGen3 = 0;
          u8 offset;
@@ -22,10 +24,10 @@ index 1d55275..110a299 100644
  	}
          /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
             S1g3 in link Gen3 mode, but I don't know how to tell
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index f17a439..0604ef8 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
+diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
+index ff9a033..f86cc75 100644
+--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
 @@ -845,7 +845,7 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
   *
   * Returns the link characteristic mask.
@@ -44,7 +46,7 @@ index f17a439..0604ef8 100644
  
  		if (val & 1)
  			linktype |= HTPHY_LINKTYPE_GANGED;
-@@ -1116,7 +1116,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1119,7 +1119,7 @@ static void cpuSetAMDPCI(u8 node)
  			 */
  			for (j = 0; j < 4; j++) {
  				if (AMD_CpuFindCapability(node, j, &offset)) {
@@ -53,7 +55,7 @@ index f17a439..0604ef8 100644
  					    & fam10_htphy_default[i].linktype) {
  						AMD_SetHtPhyRegister(node, j,
  								     i);
-@@ -1214,6 +1214,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1217,6 +1217,7 @@ static void cpuSetAMDPCI(u8 node)
  		pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword);
  
  		uint8_t link;
@@ -61,7 +63,7 @@ index f17a439..0604ef8 100644
  		uint8_t ganged;
  		uint8_t iolink;
  		uint8_t probe_filter_enabled = !!dual_node;
-@@ -1235,8 +1236,9 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1238,8 +1239,9 @@ static void cpuSetAMDPCI(u8 node)
  
  		for (link = 0; link < 4; link++) {
  			if (AMD_CpuFindCapability(node, link, &offset)) {
@@ -73,7 +75,7 @@ index f17a439..0604ef8 100644
  
  				if (!iolink && ganged) {
  					if (probe_filter_enabled) {
-@@ -1332,7 +1334,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1335,7 +1337,7 @@ static void cpuSetAMDPCI(u8 node)
  					np_req_cmd = 12;
  				}
  
@@ -82,7 +84,7 @@ index f17a439..0604ef8 100644
  				dword &= ~(0x3 << 27);			/* IsocRspData = isoc_rsp_data */
  				dword |= ((isoc_rsp_data & 0x3) << 27);
  				dword &= ~(0x3 << 25);			/* IsocNpReqData = isoc_np_req_data */
-@@ -1343,9 +1345,9 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1346,9 +1348,9 @@ static void cpuSetAMDPCI(u8 node)
  				dword |= ((isoc_preq & 0x7) << 19);
  				dword &= ~(0x7 << 16);			/* IsocNpReqCmd = isoc_np_req_cmd */
  				dword |= ((isoc_np_req_cmd & 0x7) << 16);
@@ -94,7 +96,7 @@ index f17a439..0604ef8 100644
  				dword &= ~(0x1 << 31);			/* LockBc = 0x1 */
  				dword |= ((0x1 & 0x1) << 31);
  				dword &= ~(0x7 << 25);			/* FreeData = free_data */
-@@ -1364,7 +1366,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1367,7 +1369,7 @@ static void cpuSetAMDPCI(u8 node)
  				dword |= ((preq & 0x7) << 5);
  				dword &= ~(0x1f << 0);			/* NpReqCmd = np_req_cmd */
  				dword |= ((np_req_cmd & 0x1f) << 0);
@@ -103,7 +105,7 @@ index f17a439..0604ef8 100644
  			}
  		}
  
-@@ -1387,8 +1389,9 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1390,8 +1392,9 @@ static void cpuSetAMDPCI(u8 node)
  
  		for (link = 0; link < 4; link++) {
  			if (AMD_CpuFindCapability(node, link, &offset)) {
@@ -115,7 +117,7 @@ index f17a439..0604ef8 100644
  
  				/* Set defaults */
  				isoc_rsp_tok_1 = 0;
-@@ -1616,7 +1619,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1619,7 +1622,7 @@ static void cpuSetAMDPCI(u8 node)
  					}
  				}
  
@@ -124,7 +126,7 @@ index f17a439..0604ef8 100644
  				dword &= ~(0x3 << 30);			/* FreeTok[3:2] = free_tokens[3:2] */
  				dword |= (((free_tokens >> 2) & 0x3) << 30);
  				dword &= ~(0x1 << 28);			/* IsocRspTok1 = isoc_rsp_tok_1 */
-@@ -1649,7 +1652,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1652,7 +1655,7 @@ static void cpuSetAMDPCI(u8 node)
  				dword |= (((preq_tok_0) & 0x3) << 2);
  				dword &= ~(0x3 << 0);			/* ReqTok0 = req_tok_0 */
  				dword |= (((req_tok_0) & 0x3) << 0);
@@ -133,7 +135,7 @@ index f17a439..0604ef8 100644
  			}
  		}
  
-@@ -1695,6 +1698,7 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1698,6 +1701,7 @@ static void cpuSetAMDPCI(u8 node)
  	}
  
  	uint8_t link;
@@ -141,7 +143,7 @@ index f17a439..0604ef8 100644
  	uint8_t isochronous;
  	uint8_t isochronous_link_present;
  
-@@ -1702,7 +1706,8 @@ static void cpuSetAMDPCI(u8 node)
+@@ -1705,7 +1709,8 @@ static void cpuSetAMDPCI(u8 node)
  	isochronous_link_present = 0;
  	for (link = 0; link < 4; link++) {
  		if (AMD_CpuFindCapability(node, link, &offset)) {
@@ -152,5 +154,5 @@ index f17a439..0604ef8 100644
  			if (isochronous)
  				isochronous_link_present = 1;
 -- 
-1.7.9.5
+1.9.1
 
diff --git a/resources/libreboot/patch/kgpe-d16/0139-cpu-amd-family_10h-family_15h-Enable-DFE-on-Family-1.patch b/resources/libreboot/patch/kgpe-d16/0139-cpu-amd-family_10h-family_15h-Enable-DFE-on-Family-1.patch
new file mode 100644
index 0000000..da36ce8
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0139-cpu-amd-family_10h-family_15h-Enable-DFE-on-Family-1.patch
@@ -0,0 +1,32 @@
+From 43dd7e42cfd9e3af706dd28fc482921b54029496 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sun, 13 Sep 2015 15:54:32 -0500
+Subject: [PATCH 139/139] cpu/amd/family_10h-family_15h: Enable DFE on Family
+ 15h HT3 links
+
+Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
+index 7a84fcb..b906866 100644
+--- a/src/cpu/amd/family_10h-family_15h/defaults.h
++++ b/src/cpu/amd/family_10h-family_15h/defaults.h
+@@ -857,4 +857,12 @@ static const struct {
+ 	{ 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+ 	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
+ 					   [20:16] RttIndex = 04h */
++
++	{ 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x00013480, 0x0003fc80 },	/* [17:10] DCV = 0x4d,
++					       [7] DfeEn = 0x1 */
++
++	{ 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
++	  0x00013480, 0x0003fc80 },     /* [17:10] DCV = 0x4d,
++					       [7] DfeEn = 0x1 */
+ };
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/kgpe-d16/0141-cpu-amd-model_10xxx-Enable-DFE-on-Family-15h-HT3-lin.patch b/resources/libreboot/patch/kgpe-d16/0141-cpu-amd-model_10xxx-Enable-DFE-on-Family-15h-HT3-lin.patch
deleted file mode 100644
index 3968d10..0000000
--- a/resources/libreboot/patch/kgpe-d16/0141-cpu-amd-model_10xxx-Enable-DFE-on-Family-15h-HT3-lin.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From c8c36ead5561c661604bd2e141be91091a6e8a99 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Sun, 13 Sep 2015 15:54:32 -0500
-Subject: [PATCH 141/146] cpu/amd/model_10xxx: Enable DFE on Family 15h HT3
- links
-
----
- src/cpu/amd/model_10xxx/defaults.h  |    8 ++++++++
- src/cpu/amd/model_10xxx/init_cpus.c |    2 +-
- 2 files changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
-index 7a84fcb..b906866 100644
---- a/src/cpu/amd/model_10xxx/defaults.h
-+++ b/src/cpu/amd/model_10xxx/defaults.h
-@@ -857,4 +857,12 @@ static const struct {
- 	{ 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 	  0x40040000, 0xe01F0000 },	/* [31:29] RttCtl = 02h,
- 					   [20:16] RttIndex = 04h */
-+
-+	{ 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	  0x00013480, 0x0003fc80 },	/* [17:10] DCV = 0x4d,
-+					       [7] DfeEn = 0x1 */
-+
-+	{ 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-+	  0x00013480, 0x0003fc80 },     /* [17:10] DCV = 0x4d,
-+					       [7] DfeEn = 0x1 */
- };
-diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
-index 0604ef8..2c106fe 100644
---- a/src/cpu/amd/model_10xxx/init_cpus.c
-+++ b/src/cpu/amd/model_10xxx/init_cpus.c
-@@ -1186,7 +1186,7 @@ static void cpuSetAMDPCI(u8 node)
- 		/* Check for dual node capability */
- 		if (f3xe8 & 0x20000000)
- 			dual_node = 1;
--		
-+
- 		/* Determine the number of active compute units on this node */
- 		f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80);
- 		cu_enabled = f5x80 & 0xf;
--- 
-1.7.9.5
-