1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
From 173148993ede860eb9e00d5d6efee322f6b03424 Mon Sep 17 00:00:00 2001
From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
Date: Tue, 9 Jun 2015 19:12:35 -0500
Subject: [PATCH 052/146] southbridge/amd/sb700: Disable broken SATA MSI
functionality
---
src/southbridge/amd/sb700/early_setup.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 70a2aee..1f92a4e 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -678,6 +678,7 @@ static void sb700_pci_cfg(void)
{
device_t dev;
u8 byte;
+ uint8_t acpi_s1_supported = 1;
/* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
@@ -730,10 +731,10 @@ static void sb700_pci_cfg(void)
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 0;
pci_write_config8(dev, 0x40, byte);
- if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12)
- pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */
+ if (acpi_s1_supported)
+ pci_write_config8(dev, 0x34, 0x70); /* Hide D3 power state and MSI capabilities */
else
- pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */
+ pci_write_config8(dev, 0x61, 0x70); /* Hide MSI capability */
byte &= ~(1 << 0);
pci_write_config8(dev, 0x40, byte);
}
--
1.7.9.5
|
