diff options
Diffstat (limited to 'resources/libreboot/patch/coreboot')
5 files changed, 207 insertions, 48 deletions
diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch index f2c7c4f..9fe21d4 100644 --- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch @@ -1,4 +1,4 @@ -From e1eada0b19f11777ce1ce9e64d99905fbb16bcbd Mon Sep 17 00:00:00 2001 +From bf128e4fc6d6a134d8d04ee0c4a392a4d98db1d4 Mon Sep 17 00:00:00 2001 From: Damien Zammit <damien@zamaudio.com> Date: Wed, 11 May 2016 19:08:33 +1000 Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA @@ -80,17 +80,19 @@ index fdfe73d..87719f7 100644 } } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb -index 3965538..68a3352 100644 +index 3965538..c433387 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb -@@ -46,10 +46,8 @@ +@@ -46,10 +46,10 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_legacy_combined" = "0x1" ++ register "ide_legacy_combined" = "0x0" # Combined mode broken register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" ++ register "sata_ahci" = "0x0" # AHCI does not work register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch index acdc33b..c08635c 100644 --- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch @@ -1,7 +1,14 @@ -From a7fcc0967128317b5c3dcdfffa7fb8e28210573f Mon Sep 17 00:00:00 2001 +From 9bc6d718c1f9070fb82e09499dfc3f5d95e857c5 Mon Sep 17 00:00:00 2001 From: Damien Zammit <damien@zamaudio.com> Date: Sat, 21 May 2016 01:56:01 +1000 -Subject: [PATCH] nb/intel/x4x: Add DMI init +Subject: [PATCH] nb/intel/x4x: Add DMI/EP init + +The values were obtained from vendor bios at runtime. +I am not 100% sure of the sequence required to initiate them, +but guessed from the gm45 code. There may be some status bytes +needed to be polled during the sequence that is missing, +but as I don't have bios writer's datasheet it's very hard +for me to know. Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8 Signed-off-by: Damien Zammit <damien@zamaudio.com> @@ -21,10 +28,10 @@ index 34d9b0f..3520944 100644 ramstage-y += ram_calc.c diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c new file mode 100644 -index 0000000..69a2741 +index 0000000..d432fea --- /dev/null +++ b/src/northbridge/intel/x4x/pcie.c -@@ -0,0 +1,161 @@ +@@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * @@ -56,32 +63,38 @@ index 0000000..69a2741 + +static void init_egress(void) +{ -+ EPBAR32(0x00) = 0x04010002; -+ EPBAR32(0x04) = 0x00000001; -+ EPBAR32(0x10) = 0x00000001; -+ EPBAR32(0x14) = 0x80000001; -+ EPBAR32(0x1c) = 0x00008001; -+ EPBAR32(0x40) = 0x00010005; -+ EPBAR32(0x44) = 0x00010301; -+ EPBAR32(0x50) = 0x01010001; -+ EPBAR32(0x58) = DEFAULT_DMIBAR; -+ EPBAR32(0x60) = 0x02010003; -+ EPBAR32(0x68) = 0x00008000; -+ EPBAR32(0x70) = 0x03000002; -+ EPBAR32(0x78) = 0x00030000; ++ /* VC0: TC0 only */ ++ EPBAR8(0x14) = 1; ++ EPBAR8(0x4) = 1; ++ ++ /* VC1: ID1, TC7 */ ++ EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); ++ EPBAR8(0x20) = 1 << 7; ++ ++ /* VC1: enable */ ++ EPBAR32(0x20) |= 1 << 31; ++ ++ while ((EPBAR8(0x26) & 2) != 0) ; + -+ EPBAR32(0x20) = 0x81000080; ++ printk(BIOS_DEBUG, "Done EP loop\n"); +} + +static void init_dmi(void) +{ -+ DMIBAR32(0x0000) = 0x04010002; -+ DMIBAR32(0x0004) = 0x00000001; -+ DMIBAR32(0x0010) = 0x00000001; -+ DMIBAR32(0x0014) = 0x80000001; -+ DMIBAR32(0x001c) = 0x00008001; ++ /* VC0: TC0 only */ ++ DMIBAR8(DMIVC0RCTL) = 1; ++ DMIBAR8(0x4) = 1; + -+ DMIBAR32(0x0020) = 0x81000080; ++ /* VC1: ID1, TC7 */ ++ DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); ++ DMIBAR8(DMIVC1RCTL) = 1 << 7; ++ ++ /* VC1: enable */ ++ DMIBAR32(DMIVC1RCTL) |= 1 << 31; ++ ++ // Hangs ++ //while ((DMIBAR8(0x26) & 2) != 0) ; ++ //printk(BIOS_DEBUG, "Done DMI loop\n"); + + DMIBAR32(0x0028) = 0x00000001; + DMIBAR32(0x002c) = 0x86000000; @@ -179,6 +192,15 @@ index 0000000..69a2741 + DMIBAR32(0x031c) = 0x003a0ca6; + DMIBAR32(0x0324) = 0x00040010; + DMIBAR32(0x0328) = 0x00040000; ++ ++ EPBAR32(0x40) = 0x00010005; ++ EPBAR32(0x44) = 0x00010301; ++ EPBAR32(0x50) = 0x01010001; ++ EPBAR32(0x58) = DEFAULT_DMIBAR; ++ EPBAR32(0x60) = 0x02010003; ++ EPBAR32(0x68) = 0x00008000; ++ EPBAR32(0x70) = 0x03000002; ++ EPBAR32(0x78) = 0x00030000; +} + +void x4x_late_init(void) diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch index 120fd22..be8e997 100644 --- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch @@ -1,14 +1,31 @@ -From bbea7db476854e3979a60c9a3e173eb8a52a8fa5 Mon Sep 17 00:00:00 2001 +From 26262b2e7085fa4d8201e2519fead0dec9237d2f Mon Sep 17 00:00:00 2001 From: Damien Zammit <damien@zamaudio.com> Date: Sat, 21 May 2016 01:56:53 +1000 Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Use x4x_late_init() +This patch adds DMI/EP init to the board and fixes +a couple of minor things. + Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039 Signed-off-by: Damien Zammit <damien@zamaudio.com> --- +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +index 0a26f83..31b29bb 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +@@ -26,6 +26,9 @@ + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT ++ select PCIEXP_ASPM ++ select PCIEXP_CLK_PM ++ select PCIEXP_L1_SUB_STATE + + config MMCONF_BASE_ADDRESS + hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c -index bff481f..425b176 100644 +index bff481f..6365404 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -50,9 +50,10 @@ @@ -24,7 +41,26 @@ index bff481f..425b176 100644 outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x000000e7, DEFAULT_GPIOBASE + 0x30); outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); -@@ -98,10 +99,23 @@ +@@ -66,9 +67,9 @@ + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); +- ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x00); ++ ite_reg_write(GPIO_DEV, 0xb8, 0x00); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc1, 0xc7); +@@ -89,6 +90,7 @@ + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 ++ ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + + /* IRQ routing */ + RCBA32(0x3100) = 0x00002210; +@@ -98,10 +100,23 @@ RCBA32(0x3110) = 0x00000001; RCBA32(0x3140) = 0x00410032; RCBA32(0x3144) = 0x32100237; @@ -48,6 +84,17 @@ index bff481f..425b176 100644 } static void ich7_enable_lpc(void) +@@ -126,9 +141,8 @@ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; + + /* Set southbridge and Super I/O GPIOs. */ +- mb_gpio_init(); +- + ich7_enable_lpc(); ++ mb_gpio_init(); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ @@ -146,4 +160,9 @@ quick_ram_check(); cbmem_initialize_empty(); diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0005-update-board-info.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0005-update-board-info.patch new file mode 100644 index 0000000..5e45fbc --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0005-update-board-info.patch @@ -0,0 +1,35 @@ +From ae837e942d751aaf9a7f5b9ed5fba687abbd1dde Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Tue, 24 May 2016 17:26:51 +1000 +Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Update board_info.txt and add item to Kconfig + +This adds the website URL to the board info and also enables +the realtek nic reset function as per a previous patch. + +Change-Id: I2cda120c59b55f0dd2ffa78d397b16beb13d6843 +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +index 31b29bb..7dec921 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +@@ -29,6 +29,7 @@ + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE ++ select REALTEK_8168_RESET + + config MMCONF_BASE_ADDRESS + hex +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt +index 44ed73a..170449e 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt +@@ -1,5 +1,5 @@ + Category: desktop +-Board URL: ++Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=3024#ov + ROM package: SOIC-8 + ROM protocol: SPI + ROM socketed: n diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch index 279d2f2..7d1d1c5 100644 --- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch @@ -1,7 +1,12 @@ -From 5e99bbbf3140b198b2c4b68e646e7042f76806e3 Mon Sep 17 00:00:00 2001 +From 8f90ec9634e7eb0a385902fe2d74af4ebc33c7c2 Mon Sep 17 00:00:00 2001 From: Damien Zammit <damien@zamaudio.com> Date: Sat, 21 May 2016 02:24:19 +1000 -Subject: [PATCH] drivers/net/r8168: Add driver for 10ec:8168 to reset the NIC +Subject: [PATCH] drivers/net/r8168: Add driver for realtek nic + +One thing that is vital to this patch is the MAC address setting +in case the EEPROM/efuse is unconfigured. +Linux now recognises the default MAC address on GA-G41M-ES2L which +does rely on the default bios settings for the MAC address. Change-Id: I32e070b545b4c6369686a7087b7ff838d00764e3 Signed-off-by: Damien Zammit <damien@zamaudio.com> @@ -28,41 +33,89 @@ index 9b3008d..e435d48 100644 +ramstage-$(CONFIG_REALTEK_8168_RESET) += r8168.c diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c new file mode 100644 -index 0000000..be5a7b8 +index 0000000..4301693 --- /dev/null +++ b/src/drivers/net/r8168.c -@@ -0,0 +1,46 @@ +@@ -0,0 +1,94 @@ +/* -+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> + * -+ * This driver simply forces the 10ec:8168 device to reset so that it goes -+ * into a proper power state. ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/* ++ * This driver forces the 10ec:8168 device to reset so that it goes ++ * into a proper power state, also programs a default MAC address ++ * so that if the EEPROM/efuse is unconfigured it still has a default MAC. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> -+#include <device/pci_ids.h> +#include <device/pci_ops.h> -+#include <stdlib.h> -+#include <string.h> ++#include <device/pci_def.h> ++#include <delay.h> ++#include <console/console.h> ++ ++#define NIC_TIMEOUT 1000 + -+#define CMD_REG 0x37 ++#define CMD_REG 0x37 ++#define CMD_REG_RESET 0x10 ++ ++#define CFG_9346 0x50 ++#define CFG_9346_LOCK 0x00 ++#define CFG_9346_UNLOCK 0xc0 + +static void r8168_init(struct device *dev) +{ -+ u32 cnt = 0; ++ u32 i; ++ const u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 }; + + /* Get the resource of the NIC mmio */ + struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); -+ u32 nic_mmio = (u32)res2mmio(nic_res, 0, 0); ++ u16 nic_port = (u16)nic_res->base; ++ ++ /* Set bus master */ ++ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER ++ | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); ++ ++ /* Reset NIC */ ++ printk(BIOS_DEBUG, "r8168: Resetting NIC..."); ++ outb(CMD_REG_RESET, nic_port + CMD_REG); ++ ++ i = 0; ++ /* Poll for reset, with 1s timeout */ ++ while (i < NIC_TIMEOUT && (inb(nic_port + CMD_REG) & CMD_REG_RESET)) { ++ udelay(1000); ++ if (++i >= NIC_TIMEOUT) ++ printk(BIOS_DEBUG, "timeout waiting for nic to reset\n"); ++ } ++ if (i < NIC_TIMEOUT) ++ printk(BIOS_DEBUG, "done\n"); ++ ++ /* Unlock config regs */ ++ outb(CFG_9346_UNLOCK, nic_port + CFG_9346); ++ ++ /* Set MAC address 00:e0:4c:00:c0:b0 ++ * NB: only 4-byte write accesses allowed ++ */ ++ outl(mac[4] | mac[5] << 8, nic_port + 4); ++ inl(nic_port + 4); + -+ /* Reset */ -+ outb(0x10, nic_mmio + CMD_REG); ++ outl(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, nic_port); ++ inl(nic_port); + -+ /* Poll for reset, with timeout */ -+ while (cnt < 1000 && (inb(nic_mmio + CMD_REG) & 0x10)) -+ cnt++; ++ /* Lock config regs */ ++ outb(CFG_9346_LOCK, nic_port + CFG_9346); +} + +static struct device_operations r8168_ops = { |