diff options
Diffstat (limited to 'resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch | 70 |
1 files changed, 46 insertions, 24 deletions
diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch index acdc33b..c08635c 100644 --- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch @@ -1,7 +1,14 @@ -From a7fcc0967128317b5c3dcdfffa7fb8e28210573f Mon Sep 17 00:00:00 2001 +From 9bc6d718c1f9070fb82e09499dfc3f5d95e857c5 Mon Sep 17 00:00:00 2001 From: Damien Zammit <damien@zamaudio.com> Date: Sat, 21 May 2016 01:56:01 +1000 -Subject: [PATCH] nb/intel/x4x: Add DMI init +Subject: [PATCH] nb/intel/x4x: Add DMI/EP init + +The values were obtained from vendor bios at runtime. +I am not 100% sure of the sequence required to initiate them, +but guessed from the gm45 code. There may be some status bytes +needed to be polled during the sequence that is missing, +but as I don't have bios writer's datasheet it's very hard +for me to know. Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8 Signed-off-by: Damien Zammit <damien@zamaudio.com> @@ -21,10 +28,10 @@ index 34d9b0f..3520944 100644 ramstage-y += ram_calc.c diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c new file mode 100644 -index 0000000..69a2741 +index 0000000..d432fea --- /dev/null +++ b/src/northbridge/intel/x4x/pcie.c -@@ -0,0 +1,161 @@ +@@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * @@ -56,32 +63,38 @@ index 0000000..69a2741 + +static void init_egress(void) +{ -+ EPBAR32(0x00) = 0x04010002; -+ EPBAR32(0x04) = 0x00000001; -+ EPBAR32(0x10) = 0x00000001; -+ EPBAR32(0x14) = 0x80000001; -+ EPBAR32(0x1c) = 0x00008001; -+ EPBAR32(0x40) = 0x00010005; -+ EPBAR32(0x44) = 0x00010301; -+ EPBAR32(0x50) = 0x01010001; -+ EPBAR32(0x58) = DEFAULT_DMIBAR; -+ EPBAR32(0x60) = 0x02010003; -+ EPBAR32(0x68) = 0x00008000; -+ EPBAR32(0x70) = 0x03000002; -+ EPBAR32(0x78) = 0x00030000; ++ /* VC0: TC0 only */ ++ EPBAR8(0x14) = 1; ++ EPBAR8(0x4) = 1; ++ ++ /* VC1: ID1, TC7 */ ++ EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); ++ EPBAR8(0x20) = 1 << 7; ++ ++ /* VC1: enable */ ++ EPBAR32(0x20) |= 1 << 31; ++ ++ while ((EPBAR8(0x26) & 2) != 0) ; + -+ EPBAR32(0x20) = 0x81000080; ++ printk(BIOS_DEBUG, "Done EP loop\n"); +} + +static void init_dmi(void) +{ -+ DMIBAR32(0x0000) = 0x04010002; -+ DMIBAR32(0x0004) = 0x00000001; -+ DMIBAR32(0x0010) = 0x00000001; -+ DMIBAR32(0x0014) = 0x80000001; -+ DMIBAR32(0x001c) = 0x00008001; ++ /* VC0: TC0 only */ ++ DMIBAR8(DMIVC0RCTL) = 1; ++ DMIBAR8(0x4) = 1; + -+ DMIBAR32(0x0020) = 0x81000080; ++ /* VC1: ID1, TC7 */ ++ DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); ++ DMIBAR8(DMIVC1RCTL) = 1 << 7; ++ ++ /* VC1: enable */ ++ DMIBAR32(DMIVC1RCTL) |= 1 << 31; ++ ++ // Hangs ++ //while ((DMIBAR8(0x26) & 2) != 0) ; ++ //printk(BIOS_DEBUG, "Done DMI loop\n"); + + DMIBAR32(0x0028) = 0x00000001; + DMIBAR32(0x002c) = 0x86000000; @@ -179,6 +192,15 @@ index 0000000..69a2741 + DMIBAR32(0x031c) = 0x003a0ca6; + DMIBAR32(0x0324) = 0x00040010; + DMIBAR32(0x0328) = 0x00040000; ++ ++ EPBAR32(0x40) = 0x00010005; ++ EPBAR32(0x44) = 0x00010301; ++ EPBAR32(0x50) = 0x01010001; ++ EPBAR32(0x58) = DEFAULT_DMIBAR; ++ EPBAR32(0x60) = 0x02010003; ++ EPBAR32(0x68) = 0x00008000; ++ EPBAR32(0x70) = 0x03000002; ++ EPBAR32(0x78) = 0x00030000; +} + +void x4x_late_init(void) |