KGPE-D16: update patch set (also update coreboot and vboot)

Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed

Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.

1 files changed, 0 insertions, 56 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch b/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch
deleted file mode 100644
index 8ab3cef..0000000
--- a/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From ae7424bea090928c8e3ebb69882ae5a8c3f2f82e Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Thu, 20 Aug 2015 12:49:49 -0500
-Subject: [PATCH 122/146] northbridge/amd/amdmct/mct_ddr3: Add cc6 setup
- information messages
-
----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   11 +++++++++++
- 1 file changed, 11 insertions(+)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index b869647..e7ab88e 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -1494,6 +1494,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
- 	if (pMCTstat->GStatus & (1 << GSB_NodeIntlv))
- 		interleaved = 1;
- 
-+	printk(BIOS_INFO, "%s: Initializing CC6 DRAM storage area for node %d (interleaved: %d)\n", __func__, pDCTstat->Node_ID, interleaved);
-+
- 	/* Find highest DRAM range (DramLimitAddr) */
- 	max_node = 0;
- 	max_range = -1;
-@@ -1517,6 +1519,9 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
- 	}
- 
- 	if (max_range >= 0) {
-+		printk(BIOS_INFO, "%s:\toriginal (node %d) max_range_limit: %16llx DRAM limit: %16llx\n", __func__, max_node, max_range_limit,
-+						(((uint64_t)(Get_NB32(pDCTstat->dev_map, 0x124) & 0x1fffff)) << 27) | 0x7ffffff);
-+
- 		if (interleaved)
- 			/* Move upper limit down by 16M * the number of nodes */
- 			max_range_limit -= (0x1000000 * num_nodes);
-@@ -1524,6 +1529,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
- 			/* Move upper limit down by 16M */
- 			max_range_limit -= 0x1000000;
- 
-+		printk(BIOS_INFO, "%s:\tnew max_range_limit: %16llx\n", __func__, max_range_limit);
-+
- 		/* Disable the range */
- 		dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8));
- 		byte = dword & 0x3;
-@@ -1558,6 +1565,10 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
- 	dword &= ~(0x3f << 12);				/* CoreSaveStateDestNode = destination_node */
- 	dword |= (destination_node & 0x3f) << 12;
- 	Set_NB32(pDCTstat->dev_link, 0x128, dword);
-+
-+	printk(BIOS_INFO, "%s:\tTarget node: %d\n", __func__, destination_node);
-+
-+	printk(BIOS_INFO, "%s:\tDone\n", __func__);
- }
- 
- static void lock_dram_config(struct MCTStatStruc *pMCTstat,
--- 
-1.7.9.5
-