New board: ASUS KGPE-D16

coreboot build errors:

In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
 static inline enum cb_err get_option(void *dest, const char *name)
                           ^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
 enum cb_err get_option(void *dest, const char *name);

Ping tpearson about this.

Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.

1 files changed, 56 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch b/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch
new file mode 100644
index 0000000..8ab3cef
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch
@@ -0,0 +1,56 @@
+From ae7424bea090928c8e3ebb69882ae5a8c3f2f82e Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+Date: Thu, 20 Aug 2015 12:49:49 -0500
+Subject: [PATCH 122/146] northbridge/amd/amdmct/mct_ddr3: Add cc6 setup
+ information messages
+
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c |   11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+index b869647..e7ab88e 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+@@ -1494,6 +1494,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+ 	if (pMCTstat->GStatus & (1 << GSB_NodeIntlv))
+ 		interleaved = 1;
+ 
++	printk(BIOS_INFO, "%s: Initializing CC6 DRAM storage area for node %d (interleaved: %d)\n", __func__, pDCTstat->Node_ID, interleaved);
++
+ 	/* Find highest DRAM range (DramLimitAddr) */
+ 	max_node = 0;
+ 	max_range = -1;
+@@ -1517,6 +1519,9 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+ 	}
+ 
+ 	if (max_range >= 0) {
++		printk(BIOS_INFO, "%s:\toriginal (node %d) max_range_limit: %16llx DRAM limit: %16llx\n", __func__, max_node, max_range_limit,
++						(((uint64_t)(Get_NB32(pDCTstat->dev_map, 0x124) & 0x1fffff)) << 27) | 0x7ffffff);
++
+ 		if (interleaved)
+ 			/* Move upper limit down by 16M * the number of nodes */
+ 			max_range_limit -= (0x1000000 * num_nodes);
+@@ -1524,6 +1529,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+ 			/* Move upper limit down by 16M */
+ 			max_range_limit -= 0x1000000;
+ 
++		printk(BIOS_INFO, "%s:\tnew max_range_limit: %16llx\n", __func__, max_range_limit);
++
+ 		/* Disable the range */
+ 		dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8));
+ 		byte = dword & 0x3;
+@@ -1558,6 +1565,10 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
+ 	dword &= ~(0x3f << 12);				/* CoreSaveStateDestNode = destination_node */
+ 	dword |= (destination_node & 0x3f) << 12;
+ 	Set_NB32(pDCTstat->dev_link, 0x128, dword);
++
++	printk(BIOS_INFO, "%s:\tTarget node: %d\n", __func__, destination_node);
++
++	printk(BIOS_INFO, "%s:\tDone\n", __func__);
+ }
+ 
+ static void lock_dram_config(struct MCTStatStruc *pMCTstat,
+-- 
+1.7.9.5
+