Update to latest coreboot revision and patch set for GA-G41M-ES2L

7 files changed, 46 insertions, 596 deletions

diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch
deleted file mode 100644
index 9fe21d4..0000000
--- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From bf128e4fc6d6a134d8d04ee0c4a392a4d98db1d4 Mon Sep 17 00:00:00 2001
-From: Damien Zammit <damien@zamaudio.com>
-Date: Wed, 11 May 2016 19:08:33 +1000
-Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA
-
-Previously, due to a bug in devicetree and incorrect IRQ
-settings in ACPI, SATA controller would not initialize
-any HDDs in the OS, even though it worked in SeaBIOS.
-The devicetree setting is not needed because SATA must
-function in "plain" mode on this board, as "combined" mode
-does not work at all.
-
-Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d
-Signed-off-by: Damien Zammit <damien@zamaudio.com>
----
-
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl
-index fdfe73d..87719f7 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl
-@@ -22,28 +22,35 @@
- 		Return (Package() {
- 			/* Internal GFX */
- 			Package() { 0x0002ffff, 0, 0, 16 },
-+			Package() { 0x0002ffff, 1, 0, 17 },
-+			Package() { 0x0002ffff, 2, 0, 18 },
-+			Package() { 0x0002ffff, 3, 0, 19 },
- 			/* High Definition Audio	0:1b.0 */
--			Package() { 0x001bffff, 0, 0, 22 },
-+			Package() { 0x001bffff, 0, 0, 16 },
- 			/* PCIe Root Ports		0:1c.x */
- 			Package() { 0x001cffff, 0, 0, 16 },
- 			Package() { 0x001cffff, 1, 0, 17 },
- 			Package() { 0x001cffff, 2, 0, 18 },
- 			Package() { 0x001cffff, 3, 0, 19 },
-+			Package() { 0x001cffff, 0, 0, 16 },
-+			Package() { 0x001cffff, 1, 0, 17 },
- 			/* USB and EHCI			0:1d.x */
- 			Package() { 0x001dffff, 0, 0, 23 },
- 			Package() { 0x001dffff, 1, 0, 19 },
- 			Package() { 0x001dffff, 2, 0, 18 },
- 			Package() { 0x001dffff, 3, 0, 16 },
--			Package() { 0x001dffff, 0, 0, 23 },
- 			/* SMBUS/SATA/PATA	0:1f.2, 0:1f.3 */
--			Package() { 0x001fffff, 1, 0, 19 },
--			Package() { 0x001fffff, 1, 0, 19 },
- 			Package() { 0x001fffff, 0, 0, 18 },
-+			Package() { 0x001fffff, 1, 0, 19 },
-+			Package() { 0x001fffff, 1, 0, 19 },
- 		})
- 	} Else {
- 		Return (Package() {
- 			/* Internal GFX */
- 			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-+			Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-+			Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- 			/* High Definition Audio	0:1b.0 */
- 			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- 			/* PCIe Root Ports		0:1c.x */
-@@ -51,16 +58,17 @@
- 			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- 			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- 			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
-+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- 			/* USB and EHCI			0:1d.x */
- 			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- 			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- 			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- 			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
--			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- 			/* SMBUS/SATA/PATA		0:1f.2, 0:1f.3 */
--			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
--			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- 			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
-+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
-+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- 		})
- 	}
- }
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
-index 3965538..c433387 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
-@@ -46,10 +46,10 @@
-       register "pirqf_routing" = "0x0b"
-       register "pirqg_routing" = "0x0b"
-       register "pirqh_routing" = "0x0b"
--      register "ide_legacy_combined" = "0x1"
-+      register "ide_legacy_combined" = "0x0"	# Combined mode broken
-       register "ide_enable_primary" = "0x1"
-       register "ide_enable_secondary" = "0x0"
--      register "sata_ahci" = "0x0"
-+      register "sata_ahci" = "0x0"		# AHCI does not work
-       register "sata_ports_implemented" = "0x3"
-       register "gpe0_en" = "0x40"
- 
diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch
deleted file mode 100644
index c08635c..0000000
--- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch
+++ /dev/null
@@ -1,222 +0,0 @@
-From 9bc6d718c1f9070fb82e09499dfc3f5d95e857c5 Mon Sep 17 00:00:00 2001
-From: Damien Zammit <damien@zamaudio.com>
-Date: Sat, 21 May 2016 01:56:01 +1000
-Subject: [PATCH] nb/intel/x4x: Add DMI/EP init
-
-The values were obtained from vendor bios at runtime.
-I am not 100% sure of the sequence required to initiate them,
-but guessed from the gm45 code.  There may be some status bytes
-needed to be polled during the sequence that is missing,
-but as I don't have bios writer's datasheet it's very hard
-for me to know.
-
-Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8
-Signed-off-by: Damien Zammit <damien@zamaudio.com>
----
-
-diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc
-index 34d9b0f..3520944 100644
---- a/src/northbridge/intel/x4x/Makefile.inc
-+++ b/src/northbridge/intel/x4x/Makefile.inc
-@@ -20,6 +20,7 @@
- romstage-y += raminit.c
- romstage-y += raminit_ddr2.c
- romstage-y += ram_calc.c
-+romstage-y += pcie.c
- 
- ramstage-y += acpi.c
- ramstage-y += ram_calc.c
-diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c
-new file mode 100644
-index 0000000..d432fea
---- /dev/null
-+++ b/src/northbridge/intel/x4x/pcie.c
-@@ -0,0 +1,176 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <stdint.h>
-+#include <stddef.h>
-+#include <string.h>
-+#include <arch/io.h>
-+#include <device/pci_def.h>
-+#include <device/pnp_def.h>
-+#include <console/console.h>
-+
-+#include "iomap.h"
-+#include "x4x.h"
-+
-+#define DEFAULT_RCBA	0xfed1c000
-+
-+static void init_egress(void)
-+{
-+	/* VC0: TC0 only */
-+	EPBAR8(0x14) = 1;
-+	EPBAR8(0x4) = 1;
-+
-+	/* VC1: ID1, TC7 */
-+	EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
-+	EPBAR8(0x20) = 1 << 7;
-+
-+	/* VC1: enable */
-+	EPBAR32(0x20) |= 1 << 31;
-+
-+	while ((EPBAR8(0x26) & 2) != 0) ;
-+
-+	printk(BIOS_DEBUG, "Done EP loop\n");
-+}
-+
-+static void init_dmi(void)
-+{
-+	/* VC0: TC0 only */
-+	DMIBAR8(DMIVC0RCTL) = 1;
-+	DMIBAR8(0x4) = 1;
-+
-+	/* VC1: ID1, TC7 */
-+	DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
-+	DMIBAR8(DMIVC1RCTL) = 1 << 7;
-+
-+	/* VC1: enable */
-+	DMIBAR32(DMIVC1RCTL) |= 1 << 31;
-+
-+	// Hangs
-+	//while ((DMIBAR8(0x26) & 2) != 0) ;
-+	//printk(BIOS_DEBUG, "Done DMI loop\n");
-+
-+	DMIBAR32(0x0028) = 0x00000001;
-+	DMIBAR32(0x002c) = 0x86000000;
-+	DMIBAR32(0x0040) = 0x08010005;
-+	DMIBAR32(0x0044) = 0x01010202;
-+	DMIBAR32(0x0050) = 0x00020001;
-+	DMIBAR32(0x0058) = DEFAULT_RCBA;
-+	DMIBAR32(0x0060) = 0x00010001;
-+	DMIBAR32(0x0068) = DEFAULT_EPBAR;
-+	DMIBAR32(0x0080) = 0x00010006;
-+	DMIBAR32(0x0084) = 0x00012c41;
-+	DMIBAR32(0x0088) = 0x00410000;
-+	DMIBAR32(0x00f0) = 0x00012000;
-+	DMIBAR32(0x00f4) = 0x33fe0037;
-+	DMIBAR32(0x00fc) = 0xf000f004;
-+
-+	DMIBAR32(0x01b0) = 0x00400000;
-+	DMIBAR32(0x01b4) = 0x00008000;
-+	DMIBAR32(0x01b8) = 0x000018f2;
-+	DMIBAR32(0x01bc) = 0x00000018;
-+	DMIBAR32(0x01cc) = 0x00060010;
-+	DMIBAR32(0x01d4) = 0x00002000;
-+	DMIBAR32(0x0200) = 0x00400f26;
-+	DMIBAR32(0x0204) = 0x0001313f;
-+	DMIBAR32(0x0208) = 0x00007cb0;
-+	DMIBAR32(0x0210) = 0x00000101;
-+	DMIBAR32(0x0214) = 0x0007000f;
-+	DMIBAR32(0x0224) = 0x00030005;
-+	DMIBAR32(0x0230) = 0x2800000e;
-+	DMIBAR32(0x0234) = 0x4abcb5bc;
-+	DMIBAR32(0x0250) = 0x00000007;
-+
-+	DMIBAR32(0x0c00) = 0x0000003c;
-+	DMIBAR32(0x0c04) = 0x16000000;
-+	DMIBAR32(0x0c0c) = 0x00001fff;
-+	DMIBAR32(0x0c10) = 0x0000b100;
-+	DMIBAR32(0x0c24) = 0xffff0038;
-+	DMIBAR32(0x0c28) = 0x0000000e;
-+	DMIBAR32(0x0c2c) = 0x003c0008;
-+	DMIBAR32(0x0c30) = 0x02000180;
-+	DMIBAR32(0x0c34) = 0x10040071;
-+	DMIBAR32(0x0d60) = 0x00000001;
-+	DMIBAR32(0x0d6c) = 0x00000300;
-+	DMIBAR32(0x0d74) = 0x00000020;
-+	DMIBAR32(0x0d78) = 0x00220000;
-+	DMIBAR32(0x0d7c) = 0x111f727c;
-+	DMIBAR32(0x0d80) = 0x00001409;
-+	DMIBAR32(0x0d88) = 0x000f1867;
-+	DMIBAR32(0x0d8c) = 0x013000fc;
-+	DMIBAR32(0x0da4) = 0x00009757;
-+	DMIBAR32(0x0da8) = 0x00000078;
-+	DMIBAR32(0x0e00) = 0x000d034e;
-+	DMIBAR32(0x0e04) = 0x01880880;
-+	DMIBAR32(0x0e08) = 0x01000060;
-+	DMIBAR32(0x0e0c) = 0x00000080;
-+	DMIBAR32(0x0e10) = 0xbe000000;
-+	DMIBAR32(0x0e18) = 0x000000e3;
-+	DMIBAR32(0x0e20) = 0x000d034e;
-+	DMIBAR32(0x0e24) = 0x01880880;
-+	DMIBAR32(0x0e28) = 0x01000060;
-+	DMIBAR32(0x0e2c) = 0x00000080;
-+	DMIBAR32(0x0e30) = 0xbe000000;
-+	DMIBAR32(0x0e38) = 0x000000e3;
-+	DMIBAR32(0x0e40) = 0x000d034e;
-+	DMIBAR32(0x0e44) = 0x01880880;
-+	DMIBAR32(0x0e48) = 0x01000060;
-+	DMIBAR32(0x0e4c) = 0x00000080;
-+	DMIBAR32(0x0e50) = 0xbe000000;
-+	DMIBAR32(0x0e58) = 0x000000e3;
-+	DMIBAR32(0x0e60) = 0x000d034e;
-+	DMIBAR32(0x0e64) = 0x01880880;
-+	DMIBAR32(0x0e68) = 0x01000060;
-+	DMIBAR32(0x0e6c) = 0x00000080;
-+	DMIBAR32(0x0e70) = 0xbe000000;
-+	DMIBAR32(0x0e78) = 0x000000e3;
-+
-+	DMIBAR32(0x0e14) = 0xce00381b;
-+	DMIBAR32(0x0e34) = 0x4000781b;
-+	DMIBAR32(0x0e54) = 0x5c00781b;
-+	DMIBAR32(0x0e74) = 0x5400381b;
-+
-+	DMIBAR32(0x0218) = 0x0b6202c1;
-+	DMIBAR32(0x021c) = 0x02c202c2;
-+
-+	DMIBAR32(0x0334) = 0x00b904b3;
-+	DMIBAR32(0x0338) = 0x004e0000;
-+
-+	DMIBAR32(0x0300) = 0x00a70f4c;
-+	DMIBAR32(0x0304) = 0x00a90f54;
-+	DMIBAR32(0x0308) = 0x00d103c4;
-+	DMIBAR32(0x030c) = 0x003c0e10;
-+	DMIBAR32(0x0310) = 0x003d0e11;
-+	DMIBAR32(0x0314) = 0x00640000;
-+	DMIBAR32(0x0318) = 0x00320c86;
-+	DMIBAR32(0x031c) = 0x003a0ca6;
-+	DMIBAR32(0x0324) = 0x00040010;
-+	DMIBAR32(0x0328) = 0x00040000;
-+
-+	EPBAR32(0x40) = 0x00010005;
-+	EPBAR32(0x44) = 0x00010301;
-+	EPBAR32(0x50) = 0x01010001;
-+	EPBAR32(0x58) = DEFAULT_DMIBAR;
-+	EPBAR32(0x60) = 0x02010003;
-+	EPBAR32(0x68) = 0x00008000;
-+	EPBAR32(0x70) = 0x03000002;
-+	EPBAR32(0x78) = 0x00030000;
-+}
-+
-+void x4x_late_init(void)
-+{
-+	init_egress();
-+	init_dmi();
-+}
-diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
-index e1ef745..17810aa 100644
---- a/src/northbridge/intel/x4x/x4x.h
-+++ b/src/northbridge/intel/x4x/x4x.h
-@@ -315,6 +315,7 @@
- 
- #ifndef __BOOTBLOCK__
- void x4x_early_init(void);
-+void x4x_late_init(void);
- u32 decode_igd_memory_size(u32 gms);
- u32 decode_igd_gtt_size(u32 gsm);
- u8 decode_pciebar(u32 *const base, u32 *const len);
diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch
deleted file mode 100644
index be8e997..0000000
--- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From 26262b2e7085fa4d8201e2519fead0dec9237d2f Mon Sep 17 00:00:00 2001
-From: Damien Zammit <damien@zamaudio.com>
-Date: Sat, 21 May 2016 01:56:53 +1000
-Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Use x4x_late_init()
-
-This patch adds DMI/EP init to the board and fixes
-a couple of minor things.
-
-Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039
-Signed-off-by: Damien Zammit <damien@zamaudio.com>
----
-
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
-index 0a26f83..31b29bb 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
-@@ -26,6 +26,9 @@
- 	select BOARD_ROMSIZE_KB_1024
- 	select INTEL_EDID
- 	select MAINBOARD_HAS_NATIVE_VGA_INIT
-+	select PCIEXP_ASPM
-+	select PCIEXP_CLK_PM
-+	select PCIEXP_L1_SUB_STATE
- 
- config MMCONF_BASE_ADDRESS
- 	hex
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
-index bff481f..6365404 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
-@@ -50,9 +50,10 @@
- 	pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
- 	pci_write_config8(dev, GPIO_CNTL, 0x10);
- 
--	outl(0x1f15f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
-+	outl(0x1f35f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
- 	outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
--	outl(0xe0d7fcc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
-+	outl(0xe0d7ec02, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
-+	outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
- 	outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
- 	outl(0x000000e7, DEFAULT_GPIOBASE + 0x30);
- 	outl(0x000000f0, DEFAULT_GPIOBASE + 0x34);
-@@ -66,9 +67,9 @@
- 	ite_reg_write(GPIO_DEV, 0x29, 0x0a);
- 	ite_reg_write(GPIO_DEV, 0x2c, 0x01);
- 	ite_reg_write(GPIO_DEV, 0x62, 0x08);
--	ite_reg_write(GPIO_DEV, 0x62, 0x08);
- 	ite_reg_write(GPIO_DEV, 0x72, 0x00);
- 	ite_reg_write(GPIO_DEV, 0x73, 0x00);
-+	ite_reg_write(GPIO_DEV, 0xb8, 0x00);
- 	ite_reg_write(GPIO_DEV, 0xbb, 0x40);
- 	ite_reg_write(GPIO_DEV, 0xc0, 0x00);
- 	ite_reg_write(GPIO_DEV, 0xc1, 0xc7);
-@@ -89,6 +90,7 @@
- 	ite_reg_write(EC_DEV, 0xf2, 0x0a);
- 	ite_reg_write(EC_DEV, 0xf3, 0x80);
- 	ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
-+	ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
- 
- 	/* IRQ routing */
- 	RCBA32(0x3100) = 0x00002210;
-@@ -98,10 +100,23 @@
- 	RCBA32(0x3110) = 0x00000001;
- 	RCBA32(0x3140) = 0x00410032;
- 	RCBA32(0x3144) = 0x32100237;
-+	RCBA32(0x3148) = 0x00000000;
- 
- 	/* Enable IOAPIC */
- 	RCBA8(0x31ff) = 0x03;
- 	RCBA8(0x31ff);
-+
-+	RCBA32(0x3410) = 0x00190464;
-+	RCBA32(0x3418) = 0x003c0063;
-+	RCBA32(0x341c) = 0x00000000;
-+	RCBA32(0x3430) = 0x00000001;
-+	RCBA32(0x3e00) = 0xff000001;
-+	RCBA32(0x3e08) = 0x00000080;
-+	RCBA32(0x3e0c) = 0x00800000;
-+	RCBA32(0x3e40) = 0xff000001;
-+	RCBA32(0x3e48) = 0x00000080;
-+	RCBA32(0x3e4c) = 0x00800000;
-+	RCBA32(0x3f00) = 0x0000000b;
- }
- 
- static void ich7_enable_lpc(void)
-@@ -126,9 +141,8 @@
- 	RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
- 
- 	/* Set southbridge and Super I/O GPIOs. */
--	mb_gpio_init();
--
- 	ich7_enable_lpc();
-+	mb_gpio_init();
- 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- 
- 	/* Disable SIO reboot */
-@@ -146,4 +160,9 @@
- 	quick_ram_check();
- 	cbmem_initialize_empty();
- 	printk(BIOS_DEBUG, "Memory initialized\n");
-+
-+	x4x_late_init();
-+
-+	printk(BIOS_DEBUG, "x4x late init complete\n");
-+
- }
diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0005-update-board-info.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0005-update-board-info.patch
deleted file mode 100644
index 5e45fbc..0000000
--- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0005-update-board-info.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From ae837e942d751aaf9a7f5b9ed5fba687abbd1dde Mon Sep 17 00:00:00 2001
-From: Damien Zammit <damien@zamaudio.com>
-Date: Tue, 24 May 2016 17:26:51 +1000
-Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Update board_info.txt and add item to Kconfig
-
-This adds the website URL to the board info and also enables
-the realtek nic reset function as per a previous patch.
-
-Change-Id: I2cda120c59b55f0dd2ffa78d397b16beb13d6843
-Signed-off-by: Damien Zammit <damien@zamaudio.com>
----
-
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
-index 31b29bb..7dec921 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
-@@ -29,6 +29,7 @@
- 	select PCIEXP_ASPM
- 	select PCIEXP_CLK_PM
- 	select PCIEXP_L1_SUB_STATE
-+	select REALTEK_8168_RESET
- 
- config MMCONF_BASE_ADDRESS
- 	hex
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt
-index 44ed73a..170449e 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt
-@@ -1,5 +1,5 @@
- Category: desktop
--Board URL:
-+Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=3024#ov
- ROM package: SOIC-8
- ROM protocol: SPI
- ROM socketed: n
diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch
deleted file mode 100644
index 7d1d1c5..0000000
--- a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch
+++ /dev/null
@@ -1,133 +0,0 @@
-From 8f90ec9634e7eb0a385902fe2d74af4ebc33c7c2 Mon Sep 17 00:00:00 2001
-From: Damien Zammit <damien@zamaudio.com>
-Date: Sat, 21 May 2016 02:24:19 +1000
-Subject: [PATCH] drivers/net/r8168: Add driver for realtek nic
-
-One thing that is vital to this patch is the MAC address setting
-in case the EEPROM/efuse is unconfigured.
-Linux now recognises the default MAC address on GA-G41M-ES2L which
-does rely on the default bios settings for the MAC address.
-
-Change-Id: I32e070b545b4c6369686a7087b7ff838d00764e3
-Signed-off-by: Damien Zammit <damien@zamaudio.com>
----
-
-diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig
-new file mode 100644
-index 0000000..b4bafd2
---- /dev/null
-+++ b/src/drivers/net/Kconfig
-@@ -0,0 +1,5 @@
-+config REALTEK_8168_RESET
-+	bool "Realtek 8168 reset"
-+	help
-+	  This forces a realtek 10ec:8168 card to reset to ensure power state
-+	  is correct at boot.
-diff --git a/src/drivers/net/Makefile.inc b/src/drivers/net/Makefile.inc
-index 9b3008d..e435d48 100644
---- a/src/drivers/net/Makefile.inc
-+++ b/src/drivers/net/Makefile.inc
-@@ -1,2 +1,3 @@
- romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
- ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
-+ramstage-$(CONFIG_REALTEK_8168_RESET) += r8168.c
-diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c
-new file mode 100644
-index 0000000..4301693
---- /dev/null
-+++ b/src/drivers/net/r8168.c
-@@ -0,0 +1,94 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * This driver forces the 10ec:8168 device to reset so that it goes
-+ * into a proper power state, also programs a default MAC address
-+ * so that if the EEPROM/efuse is unconfigured it still has a default MAC.
-+ */
-+
-+#include <arch/io.h>
-+#include <device/device.h>
-+#include <device/pci.h>
-+#include <device/pci_ops.h>
-+#include <device/pci_def.h>
-+#include <delay.h>
-+#include <console/console.h>
-+
-+#define NIC_TIMEOUT		1000
-+
-+#define CMD_REG			0x37
-+#define  CMD_REG_RESET		0x10
-+
-+#define CFG_9346		0x50
-+#define  CFG_9346_LOCK		0x00
-+#define  CFG_9346_UNLOCK	0xc0
-+
-+static void r8168_init(struct device *dev)
-+{
-+	u32 i;
-+	const u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 };
-+
-+	/* Get the resource of the NIC mmio */
-+	struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0);
-+	u16 nic_port = (u16)nic_res->base;
-+
-+	/* Set bus master */
-+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER
-+					| PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-+
-+	/* Reset NIC */
-+	printk(BIOS_DEBUG, "r8168: Resetting NIC...");
-+	outb(CMD_REG_RESET, nic_port + CMD_REG);
-+
-+	i = 0;
-+	/* Poll for reset, with 1s timeout */
-+	while (i < NIC_TIMEOUT && (inb(nic_port + CMD_REG) & CMD_REG_RESET)) {
-+		udelay(1000);
-+		if (++i >= NIC_TIMEOUT)
-+			printk(BIOS_DEBUG, "timeout waiting for nic to reset\n");
-+	}
-+	if (i < NIC_TIMEOUT)
-+		printk(BIOS_DEBUG, "done\n");
-+
-+	/* Unlock config regs */
-+	outb(CFG_9346_UNLOCK, nic_port + CFG_9346);
-+
-+	/* Set MAC address 00:e0:4c:00:c0:b0
-+	 * NB: only 4-byte write accesses allowed
-+	 */
-+	outl(mac[4] | mac[5] << 8, nic_port + 4);
-+	inl(nic_port + 4);
-+
-+	outl(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, nic_port);
-+	inl(nic_port);
-+
-+	/* Lock config regs */
-+	outb(CFG_9346_LOCK, nic_port + CFG_9346);
-+}
-+
-+static struct device_operations r8168_ops  = {
-+       .read_resources   = pci_dev_read_resources,
-+       .set_resources    = pci_dev_set_resources,
-+       .enable_resources = pci_dev_enable_resources,
-+       .init             = r8168_init,
-+       .scan_bus         = 0,
-+};
-+
-+static const struct pci_driver r8168_driver __pci_driver = {
-+        .ops    = &r8168_ops,
-+        .vendor = 0x10ec,
-+        .device = 0x8168,
-+};
diff --git a/resources/libreboot/patch/coreboot/3a96ac44e275eca84baea513bc0802f62fe83fd3/grub/ga-g41m-es2l/x4x-fix-cas-latency-detection.patch b/resources/libreboot/patch/coreboot/3a96ac44e275eca84baea513bc0802f62fe83fd3/grub/ga-g41m-es2l/x4x-fix-cas-latency-detection.patch
new file mode 100644
index 0000000..ebf82a3
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/3a96ac44e275eca84baea513bc0802f62fe83fd3/grub/ga-g41m-es2l/x4x-fix-cas-latency-detection.patch
@@ -0,0 +1,46 @@
+From 267362bd16715216e0fb7af54d60ebaeaf6250ae Mon Sep 17 00:00:00 2001
+From: Damien Zammit <damien@zamaudio.com>
+Date: Sun, 17 Jul 2016 18:26:18 +1000
+Subject: [PATCH] nb/intel/x4x: Fix CAS latency detection
+
+Fix and use the failsafe CAS detection logic rather than
+recalulating the values from raw SPDs.
+
+Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs
+(which worked before and still work)
+
+Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01
+Signed-off-by: Damien Zammit <damien@zamaudio.com>
+---
+
+diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
+index 5d341db..9be2cd3 100644
+--- a/src/northbridge/intel/x4x/raminit.c
++++ b/src/northbridge/intel/x4x/raminit.c
+@@ -111,10 +111,10 @@
+ 			s->dimms[i].chip_capacity = s->dimms[i].banks;
+ 			s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12;
+ 			s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9;
+-			s->dimms[i].cas_latencies = 0x78;
++			s->dimms[i].cas_latencies = 0x70; // 6,5,4 CL
+ 			s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18];
+ 			if (s->dimms[i].cas_latencies == 0)
+-				s->dimms[i].cas_latencies = 7;
++				s->dimms[i].cas_latencies = 0x70;
+ 			s->dimms[i].tAAmin = s->dimms[i].spd_data[26];
+ 			s->dimms[i].tCKmin = s->dimms[i].spd_data[25];
+ 			s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1;
+@@ -337,10 +337,10 @@
+ 		// Choose max memory frequency for MCH as previously detected
+ 		freq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;
+ 
+-		// Detect a common CAS latency
+-		commoncas = 0xff;
++		// Detect a common CAS latency (Choose from 6,5,4 CL)
++		commoncas = 0x70;
+ 		FOR_EACH_POPULATED_DIMM(s->dimms, i) {
+-			commoncas &= s->dimms[i].spd_data[18];
++			commoncas &= s->dimms[i].cas_latencies;
+ 		}
+ 		if (commoncas == 0) {
+ 			die("No common CAS among dimms\n");
diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/reused.list
deleted file mode 100644
index f64e59b..0000000
--- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/reused.list
+++ /dev/null
@@ -1 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch