diff options
| author | Francis Rowe <info@gluglug.org.uk> | 2014-07-28 18:33:00 (EDT) |
|---|---|---|
| committer | Michał Masłowski <mtjm@mtjm.eu> | 2014-08-22 14:19:33 (EDT) |
| commit | 7eca665d684a734d55b0bb26c4f1831d399c5330 (patch) | |
| tree | 01b0e5bd983ae30b6f545d0d1d0cec4d7cc9b01d | |
| parent | 488242eb941305ef61319b8499d4a1e8ccf218a1 (diff) | |
| download | libreboot-r20140729.zip libreboot-r20140729.tar.gz libreboot-r20140729.tar.bz2 | |
Libreboot release 6 beta 4.r20140729
- Documentation: improved (more explanations, background info) in
docs/howtos/x60_security.html (courtesy of Denis Carikli)
- MacBook2,1 tested (confirmed)
- macbook21: Added script 'macbook21_firstflash' for flashing
libreboot while Apple EFI firmware is running.
- Documentation: macbook21: added software-based flashing instructions
for flashing libreboot while Apple EFI firmware is running.
- Reduced size of libreboot_src.tar.gz:
- Removed .git and .gitignore from grub directory (libreboot_src);
not needed. Removing them reduces the size of the archive (by a
lot). GRUB development should be upstream.
- Removed .git and .gitignore from bucts directory (libreboot_src);
not needed. Removing them reduces the size of the archive. bucts
development should be upstream.
- Removed .svn from flashrom directory (libreboot_src); not
needed. Removing it reduces the size of the archive. flashrom
development should be upstream.
- Added ROM's with Qwerty (Italian) layout in GRUB
(libreboot*itqwerty.rom)
- Added resources/utilities/i945gpu/intel-regs.py for debugging issues
related to LCD panel compatibility on X60 Tablet and T60. (courtesy
of Michał Masłowski)
42 files changed, 11486 insertions, 149 deletions
@@ -136,7 +136,7 @@ cp -r resources ../libreboot_bin cp lenovobios_firstflash ../libreboot_bin cp lenovobios_secondflash ../libreboot_bin -# Flashrom script (makes flashing easier: ./flash path/to/coreboot.rom) +# Flashrom script (makes flashing easier: ./flash path/to/libreboot.rom) cp flash ../libreboot_bin # patch the version of cbfstool included in libreboot_bin, @@ -42,7 +42,7 @@ ./builddeps-memtest86 -# Build BUC.TS utility (needed for flashing ROM's on X60/T60 while Lenovo BIOS is running) +# Build BUC.TS utility (needed for flashing ROM's on X60/T60/X60T while Lenovo BIOS is running) # -------------------------------------------------------------------- ./builddeps-bucts diff --git a/buildrom-withgrub b/buildrom-withgrub index 49e3b05..c7eb280 100755 --- a/buildrom-withgrub +++ b/buildrom-withgrub @@ -110,12 +110,12 @@ do ./cbfstool libreboot_serial_"$keymap".rom add -f grub_serial_"$keymap".cfg -n grub.cfg -t raw done -# Now we clean up and prepare the binary archive ready for release. -# ---------------------------------------------------------------------------------------------------------------------------- - # we don't need the grub.cfg's anymore rm -rf grub*cfg +# Now we clean up and prepare the binary archive ready for release. +# ---------------------------------------------------------------------------------------------------------------------------- + # prepare directory for new ROM images rm -rf $1 mkdir $1 @@ -32,6 +32,10 @@ make clean cd util/cbfstool make clean +# clean nvramtool +cd ../nvramtool +make clean + # go back to coreboot dir cd ../../ diff --git a/docs/RELEASE.html b/docs/RELEASE.html index 6e12ca7..7e1456a 100644 --- a/docs/RELEASE.html +++ b/docs/RELEASE.html @@ -32,7 +32,7 @@ <h2>Releases</h2> <ul> - <li><a href="#release6">6th release</a> (2014 July 20th, <b>pre-release, 3rd beta</b>)</h1> + <li><a href="#release6">6th release</a> (2014 July 29th, <b>pre-release, 4th beta</b>)</h1> <li><a href="#release5">5th release</a> (2014 March 7th, revised 2014 June 22nd)</h1> <li><a href="#release4">4th release</a> (2014 February 21st)</h1> <li><a href="#release3">3rd release</a> (2013 December 14th)</h1> @@ -52,12 +52,13 @@ <hr/> - <h1 id="release6">6th release (pre-release, 3rd beta)</h1> + <h1 id="release6">6th release (pre-release, 4th beta)</h1> <ul> <li>Released 2014 July 11th (pre-release) 1st beta</li> <li>Revised (pre-release, 2nd beta) 2014 July 16th</li> <li>Revised (pre-release, 3rd beta) 2014 July 20th</li> + <li>Revised (pre-release, 4th beta) 2014 July 29th</li> </ul> <div class="important"> @@ -68,23 +69,23 @@ </p> </div> - <h2>Binaries (for flashing)</h2> + <h2>Binaries (for flashing) (right-click save as, or use wget)</h2> <ul> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_bin.tar.gz">http://libreboot.org/release/5/prerelease_beta3/libreboot_bin.tar.gz</a></li> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_bin.tar.gz.gpg.sig">http://libreboot.org/release/5/prerelease_beta3/libreboot_bin.tar.gz.gpg.sig</a></li> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_bin.tar.gz.sha512sum.txt">http://libreboot.org/release/5/prerelease_beta3/libreboot_bin.tar.gz.sha512sum.txt</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_bin.tar.gz">http://libreboot.org/release/5/prerelease_beta4/libreboot_bin.tar.gz</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_bin.tar.gz.sig">http://libreboot.org/release/5/prerelease_beta4/libreboot_bin.tar.gz.sig</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_bin.tar.gz.sha512sum.txt">http://libreboot.org/release/5/prerelease_beta4/libreboot_bin.tar.gz.sha512sum.txt</a></li> </ul> - <h2>Source code (for hacking)</h2> + <h2>Source code (for hacking) (right-click save as, or use wget)</h2> <ul> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_src.tar.gz">http://libreboot.org/release/5/prerelease_beta3/libreboot_src.tar.gz</a></li> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_src.tar.gz.gpg.sig">http://libreboot.org/release/5/prerelease_beta3/libreboot_src.tar.gz.gpg.sig</a></li> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_src.tar.gz.sha512sum.txt">http://libreboot.org/release/5/prerelease_beta3/libreboot_src.tar.gz.sha512sum.txt</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_src.tar.gz">http://libreboot.org/release/5/prerelease_beta4/libreboot_src.tar.gz</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_src.tar.gz.sig">http://libreboot.org/release/5/prerelease_beta4/libreboot_src.tar.gz.sig</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_src.tar.gz.sha512sum.txt">http://libreboot.org/release/5/prerelease_beta4/libreboot_src.tar.gz.sha512sum.txt</a></li> </ul> - <h2>Metadata (for re-creating the source archive)</h2> + <h2>Metadata (for re-creating the source archive) (right-click save as, or use wget)</h2> <ul> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_meta.tar.gz">http://libreboot.org/release/5/prerelease_beta3/libreboot_meta.tar.gz</a></li> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_meta.tar.gz.gpg.sig">http://libreboot.org/release/5/prerelease_beta3/libreboot_meta.tar.gz.gpg.sig</a></li> - <li><a href="http://libreboot.org/release/5/prerelease_beta3/libreboot_meta.tar.gz.sha512sum.txt">http://libreboot.org/release/5/prerelease_beta3/libreboot_meta.tar.gz.sha512sum.txt</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_meta.tar.gz">http://libreboot.org/release/5/prerelease_beta4/libreboot_meta.tar.gz</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_meta.tar.gz.sig">http://libreboot.org/release/5/prerelease_beta4/libreboot_meta.tar.gz.sig</a></li> + <li><a href="http://libreboot.org/release/5/prerelease_beta4/libreboot_meta.tar.gz.sha512sum.txt">http://libreboot.org/release/5/prerelease_beta4/libreboot_meta.tar.gz.sha512sum.txt</a></li> </ul> <h2>Machines still supported (compared to previous release):</h2> @@ -125,6 +126,9 @@ </p> <h2><u>*</u> T60 (microcode): some CPU's might not work (can be replaced)</h2> <p> + Also see <a href="future/index.html#t60_cpu_microcode">future/index.html#t60_cpu_microcode</a>. + </p> + <p> A user with 2 T60's, each with a Core 2 Duo T7200 processor tried libreboot on each machine. One worked, one did not. It should be explained that in addition to the microcode (on the CPU), updates are usually supplied in coreboot (from Intel) which patch the onboard microcode to fix bugs. @@ -145,12 +149,6 @@ <p> If reading this for 2nd beta, note that any debugging obtained so far will be included in the 3rd beta. </p> - <h2><u>**</u> Warning: MacBook2,1 <u>UNTESTED</u>!</h2> - <p> - At the time of this pre-release, MacBook2,1 support is present but untested. I have ordered a MacBook2,1 - but it has not yet arrived at the time of writing. - I take it merely on faith that these images even work at all. <b>Use at your own risk!</b> - </p> </div> <h2>Machines no longer supported (compared to previous release):</h2> <ul> @@ -382,7 +380,7 @@ </li> <li> Documentation: added (preliminary) details about (rare) buggy CPU's on the ThinkPad T60 that were found to fail (instability, kernel panics, etc) - without the microcode updates. + without the microcode updates. </li> <li>Documentation: added docs/howtos/x60_heatsink.html for showing how to change the heatsink on the Thinkpad X60</li> <li>Added ROM images for Azerty (French) keyboard layout in GRUB (courtesy of Olivier Mondoloni)</li> @@ -403,8 +401,8 @@ <li>Replaced background.png with background.jpg. added gnulove.jpg. (resources/grub/background/)</li> <li>Updated buildrom-withgrub to use background.jpg instead of background.png</li> <li>Updated buildrom-withgrub to use gnulove.jpg aswell</li> - <li>Updated resources/grub/macbook21/grub*cfg to use gnulove.jpg background.</li> - <li>Updated resources/grub/{x60,t60,x60t}/grub*cfg to use background.jpg background.</li> + <li>Updated resources/grub/config/macbook21/grub*cfg to use gnulove.jpg background.</li> + <li>Updated resources/grub/config/{x60,t60,x60t}/grub*cfg to use background.jpg background.</li> <li>Documentation: updated docs/index.html#grub_custom_keyboard to be more generally useful.</li> <li> nvramtool: @@ -418,12 +416,65 @@ </li> </ul> + <h2> + Revisions for 4th beta (2014 July 29th) + </h2> + <ul> + <li>Documentation: improved (more explanations, background info) in docs/howtos/x60_security.html (courtesy of Denis Carikli)</li> + <li>MacBook2,1 tested (confirmed)</li> + <li>macbook21: Added script 'macbook21_firstflash' for flashing libreboot while Apple EFI firmware is running.</li> + <li>Documentation: macbook21: added software-based flashing instructions for flashing libreboot while Apple EFI firmware is running.</li> + <li> + Reduced size of libreboot_src.tar.gz: + <ul> + <li> + Removed .git and .gitignore from grub directory (libreboot_src); not needed. + Removing them reduces the size of the archive (by a lot). GRUB development should be upstream. + </li> + <li> + Removed .git and .gitignore from bucts directory (libreboot_src); not needed. + Removing them reduces the size of the archive. bucts development should be upstream. + </li> + <li> + Removed .svn from flashrom directory (libreboot_src); not needed. + Removing it reduces the size of the archive. flashrom development should be upstream. + </li> + </ul> + </li> + <li> + Added ROM's with Qwerty (Italian) layout in GRUB (libreboot*itqwerty.rom) + </li> + <li> + Added resources/utilities/i945gpu/intel-regs.py for debugging issues related to LCD panel compatibility on X60 Tablet and T60. (courtesy of <a href="http://mtjm.eu">Michał Masłowski</a>) + </li> + </ul> + <div class="important"> <h2> Other tasks (to be completed before declaring the initial stable release) </h2> <ul> + <li> + <b><u><i>TODO:</i></u></b> Fix remaining incompatible LCD panels in native graphics on X60 Tablet and T60. + (see <a href="future/index.html#lcd_i945_incompatibility">future/index.html#lcd_i945_incompatibility</a>) and <b>submit patches upstream</b>. + </li> + <li> + <b><u><i>TODO:</i></u></b> Implement VBT on X60/T60/X60T (and macbook21?) + (see <a href="future/index.html#i945_vbt">future/index.html#i945_vbt</a> and + <a href="future/index.html#intelvbttool_results">future/index.html#intelvbttool_results</a>) and <b>submit changes upstream</b>. + </li> + <li> + <b><u><i>TODO:</i></u></b> Submit 3D fix (for X60/T60/macbook21/X60T on kernel 3.12+) upstream for 5320 changeset. + </li> + <li> + <b><u><i>TODO:</i></u></b> Add modules (see 'build' script) for cryptomount/luks in grub.elf + </li> + <li> + <b><u><i>TODO:</i></u></b> Fix remaining incompatible LCD panels in native graphics on X60 Tablet and T60. + (see <a href="future/index.html#lcd_i945_incompatibility">future/index.html#lcd_i945_incompatibility</a>) and <b>submit patches upstream</b>. + </li> <li><b><u><i>TODO:</i></u></b> Re-tooled linux-libre deblob scripts for use with coreboot. <b>Deblobbing is already complete; completion of this additional task will simply make future deblobbing work easier.</b></li> + <li><b><u><i>TODO:</i></u></b> Remove mention of blob/3rdparty repository in Kconfig</li> <li> <b><u><i>TODO:</i></u></b> Modified coreboot to make wifi and trackpoint be enabled by default on the ThinkPad X60 (so no need for nvramtool) <ul> @@ -443,7 +494,13 @@ </li> </ul> </li> - <li><b><u><i>TODO:</i></u></b> T60: find (for rare buggy CPU's that are unstable without microcode updates) if there is a workaround (patched kernel, special parameter, etc)</li> + <li> + <b><u><i>TODO:</i></u></b> make writing the cmos.layout to the rom default + </li> + <li> + <b><u><i>TODO:</i></u></b> T60: find (for rare buggy CPU's that are unstable without microcode updates) + if there is a workaround: see <a href="future/index.html#t60_cpu_microcode">future/index.html#t60_cpu_microcode</a> + </li> <li><b><u><i>TODO:</i></u></b> Modify coreboot so that tft_brightness is 0xff by default (for fixing the looping issue automatically)</li> <li><b><u><i>TODO:</i></u></b> Modify the Kconfig options in coreboot so that the (non-existent, deleted) microcode is never loaded when building.</li> <li><b><u><i>TODO:</i></u></b> Ask Mono what license he wants to use for his pages (see notes in docs/index.html#macbook21) and then include a copy in the relevant part of the documentation. (note: the backups are not included for now, for this exact reason)</li> @@ -451,7 +508,6 @@ <li><b><u><i>TODO:</i></u></b> For the gitdiff in resources/libreboot/patch, re-implement those changes as actual commits in git, using separate patch files for each change.</li> <li><b><u><i>TODO:</i></u></b> Made the lenovobios_firstflash and lenovobios_secondflash scripts safer to use (checking for unintended errors, bad checksums and so on)</li> <li><b><u><i>TODO:</i></u></b> Tested all of the remaining untested LCD panels under docs/index.html#supported_t60_list</li> - <li><b><u><i>TODO:</i></u></b> macbook21: from what I can tell, macbook21 has no dock or serial. investigate usbdebug and spkmodem option.</li> <li><b><u><i>TODO:</i></u></b> Documentation: Added macbook2,1 unbricking tutorial.</li> <li><b><u><i>TODO:</i></u></b> Documentation: macbook2,1: Show how to physically remove the built-in webcam (which doesn't work unless you install a non-free driver)</li> <li><b><u><i>TODO:</i></u></b> Documentation: macbook2,1: Check if there is another webcam to replace it that can work without requiring any non-free drivers.</li> @@ -472,8 +528,6 @@ </li> <li><b><u><i>TODO:</i></u></b> Documentation: Added (replicated) the same level of logs (from default firmware) that Mono did for macbook21, for t60/x60/x60t</li> <li><b><u><i>TODO:</i></u></b> Documentation: Write documentation showing how to install a GNU/Linux distribution on a macbook2,1 while stock (non-free) firmware is running.</li> - <li><b><u><i>TODO:</i></u></b> macbook21: Added script 'macbook21_firstflash' for flashing libreboot while Apple EFI firmware is running.</li> - <li><b><u><i>TODO:</i></u></b> Documentation: macbook21: added software-based flashing instructions for flashing libreboot while Apple EFI firmware is running.</li> <li><b><u><i>TODO:</i></u></b> Documentation: updated the X60 unbrick tutorial to use the 5-pin method instead (safer / less dangerous).</li> <li><b><u><i>TODO:</i></u></b> Documentation: added unbricking tutorial for T60</li> <li><b><u><i>TODO:</i></u></b> Documentation: Advise what parts of the unbricking tutorial to follow (or skip) for replacing motherboard</li> @@ -489,6 +543,15 @@ <li><a href="x60.config">kernel .config file</a></li> </ul> </li> + <li> + <b><u><i>TODO:</i></u></b> <a href="http://forum.tabletpcreview.com/lenovo-ibm/9778-x61-tablet-icc-profile-sxga.html">http://forum.tabletpcreview.com/lenovo-ibm/9778-x61-tablet-icc-profile-sxga.html</a> + was reported by a user, saying: xcalib can be used (the icm file also works on X60. Note: it's for X61/X60 Tablet which use + IPS (different) screens), with the icm file that they have. Investigate this. + </li> + <li> + <b><u><i>TODO:</i></u></b><a href="https://wiki.archlinux.org/index.php/TLP">https://wiki.archlinux.org/index.php/TLP</a> (example article) a user + mentioned that this also removes the high-pitched noise (like powertop does). Must look into this. + </li> </ul> </div> diff --git a/docs/future/coreboot_native_3.12_bug.tar.gz b/docs/future/coreboot_native_3.12_bug.tar.gz Binary files differnew file mode 100644 index 0000000..3564198 --- /dev/null +++ b/docs/future/coreboot_native_3.12_bug.tar.gz diff --git a/docs/future/dumps/5320_7c0000_gma.c b/docs/future/dumps/5320_7c0000_gma.c new file mode 100644 index 0000000..04a70dc --- /dev/null +++ b/docs/future/dumps/5320_7c0000_gma.c @@ -0,0 +1,519 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <bootmode.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include "i945.h" +#include "chip.h" +#include <edid.h> +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include <string.h> + +#define GDRST 0xc0 + +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define DISPPLANE_BGRX888 (0x6<<26) +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ + +#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) + +#define PGETBL_CTL 0x2020 +#define PGETBL_ENABLED 0x00000001 + +#define BASE_FREQUENCY 120000 + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +static int gtt_setup(unsigned int mmiobase) +{ + unsigned long PGETBL_save; + + PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + PGETBL_save |= PGETBL_ENABLED; + + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= 2; /* set GTT to 256kb */ + + // hack!!! + PGETBL_save += 0x7c0000; // ugly hack. from 5927/3. Must calculate it properly! + /// hack!!! + + write32(mmiobase + GFX_FLSH_CNTL, 0); + + write32(mmiobase + PGETBL_CTL, PGETBL_save); + + /* verify */ +/* // old + if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); +*/ + // Hack. Must do properly later: + PGETBL_save = read32(mmiobase + PGETBL_CTL); + if (PGETBL_save & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled: GTT PGETLB_CTL register: 0x%lx\n", PGETBL_save); + // end hack + } else { + printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); + return 1; + } + write32(mmiobase + GFX_FLSH_CNTL, 0); + + return 0; +} + +static int intel_gma_init(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + unsigned int pmmio, unsigned int pgfx) +{ + struct edid edid; + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; + + pphysbase += 0x20000; + + printk(BIOS_SPEW, + "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + (void *)pgfx, pmmio, piobase, pphysbase); + + intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, sizeof(edid_data), &edid); + + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = edid.hborder; + bottom_border = edid.vborder; + vblank = edid.vbl; + hblank = edid.hbl; + vsync = edid.vspw; + hsync = edid.hspw; + hfront_porch = edid.hso; + vfront_porch = edid.vso; + + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + /* R=j, G=j, B=j. */ + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); + + write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + /* Clean registers. */ + for (i = 0; i < 0x20; i += 4) + write32(pmmio + RENDER_RING_BASE + i, 0); + for (i = 0; i < 0x20; i += 4) + write32(pmmio + FENCE_REG_965_0 + i, 0); + write32(pmmio + PP_ON_DELAYS, 0); + write32(pmmio + PP_OFF_DELAYS, 0); + + /* Disable VGA. */ + write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); + + /* Disable pipes. */ + write32(pmmio + PIPECONF(0), 0); + write32(pmmio + PIPECONF(1), 0); + + /* Init PRB0. */ + write32(pmmio + HWS_PGA, 0x352d2000); + write32(pmmio + PRB0_CTL, 0); + write32(pmmio + PRB0_HEAD, 0); + write32(pmmio + PRB0_TAIL, 0); + write32(pmmio + PRB0_START, 0); + write32(pmmio + PRB0_CTL, 0x0001f001); + + write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF + | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); + write32(pmmio + ECOSKPD, 0x00010000); + write32(pmmio + HWSTAM, 0xeffe); + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + + target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + + BASE_FREQUENCY / 2) / BASE_FREQUENCY; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (BASE_FREQUENCY * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock + ? "Spread spectrum clock\n" + : "DREF clock\n")); + printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel + ? "Dual channel\n" + : "Single channel\n")); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) + | (pixel_p1 << 16) + | (pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) + | (pixel_p1 << 16) + | (pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(pmmio + HBLANK(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(pmmio + HSYNC(1), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(pmmio + VSYNC(1), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); + + /* Disable panel fitter (we're in native resolution). */ + write32(pmmio + PF_CTL(0), 0); + write32(pmmio + PF_WIN_SZ(0), 0); + write32(pmmio + PF_WIN_POS(0), 0); + write32(pmmio + PFIT_PGM_RATIOS, 0); + write32(pmmio + PFIT_CONTROL, 0); + + mdelay(1); + + write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio + DSPPOS(0), 0); + + /* Backlight init. */ + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC, 0x011d011a); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC_SELF, 0x0001003f); + write32(pmmio + FW_BLC, 0x011d0109); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + mdelay(1); + + write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); + write32(pmmio + LVDS, LVDS_ON + | (hpolarity << 20) | (vpolarity << 21) + | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_PIPE(1)); + + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(pmmio + PP_STATUS); + if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Clear interrupts. */ + write32(pmmio + DEIIR, 0xffffffff); + write32(pmmio + SDEIIR, 0xffffffff); + write32(pmmio + IIR, 0xffffffff); + write32(pmmio + IMR, 0xffffffff); + write32(pmmio + EIR, 0xffffffff); + + /* GTT is the Global Translation Table for the graphics pipeline. + * It is used to translate graphics addresses to physical + * memory addresses. As in the CPU, GTTs map 4K pages. + * There are 32 bits per pixel, or 4 bytes, + * which means 1024 pixels per page. + * There are 4250 GTTs on Link: + * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. + * The setgtt function adds a further bit of flexibility: + * it allows you to set a range (the first two parameters) to point + * to a physical address (third parameter);the physical address is + * incremented by a count (fourth parameter) for each GTT in the + * range. + * Why do it this way? For ultrafast startup, + * we can point all the GTT entries to point to one page, + * and set that page to 0s: + * memset(physbase, 0, 4096); + * setgtt(0, 4250, physbase, 0); + * this takes about 2 ms, and is a win because zeroing + * the page takes a up to 200 ms. We will be exploiting this + * trick in a later rev of this code. + * This call sets the GTT to point to a linear range of pages + * starting at physbase. + */ + + if (gtt_setup(pmmio)) { + printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + return 0; + } + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(pphysbase + (i << 12) + 1, piobase + 4); + } + + temp = read32(pmmio + PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + + if (temp & 1) + printk(BIOS_INFO, "GTT Enabled\n"); + else + printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + + printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", + (void *)pgfx, hactive * vactive * 4); + memset((void *)pgfx, 0x00, hactive * vactive * 4); + + set_vbe_mode_info_valid(&edid, pgfx); + + return 0; +} +#endif + +static void gma_func0_init(struct device *dev) +{ + u32 reg32; + + /* Unconditionally reset graphics */ + pci_write_config8(dev, GDRST, 1); + udelay(50); + pci_write_config8(dev, GDRST, 0); + /* wait for device to finish */ + while (pci_read_config8(dev, GDRST) & 1) { }; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); +#endif + + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* This should probably run before post VBIOS init. */ + printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); + u32 iobase, mmiobase, graphics_base; + struct northbridge_intel_i945_config *conf = dev->chip_info; + + iobase = dev->resource_list[1].base; + mmiobase = dev->resource_list[0].base; + graphics_base = dev->resource_list[2].base; + + printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", + pci_read_config32(dev, 0x18), + pci_read_config32(dev, 0x1c) + ); + + int err; + err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); +#endif +} + +/* This doesn't reclaim stolen UMA memory, but IGD could still + be reenabled later. */ +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + + pci_write_config16(dev, GCFC, 0xa00); + pci_write_config16(dev_host, GGC, (1 << 1)); + + unsigned int reg32 = pci_read_config32(dev_host, DEVEN); + reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); + pci_write_config32(dev_host, DEVEN, reg32); + + dev->enabled = 0; +} + +static void gma_func1_init(struct device *dev) +{ + u32 reg32; + u8 val; + + /* IGD needs to be Bus Master, also enable IO accesss */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + + if (get_option(&val, "tft_brightness") == CB_SUCCESS) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); +} + +static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations gma_pci_ops = { + .set_subsystem = gma_set_subsystem, +}; + +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .disable = gma_func0_disable, + .ops_pci = &gma_pci_ops, +}; + + +static struct device_operations gma_func1_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func1_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, +}; + +static const struct pci_driver i945_gma_func0_driver __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27a2, +}; + +static const struct pci_driver i945_gma_func1_driver __pci_driver = { + .ops = &gma_func1_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27a6, +}; diff --git a/docs/future/dumps/5885_logs.tar.gz b/docs/future/dumps/5885_logs.tar.gz Binary files differnew file mode 100644 index 0000000..599445e --- /dev/null +++ b/docs/future/dumps/5885_logs.tar.gz diff --git a/docs/future/dumps/5885_logs_2.tar.gz b/docs/future/dumps/5885_logs_2.tar.gz Binary files differnew file mode 100644 index 0000000..a3381b4 --- /dev/null +++ b/docs/future/dumps/5885_logs_2.tar.gz diff --git a/docs/future/dumps/5927_2.tar.gz b/docs/future/dumps/5927_2.tar.gz Binary files differnew file mode 100644 index 0000000..39a794b --- /dev/null +++ b/docs/future/dumps/5927_2.tar.gz diff --git a/docs/future/dumps/5927_3.tar.gz b/docs/future/dumps/5927_3.tar.gz Binary files differnew file mode 100644 index 0000000..484acc6 --- /dev/null +++ b/docs/future/dumps/5927_3.tar.gz diff --git a/docs/future/dumps/5927_5.tar.gz b/docs/future/dumps/5927_5.tar.gz Binary files differnew file mode 100644 index 0000000..31ba59f --- /dev/null +++ b/docs/future/dumps/5927_5.tar.gz diff --git a/docs/future/dumps/5927_6.tar.gz b/docs/future/dumps/5927_6.tar.gz Binary files differnew file mode 100644 index 0000000..09810f0 --- /dev/null +++ b/docs/future/dumps/5927_6.tar.gz diff --git a/docs/future/dumps/5927_7.tar.gz b/docs/future/dumps/5927_7.tar.gz Binary files differnew file mode 100644 index 0000000..8543547 --- /dev/null +++ b/docs/future/dumps/5927_7.tar.gz diff --git a/docs/future/dumps/5927_cbmemc b/docs/future/dumps/5927_cbmemc new file mode 100644 index 0000000..1ef5139 --- /dev/null +++ b/docs/future/dumps/5927_cbmemc @@ -0,0 +1,1442 @@ + + +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (417848 bytes), entry @ 0x100000 +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2975 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529332 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353806 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124473 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5804 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00160000, stack_end 00160ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11641 loops) +CPU1: stack: 00160000 - 00161000, lowest used address 00160c68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687708 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +Initializing VGA without OPROM. +GMADR=0xd0000008 GTTADR=0xe4400000 +i915lightup: graphics d0020000 mmio e4300000 addrport 50a0 physbase bf800000 +Extracted contents: +header: 00 ff ff ff ff ff ff 00 +serial number: 30 ae 00 40 00 00 00 00 00 0f +version: 01 03 +basic params: 80 19 12 78 ea +chroma info: ed 75 91 57 4f 8b 26 21 50 54 +established: 21 08 00 +standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 +descriptor 1: 28 15 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 2: ed 10 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 3: 00 00 00 0f 00 61 43 32 61 43 28 0f 01 00 4c a3 58 4a +descriptor 4: 00 00 00 fe 00 4c 54 4e 31 32 31 58 4a 2d 4c 30 37 0a +extensions: 00 +checksum: 00 + +Manufacturer: LEN Model 4000 Serial Number 0 +EDID version: 1.3 +Digital display +Maximum image size: 25 cm x 18 cm +Gamma: 220% +Check DPMS levels +DPMS levels: Standby Suspend Off +Supported color formats: RGB 4:4:4, YCrCb 4:2:2 +First detailed timing is preferred timing +Established timings supported: + 640x480@60Hz + 800x600@60Hz + 1024x768@60Hz +Standard timings supported: +Detailed timings +Hex of detail: 281500404100263018883600f6b900000018 +Did detailed timing +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: ed1000404100263018883600f6b900000018 +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: 0000000f006143326143280f01004ca3584a +Manufacturer-specified data, tag 15 +Hex of detail: 000000fe004c544e313231584a2d4c30370a +ASCII string: LTN121XJ +Checksum +Checksum: 0x0 (valid) + +Unknown extension block + +EDID block does NOT conform to EDID 1.3! + Missing name descriptor + Missing monitor ranges + Detailed block string not properly terminated +EDID block does not conform at all! + Bad year of manufacture + Detailed blocks filled with garbage +I915_WRITE(HTOTAL(pipe), 053f03ff) +I915_WRITE(HBLANK(pipe),0x053f03ff) +I915_WRITE(HSYNC(pipe),0x049f0417) +I915_WRITE(VTOTAL(pipe), 032502ff) +I915_WRITE(VBLANK(pipe),0x032502ff) +I915_WRITE(VSYNC(pipe),0x03080302) +Table has 2247 elements +Change verbosity to 0 +run: return 2246 +Run returns 2247 +gtt_setup: GTT PGETLB_CTL register: 0x0 +gtt_setup: GTT PGETLB_CTL register: 0x1 +gtt_setup: GTT PGETLB_CTL register: 0xbf800001 +gtt_setup: GTT PGETLB_CTL register: 0xbf800003 +gtt_setup is enabled: GTT PGETLB_CTL register: 0x1 +setgtt(0,1600,0xbf800000,4096); +GTT PGETLB_CTL register: 0xbf800001 +GTT Enabled +memset d0020000 to 0x00 for 3145728 bytes +229929 microseconds +PCI: 00:02.0 init 265041 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2382 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4490 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4489 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4925 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4926 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1683 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50455 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4942 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7210 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1669 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1668 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7377 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1670 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1670 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1670 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1582 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1584 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1584 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16205 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3593 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1411225 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp tabl +6653 bytes lost diff --git a/docs/future/dumps/5927_config b/docs/future/dumps/5927_config new file mode 100644 index 0000000..045ca30 --- /dev/null +++ b/docs/future/dumps/5927_config @@ -0,0 +1,441 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="7BETC7WW (2.08 )" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_STACK_SIZE=0x1000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="ThinkPad X60" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="L3AZ921" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="1703WMF" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set + +# +# VGA BIOS +# + +# +# Display +# + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_POST_IO is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_VGA is not set +# CONFIG_GFXUMA is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +CONFIG_MAX_REBOOT_CNT=3 diff --git a/docs/future/dumps/5927_crashdump b/docs/future/dumps/5927_crashdump new file mode 100644 index 0000000..3e09cd5 --- /dev/null +++ b/docs/future/dumps/5927_crashdump @@ -0,0 +1,77 @@ +Time: 1401830541 s 274954 us +Kernel: 3.14.4-gnuowen +PCI ID: 0x27a2 +EIR: 0x00000010 +IER: 0x00028053 +PGTBL_ER: 0x00000013 +FORCEWAKE: 0x00000000 +DERRMR: 0x00000000 +CCID: 0x00000000 +Missed interrupts: 0x00000000 + fence[0] = 00000000 + fence[1] = 00000000 + fence[2] = 00000000 + fence[3] = 00000000 + fence[4] = 00000000 + fence[5] = 00000000 + fence[6] = 00000000 + fence[7] = 00000000 + fence[8] = 00000000 + fence[9] = 00000000 + fence[10] = 00000000 + fence[11] = 00000000 + fence[12] = 00000000 + fence[13] = 00000000 + fence[14] = 00000000 + fence[15] = 00000000 + INSTDONE_0: 0x7fffffc0 + INSTDONE_1: 0x00000000 + INSTDONE_2: 0x00000000 + INSTDONE_3: 0x00000000 +Active [0]: +Pinned [0]: +Num Pipes: 2 +Pipe [0]: + Power: off + SRC: 00000000 +Plane [0]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [0]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +Pipe [1]: + Power: off + SRC: 00000000 +Plane [1]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [1]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 diff --git a/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc b/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc new file mode 100644 index 0000000..c769d1a --- /dev/null +++ b/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc @@ -0,0 +1,1436 @@ + + +coreboot-4.0-6195-g3b7c130-7BETC7WW (2.08 ) Tue Jun 3 16:36:44 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (327736 bytes), entry @ 0x100000 +coreboot-4.0-6195-g3b7c130-7BETC7WW (2.08 ) Tue Jun 3 16:36:44 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2976 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3323 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529959 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353777 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124466 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5771 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 0014a000, stack_end 0014aff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11642 loops) +CPU1: stack: 0014a000 - 0014b000, lowest used address 0014ac68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687602 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +In CBFS, ROM address for PCI: 00:02.0 = ffe007b8 +PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 +PCI ROM image, vendor ID 8086, device ID 27a2, +PCI ROM image, Class Code 030000, Code Type 00 +Copying VGA ROM Image from ffe007b8 to 0xc0000, 0x10000 bytes +Real mode stub @00000600: 867 bytes +Calling Option ROM... +int15_handler: AX=5f40 BX=d103 CX=0055 DX=0002 +DISPLAY=3 +int15_handler: AX=5f34 BX=078f CX=0002 DX=0002 +Unknown INT15 function 5f34! +int15 call returned error. +int15_handler: AX=5f35 BX=078f CX=0002 DX=00c0 +... Option ROM returned. +VGA Option ROM was run +gma_func0_init: After VBIOS/native init: GMADR=0xd0000008 GTTADR=0xe4400000 +PCI: 00:02.0 init 175395 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2383 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4491 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4491 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4923 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4924 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1681 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50464 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4941 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7211 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1668 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1670 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7378 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1669 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1671 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1671 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1584 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1583 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1583 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16211 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3591 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3592 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1321463 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp table end at: bf6e1810 - bf6e19cc +MP table: 460 bytes. +Adding CBMEM entry as no. 7 +ACPI: Writing ACPI tables at bf6e2800. +ACPI: * HPET +ACPI: added table 1/32, length now 40 +ACPI: * MADT +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * FACS +ACPI: Patching up global NVS in DSDT at offset 0x0263 -> 0xbf6e5c10 +ACPI: * DSDT @ bf6e2b40 Length 30ca +ACPI: * FADT +ACPI: added table 4/32, length now 52 +ACPI: * SSDT +Found 1 CPU(s) with 2 core(s) each. +clocks between 1000 and 1666 MHz. +adding 3 P-States between busratio 6 and a, incl. P0 +PSS: 1666MHz power 31000 control 0xa1e status 0xa1e +PSS: 1333MHz power 22050 control 0x818 status 0x818 +PSS: 1000MHz power 13100 control 0x613 status 0x613 +clocks between 1000 and 1666 MHz. +adding 3 P-States between busratio 6 and a, incl. P0 +PSS: 1666MHz power 31000 control 0xa1e status 0xa1e +PSS: 1333MHz power 22050 control 0x818 status 0x818 +PSS: 1000MHz power 13100 control 0x613 status 0x613 +ACPI: added table 5/32, length now 56 +current = bf6e6110 +ACPI: done. +Laptop handling... +ACPI tables: 14608 bytes. +Adding CBMEM entry as no. 8 +smbios_write_tables: bf6edc00 +Root Device (Lenovo ThinkPad X60 / X60s) +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +CPU_CLUSTER: 0 (Intel i945 Northbridge) +APIC: 00 (Socket mFCPGA478 CPU) +DOMAIN: 0000 (Intel i945 Northbridge) +PCI: 00:00.0 (Intel i945 Northbridge) +PCI: 00:02.0 (Intel i945 Northbridge) +PCI: 00:02.1 (Intel i945 Northbridge) +PCI: 00:1b.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1c.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1c.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.2 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.3 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.7 (Intel ICH7/I +4509 bytes lost diff --git a/docs/future/dumps/coreboot_5926_oprom_grub_config b/docs/future/dumps/coreboot_5926_oprom_grub_config new file mode 100644 index 0000000..dedf3ae --- /dev/null +++ b/docs/future/dumps/coreboot_5926_oprom_grub_config @@ -0,0 +1,449 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="7BETC7WW (2.08 )" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_VGA_BIOS=y +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_VGA_BIOS_FILE="vgabios.bin" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_STACK_SIZE=0x1000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="ThinkPad X60" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="L3AZ921" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="1703WMF" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_S3_VGA_ROM_RUN=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +# CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_RUN=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y +# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set + +# +# VGA BIOS +# + +# +# Display +# +# CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_POST_IO is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_VGA is not set +# CONFIG_GFXUMA is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_REALMODE_DEBUG is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +CONFIG_MAX_REBOOT_CNT=3 diff --git a/docs/future/dumps/grub.cfg b/docs/future/dumps/grub.cfg new file mode 100644 index 0000000..ddc5606 --- /dev/null +++ b/docs/future/dumps/grub.cfg @@ -0,0 +1,38 @@ +set default="0" +set timeout=1 +set pager=1 + +menuentry 'Trisquel GNU/Linux with linux-libre 3.14.4' { + linux (ahci0,1)/boot/vmlinuz-3.14.4-gnuowen root=/dev/sda1 processor.max_cstate=2 drm.debug=0x06 console=tty0 console=ttyS0,115200n8 + initrd (ahci0,1)/boot/initrd.img-3.14.4-gnuowen +} +menuentry 'Parse ISOLINUX menu (USB)' { + set root='usb0' + syslinux_configfile -i (usb0)/isolinux/isolinux.cfg +} +menuentry 'Parse ISOLINUX menu (CD)' { + set root='ata0' + syslinux_configfile -i (ata0)/isolinux/isolinux.cfg +} +menuentry 'Scan for GRUB configurations on the internal HDD (Permits to load other OS or distributions)' { + insmod regexp + insmod ahci + insmod part_msdos + for x in (ahci0,*) ; do + if [ -f "$x/grub/grub.cfg" ] ; then + submenu "Load Config from $x" $x { + root=$2 + source /grub/grub.cfg + unset superusers + } + fi + if [ -f "$x/boot/grub/grub.cfg" ] ; then + submenu "Load Config from $x" $x { + root=$2 + source /boot/grub/grub.cfg + unset superusers + } + fi + done +} + diff --git a/docs/future/dumps/grub_memdisk_serial.cfg b/docs/future/dumps/grub_memdisk_serial.cfg new file mode 100644 index 0000000..9200910 --- /dev/null +++ b/docs/future/dumps/grub_memdisk_serial.cfg @@ -0,0 +1,10 @@ +#Serial and keyboard configuration, very important. +serial --speed=115200 --unit=0 --word=8 --parity=no --stop=1 +terminal_input --append serial +terminal_output --append serial +terminal_input --append at_keyboard #add keyboard support. + +set prefix=(memdisk)/boot/grub + +set root='cbfsdisk' +source (cbfsdisk)/grub.cfg diff --git a/docs/future/dumps/index.html b/docs/future/dumps/index.html new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/docs/future/dumps/index.html diff --git a/docs/future/dumps/kernel312_irc b/docs/future/dumps/kernel312_irc new file mode 100644 index 0000000..c04a00c --- /dev/null +++ b/docs/future/dumps/kernel312_irc @@ -0,0 +1,1590 @@ +<hr/> + + <h1 id="todo_cb5926_paulmenzel">Coreboot 5926 test for Paul Menzel</h1> + <p> + Coreboot log when running Video BIOS (grub payload) and <a href="http://review.coreboot.org/5926">http://review.coreboot.org/5926</a>. + </p> + <p> + Result (ThinkPad X60): <a href="dumps/coreboot_5296_oprom_grub_cbmemc">cbmem -c output</a><br/> + Config used on the X60 (grub payload and vbios): <a href="dumps/coreboot_5926_oprom_grub_config">.config</a> + </p> + + + + + + + + + + + + <h1 id="todo_cb5893_paulmenzel">Coreboot 5893 test for Paul Menzel</h1> + <p> + <a href="dumps/x60_5893_vbios.tar.gz">With VBIOS</a><br/> + <a href="dumps/x60_5893_native.tar.gz">With native graphics</a> (replay code). + </p> + <p> + Here is a crash dump from running native graphics (): <a href="dumps/x60_5893_native_crashdump">/sys/class/drm/card0/error</a>. + </p> + +<hr/> + +<h1 id="i945_stolenmem_fix">early attempt: i945 stolen memory fix (for kernel 3.12/later) (this attempt failed)</h1> +<p> +Back then we had no idea that GTT address was incorrect, and we had no idea what was causing the issue. + +<pre> +Note: see <a href="#i945_312fix">this fix</a> for the initial fix that was found. + +<b><font color="red">not working yet</font></b> +<a href="http://review.coreboot.org/#/c/5885/" target="_blank">http://review.coreboot.org/#/c/5885/</a> + +untested. will test this. +checkout 5320. cherry pick 5345 on top. +mannually apply changes from 5884/1 and 5885/3 +make backlight changes as in #x60_native_notes and #t60_native_notes +test this on X60 and T60. + +If it works, manually apply 5885 to 5320 alone and then push with 5320 as dependency. +Rebase that new change ID, and rebase 5345 (pushing it as new change ID). +Manually merge the rebased 5345 into the new patch, and then push that. + +Boot with grub (obviosly!) and kernel 3.14.4 as before (with 17fec8a left untouched!). + +Note: tidy these notes! (so others can follow) + +get those logs: +Make a copy of these files: + * /var/log/dmesg + * /var/log/kern.log + * /var/log/Xorg.0.log + * /var/log/Xorg.0.log.old (If you have to restart gdm) + * /proc/ioports + * /proc/iomem +Record these outputs: + * sudo intel_reg_dumper + * uname -r + * lspci -vvnn +Do this first: <b>$ sudo modprobe msr</b> (then do as below): + * sudo inteltool -a --> in coreboot/src/util/inteltool +Make a copy of: + * coreboot serial output log. + --> Get it from serial port, or get it like that: + --> <b>./cbmem -c</b> (under coreboot/util/cbmem) +Output from source tree: +$ git log -p | head -150 (localhost/x60gitlog) +$ git diff (localhost/x60gitdiff) +Make a copy of the .config from coreboot source tree + ^ (localhost/x60config) +3D acceleration test (test if 3.12+/stolenmem issue is fixed): + - Run openarena (1024x768 res), say if it works. (note: Press tilde, do <b>/cg_drawfps 1</b>) + - Run tuxcart (1024x768 res), say if it works. + - Run neverball (1024x768 res), say if it works. + - Run glxgears, report what you see. + +Some results on the X60 (3D still doesn't work, openarena and tuxkart were slow): +<a href="dumps/5885_logs.tar.gz">5885_logs.tar.gz</a> +git diff: http://paste.debian.net/102618/ + +In src/northbridge/intel/i945/raminit.c +PaulePanter: fchmmr: In your next step could you please add +PaulePanter: printk(BIOS_DEBUG, "BSM = 0x%08x\n", pci_read_config32(PCI_DEV(0,2,0), BSM)); +PaulePanter: before +PaulePanter: pci_write_config32(PCI_DEV(0,2,0), BSM, (tolud * MiB - 64 * MiB) & 0xfff00000); +done +Also removing the #if statement around those 2 lines above. +Also adding it after that line aswell, per advice from PaulePanter + +Some new results on the X60 after doing the above (3D still doesn't work, openarena and tuxkart were slow): +<a href="dumps/5885_logs_2.tar.gz">5885_logs_2.tar.gz</a> + +PaulePanter: fchmmr: No idea if you can write with `devmem2`. Never used it. +PaulePanter: fchmmr: It would indeed be interesting to know what value the BSM has with the vendor BIOS. +Note to self: do that. + +PaulePanter said: I have `& 0xfff00000` and phcoder uses `& 0xfffff000`, so it looks like I have the ordering incorrect. + + +Look at that discussion: +http://lists.freedesktop.org/archives/intel-gfx/2014-May/046309.html +http://lists.freedesktop.org/archives/intel-gfx/2014-May/046310.html +--> if BSM register is read-only, then is there something els ethat we might have missed? + +</pre> +</p> + + + + + + + + + + + <h2><a name="kernel312bugs">kernel 3.12+ bugs (X60/T60 native init)</a><a href="#pagetop">Back to top of page</a></h2> + <p> + Some further notes to refer to later (WARNING: long! These are collected IRC logs for later reference. Most of the + logs are not useful or relevant, and will be deleted later): + +<pre> +Note: see <a href="#i945_312fix">this fix</a> for the initial fix that was found. + +see: <a href="http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels" target="_blank">http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels</a> +see: <a href="http://www.coreboot.org/Lenovo_x60x_vgainit_todos" target="_blank">http://www.coreboot.org/Lenovo_x60x_vgainit_todos</a> + +Non-coreboot (not even i945) platforms also have issues with 3.12+ +see: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=76520" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=76520</a> + +Is this relevant?: <a href="http://lists.freedesktop.org/archives/intel-gfx/2014-February/040771.html" target="_blank">http://lists.freedesktop.org/archives/intel-gfx/2014-February/040771.html</a> + + + +note: read below. +and note: on later kernels they also can't seem to init the GPU properly without vbios or native gfx, whereas older kernels could. + +PaulePanter: damo22: There is also a Linux and coreboot native graphics incompatibility documented in the Wiki (by samnob). +PaulePanter: http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels +fchmmr: PaulePanter, that only exists with kernel 3.12 and above. +PaulePanter: fchmmr: Do you have time to report it to the Freedesktop Bugzilla? +funfunctor: patrickg: I think its related to recent changes we had done to toolchain.in +fchmmr: Yes. What info do you need ? +PaulePanter: fchmmr: It’s a regressions and these are normally not allowed with Linux’ no regression policy. +fchmmr: What do you think would happen then, after I made that report? +PaulePanter: fchmmr: https://01.org/linuxgraphics/documentation/how-report-bugs +fchmmr: You can look at it 2 ways: kernel broke, or kernel fixed a bug which broke coreboot. +PaulePanter: fchmmr: Hopefully they’ll fix it. +fchmmr: so: either coreboot is broken, or kernel is broken. +fchmmr: PaulePanter, kernel 3.12+ should work just fine on lenovo bios, so my opinion is that the native gfx in coreboot is what's buggy. +PaulePanter: fchmmr: You can also check with the developers in #intel-gfx. But first report the bug so you can reference it. +fchmmr: Do you think I should just copy what's in the coreboot wiki already? +PaulePanter: fchmmr: Does not matter. If it worked before 3.12, it should work afterward. +fchmmr: It seems pretty complete (as far as reporting it is concerned). +fchmmr: PaulePanter, my basic point is that I'm on the fence as to whether this is linux's problem, coreboot's problem, or both. +PaulePanter: fchmmr: That would probably help. If they need other information, the Intel folks will ask you for it. Daniel Vetter and the other Intel folks are very responsive in my experience. +fchmmr: So you think then that there would be a patch specifically for i915 + coreboot_native_init +PaulePanter: fchmmr: I do not know. They hopefully figure it out. +fchmmr: PaulePanter, I will do it. +PaulePanter: fchmmr: And as I wrote, it is a regression. As far as I understood it, even if the firmware/hardware is broken, Linux should not introduce regressions. +fchmmr: PaulePanter: at the very least, it might offer a new perspective. this whole issue has been very one-sided so far: it has only been coreboot community that talks about it. It has probably gone unobserved in kernel/intel community. +fchmmr: The intel/kernel people might even be able to (easily) spot a fix for coreboot. +fchmmr: I hadn't even considered this possibility before, I thought it was only a coreboot problem. Talking to those other people definitely makes sense. + +PaulePanter of #coreboot made the initial report to Freedesktop tracker: + +PaulePanter: fchmmr: Hi. Did you report the Linux regression to the Freedesktop bug tracker? +PaulePanter: fchmmr: Understood. Do you have an account for the Freedesktop bug tracker? +fchmmr: PaulePanter: I do not have an account for Freedesktop bug tracker, but I think I could get one? +PaulePanter: fchmmr: Yes, it is easy to register. +fchmmr: PaulePanter, there's reporting and there's reporting properly; I want to compile my report first, before I make it. +PaulePanter: fchmmr: As you do not know what they need, I think it is the wrong approach. +fchmmr: Since the people that I am reporting to will be unfamiliar with the issue, and might not even know about coreboot, or only vaguely know. +PaulePanter: fchmmr: I’ll report the issue and give you the URL. You can then add to it. +fchmmr: PaulePanter: Good point. I can make it brief describing it as best I can, and then I can answer any specific questions. +fchmmr: PaulePanter, you can use my notes at http://libreboot.org/howto.html#kernel312bugs if you like, it's a collection of insights plus links to those pages on the coreboot wiki that talk about the issue. +fchmmr: (in case there is anything in the notes that might be helpful) +fchmmr: PaulePanter, are the intel i915 devs of freedesktop also the ones working on the i915 code in kernel.org? (I'm slightly confused about this) + +THE REPORT: + +PaulePanter: fchmmr: The Wiki talks about crashes. +PaulePanter: fchmmr: https://bugs.freedesktop.org/show_bug.cgi?id=79038 + +PaulePanter: fchmmr: The Wiki talks about crashes. +PaulePanter: fchmmr: https://bugs.freedesktop.org/show_bug.cgi?id=79038 +fchmmr: PaulePanter, thanks. I'll add to it and help any way I can. +PaulePanter: fchmmr: Add `drm.debug=0x06` to the Linux command line (probably configuring in GRUB) and please add `/var/log/dmesg` to the bug report. (Or the output of `dmesg`.) +PaulePanter: fchmmr: They also need `/var/log/Xorg.0.log` and your distribution and exact Linux kernel version `uname -r`. +fchmmr: PaulePanter: there are basically 2 versions of native init: 3998 (based on replay, only works on X60 with XGA screen - also what libreboot currently uses) and 5320 (much better, works on more screens, 5345 can use it to enable T60 - not yet in libreboot) +fchmmr: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345) + +fchmmr: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345) +fchmmr: PaulePanter: nonetheless, I will do both, and make that report for you now. +fchmmr: Do I do this on pre-3.12 kernel or 3.12+ ? +PaulePanter: fchmmr: I’d say Linux 3.12+. +PaulePanter: fchmmr: Do you know which coreboot patches samnob used? + +fchmmr: PaulePanter: very well. http://jxself.org/linux-libre has latest kernels +fchmmr: I will install that. +fchmmr: I do not know what coreboot patches samnob used. Probably 3998 (this was a long time ago). +fchmmr: Definitely change ID 3998 (review.coreboot.org gerrit): http://review.coreboot.org/#/c/3998/ + + +fchmmr: PaulePanter: here is the information that you requested: http://libreboot.org/logs/3998_Xorg.0.log http://libreboot.org/logs/3998_dmesg http://libreboot.org/logs/3998_uname +fchmmr: PaulePanter: that bug in the report doesn't happen with the above -- it's an older kernel. +fchmmr: Do they want me to try 3.12+ instead? +fchmmr: PaulePanter: you should also give them these links to the lastest code for native graphics: +fchmmr: http://review.coreboot.org/#/c/5320/ + +PaulePanter: fchmmr: Thank you for getting the logs. Please register and upload the files yourself. +fchmmr: Yes, ok. I will also get the same logs again for a kernel that is broken (3.12+) +fchmmr: I will repeat both processes again for coreboot+5320+5345, as currently I am getting these on libreboot. +fchmmr: More logs can't hurt, the worst that can happen is they will ignore the ones they don't need. I want to make sure they have everything they need. + +samnob: fchmmr: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_1_i386.deb and http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_1_i386.deb latest linux-libre without and with 17fec8a reverted. +PaulePanter: fchmmr: Thanks. + +fchmmr: samnob, thanks. +fchmmr: but we are trying to get kernel 3.12+ to work without users having to patch it +fchmmr: either by fixing coreboot, or patching around coreboot in the kernel +fchmmr: eventually both +samnob: Yes, just providing you kernels for the bug. +fchmmr: ah right. +fchmmr: with and without. that is useful. i was going to use jxself kernels. that is useful. +fchmmr: I'll use yours then ;) +fchmmr: dpkg -i ? + +samnob: Though based on the devs comment in the bug I think you're hope of the driver working around it is unlikely. +fchmmr: can't hurt to try +samnob: dpkg -i will work fine. +samnob: (though gdebi is more fun.) +samnob: there's a version symlink_hook in that same folder that is handy for grub2 payload users too. +fchmmr: samnob we think it might be classed under linux "no regression" policy +fchmmr: PaulePanter's idea +samnob: can't hurt to try :) + +Here is the debugging results then: <a href="coreboot_native_3.12_bug.tar.gz" target="_blank">coreboot_native_3.12_bug.tar.gz</a> + +--- + +http://undeadly.org/cgi?action=article&sid=20131120060004 was suggested +(also refer back te the datasheet) + +---- + +I have since been alerted to this bug report, which is unrelated to us +but shows that 3.12 also breaks later systems on Lenovo BIOS (as far as I can tell): + +https://bugzilla.kernel.org/show_bug.cgi?id=71391 + +-- + +PaulePanter: fchmmr: If you run the Lenovo X60 right now, could you just paste it now. It should not change between all your tests. +PaulePanter: fchmmr: It would really be helpful to have it now. +fchmmr: My workstation X60 is running coreboot+5320 (and modification for backlight control support) +fchmmr: Shall I take iomem output from that? +fchmmr: kernel 3.2 is in use +PaulePanter: fchmmr: Yes. Please. +fchmmr: For you record: +fchmmr: $ uname -r +fchmmr: 3.2.0-56-generic-pae +fchmmr: distro: trisquel 6 +fchmmr: PaulePanter: http://paste.debian.net/101404/ + +PaulePanter linked to this: +http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf +--------------- + +PaulePanter: patrickg: As the resident i945 export, do you know where the register GBSM (Graphics Base of Stolen Memory) should be set? +PaulePanter: patrickg: Is the VGA Option ROM responsible for that? +PaulePanter: damo22: You do not see any problems with the VGA Option ROM, right? +damo22: PaulePanter: i am running vga rom with updated kernel (after the patch) and experience no problems with video +PaulePanter: damo22: Thank you for the confirmation. +PaulePanter: src/northbridge/intel/i945/northbridge.c: printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", +patrickg: PaulePanter: what's that, 0x5c? +patrickg: h, no +PaulePanter: + /* Almost universally we can find the Graphics Base of Stolen Memory +PaulePanter: + * at offset 0x5c in the igfx configuration space. On a few (desktop)patrickg: PaulePanter: I think we never configured that but left it to vgabios +patrickg: PaulePanter: we only configured the RAM side +PaulePanter: patrickg: Thanks. So with native VGA init, coreboot needs to do that too. +<b><font color="red">damo22: we just need to write the gfxstolen base to gma config space at 0x5c</font></b> +damo22: that should fix it +damo22: because then the kernel will try to read that +damo22: hmm but if the generation of the gma is not >=3 it will assume it is above top of memory +patrickg: well, it is +damo22: patrickg: do you happen to know if the x60 gma is generation 2 or 3? how do i find out +PaulePanter: damo22: lspci ? +damo22: (rev 0x)? +PaulePanter: lspci -nn +damo22: never mind i will ctags the kernel tree +patrickg: but bbl +patrickg: damo22: code.metager.de applies openGrok on tons of open source projects. probably to linux, too +damo22: thanks patrickg +damo22: okay, i945g/gm is generation 3 +damo22: its nothing to do with the lscpi revision +PaulePanter: damo22: How did you check that? +PaulePanter: … it is 3rd gen? +damo22: PaulePanter: its in the i915_drv.c in the kernel +damo22: eg, i965g/gm is generation 4 +PaulePanter: Ok. +damo22: its also NOT valleyview +* pl4nkton is now known as pl4nkton`away +PaulePanter: damo22: ? +PaulePanter: Who said that? +damo22: im trying to figure out which path the kernel takes before and after the patch +damo22: it must be different +PaulePanter: damo22: https://bugs.freedesktop.org/show_bug.cgi?id=79038#c12 +PaulePanter: damo22: Before they calculate it manually and afterward they read out that register, which the firmware should program, right? +PaulePanter: src/northbridge/intel/i945/i945.h:#define TOLUD 0x9c /* Top of Low Used Memory */ +PaulePanter: Off topic, how do I make Vim and Ctags jump to the correct header definition. If I Ctrl + click on `TOLUD` in `src/northbridge/intel/i945/raminit.c` it jumps into the header of `intel/fsp_sandybridge/northbridge.h` instead of `src/northbridge/intel/i945/i945.h`. +PaulePanter: ? +damo22: i have the same problem, there is a way to configure it to pop up a list of matches so you can select the right one but i dont know how +PaulePanter: damo22: Ok. Good to know I am not the only one. +<b><font color="red"> +damo22: okay, so for gen 3 i915, (i945/m) we can do what i said above and it should work +PaulePanter: Is “graphics datastolen memory size (PCI Device 0 offset 52 bits 7:4)” configurable and programmed by the firmware or is it fixed if the IGP is enabled and can just be read? +PaulePanter: damo22: Yes. +damo22: its just a matter of setting the base address in the register +damo22: i think the only difference is that in the kernel it is assumed that it is aligned to 0x100000 +damo22: kernel does this: base &= ~((1<<20) - 1); +damo22: but coreboot does this: pci_read_config32(dev, 0x5c) & ~0xf, +damo22: possibly a one liner +damo22: change ~0xf to ~0xfffff lol +samnob: fchmmr: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_2_i386.deb and linux-image-3.14.4-gnuowen_2_i386.deb with CONFIG_STRICT_DEVMEM unset. No PAE as always. +samnob: damo22: thanks for looking into this. +</font></b> +fchmmr: damo22: you are the most awesome person ever. I'm stilll preparing my dev/debugging environment and you speculate this already. I will try it soon. +fchmmr: samnob: thank you for confirming. +fchmmr: samnob: ok, /dev/mem support and non-PAE. excellent! +samnob: fchmmr: don't overlook that revision 2 those, are new debs with STRICT_DEVMEM unset +damo22: fchmmr: its much quicker to read and compare code than to compile kernels and flash firmware +PaulePanter: fchmmr: I think your testing is not needed until you get a patch. +PaulePanter: damo22: TOLUD (PCI Device 0 offset BCh bits 31:20) +fchmmr: PaulePanter ? +fchmmr: Yes I understand that. I was about to debug, but now we will test damo22's advice first. +damo22: PaulePanter: i think intel_gma_init is being called with unaligned physical address for graphics mem + +PaulePanter: fchmmr: BDSM—Base Data of Stolen Memory Register +PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf + +PaulePanter: fchmmr: The methods you try just read it out and never set it. +PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20). +damo22: PaulePanter: im pretty sure BDSM is only present in core iX cpus +fchmmr: PaulePanter, yes my method was to go about to be sure where it is set, and then try to set it properly in 5320. +PaulePanter: fchmmr: The problem is already present with native graphics in coreboot master, isn’t it? +fchmmr: damo22 took a shorter method to get the same result (hopefully. like you, i wait for him to confirm or deny success) +fchmmr: PaulePanter, yes the 3.12+ glitches exist in 5320 changeset aswell as 3998 (the old replay version, which 5320 is a re-write of) +PaulePanter: fchmmr: Sorry, I claim your tests would have never gotten any solution for the problem. +* martinr (~martin@8.36.227.227) has joined #coreboot +fchmmr: PaulePanter, that is quite possible, but it was a test anyway. +PaulePanter: damo22: Chris Wilson and the Linux commit say that the BDSM is present, don’t they? +PaulePanter: + if (INTEL_INFO(dev)->gen >= 3) { +PaulePanter: + /* Read Graphics Base of Stolen Memory directly */ +fchmmr: I actually did find where the stolen memory address was set, in /var/log/kern.log after using drm.debug=0x06 in those previous results i uploaded to freedesktop.org, but that was on coreboot/5320 with the address set incorrectly. +fchmmr: just search for the word "stolen" in the log and you'll find it on one of the lines. + +PaulePanter: fchmmr: It’s not *set* it is *read* in there. +fchmmr: Oh right. +fchmmr: But I thought when reading it, it has to know the address. So the address I saw must have been what was set? +fchmmr: What am I missing? +damo22: okay so there is something to clarify, i915 driver is the same for all intel gpus even some that are physically located in cpu + +PaulePanter: fchmmr: As it is not explicitely set beforehand it contains some incorrect value, which is then read. +PaulePanter: fchmmr: That is the whole problem. +fchmmr: I see. +fchmmr: So, +fchmmr: my tests would have been useless, then. + +<b><font color="red">damo22: it didnt work</font></b> +(note: can still try to make other changes: see testing notes below) + +damo22: oh wait, X just didnt detect the LVDS +damo22: in fact nothing did +damo22: but there were no errors +damo22: ok so when i plug external monitor X freezes and gives errors +damo22: and internal display isnt active +damo22: wierd, when i rebooted i got vga fine +damo22: i think linux kernel i915 is trying to do something with vgarom because it says "invalid rom contents" as first boot line +damo22: no i need to find out if the kernel is doing something bad without rom present +damo22: and then figure out how to enable lvds, because vga is working +fchmmr: drivers/pci/rom.c: dev_err(&pdev->dev, "Invalid ROM contents\n"); +fchmmr: in that: size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) +fchmmr: /* Standard PCI ROMs start out with these bytes 55 AA */ +fchmmr: if (readb(image) != 0x55) { +fchmmr: dev_err(&pdev->dev, "Invalid ROM contents\n"); +fchmmr: break; +fchmmr: } +damo22: i guess i should focus on the fact that coreboot did not initialise the gfx at grub screen +damo22: i mean seabios +damo22: its difficult because linux does some reinitialisation of gfx +damo22: i thought i had this one in the bag +CareBear\: damo22 : it does complete reinit +damo22: i flicked throught the kernel i915 driver and it looks like it reads VBT tables from romheaders or something +damo22: if we are using native gfx init, those are not present right? +samnob: damo22: I think you need to be using grub2 to test native gfx init, seabios needs at least a stub of a vgarom. +CareBear\: damo22 : correct +CareBear\: samnob damo22 : if you want to use SeaBIOS you can use the SeaVGABIOS which will pick up a native framebuffer initialized by coreboot +damo22: does SeaVGABIOS install VBT stuff in the vgarom area? +CareBear\: damo22 : probably not the kind the framebuffer driver looks for +damo22: then it will fail with linux +CareBear\: damo22 : yes +damo22: CareBear\: can we write a vgabios stub that passes the signature tests and also has native VBT tables, but executes nothing? +damo22: otherwise we need to patch the linux kernel to ignore certain models that have no vgabios +CareBear\: damo22 : let's first find out what information is used in those tables +damo22: i have the code in front of me +damo22: drivers/gpu/drm/i915/intel_bios.c (kernel) +damo22: fchmmr: no, i am trawling through linux driver code +fchmmr: damo22: are you aware that certain kernels can initialize the GPU on X60 without the native gfx or oprom? (you don't see payloads, but kernel/X11 shows display +damo22: i have a feeling the linux kernel currently tries to load the vgarom regardless of PCH existance + +damo22: i think there are two problems with native gfx init, one problem is that the lvds isnt coming up (coreboot issue), the other is is with the linux kernel i915 driver that tries to read the vgarom that isnt there + +fchmmr: damo22, what hardware are you testing your changes on? +fchmmr: Did you try 5320 without your changes? +fchmmr: (hardware: X60 or T60) + +Peter on 5320 talks about vga pipe not being enabled: this means that payload doesn't appear +on vga (only on lvds). OS can output on vga or lvds. so we need to get 5320 to output (during payload) on vga + +damo22: i just slept on it, and i think i know what the problem is + + * LVDS discovery: + * 1) check for EDID on DDC + * 2) check for VBT data + * 3) check to see if LVDS is already on + * if none of the above, no panel + + +1) it cant find the EDID because the i2c is failing to read with NAK +2) there is no VBT data because there is no vga option rom +3) coreboot is still not doing native init properly so the panel is still off + +Therefore linux assumes there is no LVDS. + +damo22: how do i enable cbmem console? i enabled it in menuconfig, do i need cbmem dynamically growing? +damo22: [*] Send console output to a CBMEM buffer\ +damo22: but i got nothing + +Guest-FR: Hi +Guest-FR: would you please check +Guest-FR: src/northbridge/intel/i945/gma.c +Guest-FR: function gma_func0_disable +Guest-FR: pci_write_config16(dev, GCFC, 0xa00) , sound wrong isn't it? + +damo22: Guest-FR: what do you think is wrong about it? +Guest-FR: per the datasheet (intel, so probably it is also wrong!) , the value should be "0x1b" +Guest-FR: page 74 +damo22: Guest-FR: can you link me to the datasheet +Guest-FR: damo22: congig16 is expecting 0x && 4 digits isn't it? +Guest-FR: damo22: e.i.: 0x1234 +damo22: Guest-FR: 0xa00 === 0x0a00 +damo22: same thing +Guest-FR: ok + +Guest-FR: here is the link for tha datasheet http://www.intel.com/Assets/PDF/datasheet/307502.pdf + +damo22: ty +damo22: Guest-FR: i am also working on this gma +damo22: Guest-FR: i am trying to figure out why native gfx init is not working on my X60 tablet + +Guest-FR: per gma.h, GCFC is 0xf0 /* Graphics Clock Frequency & Gating Control */ +damo22: Guest-FR: GCFC is missing from the datasheet +damo22: so how do you know its wrong +Guest-FR: it is my mistake.... I'm expecting to see 4 digits for conf16 +damo22: Guest-FR: ok, i would have expected GCFC to be on page 62 at the bottom but its missing +Guest-FR: probably we should make a dump to see the value we have with an original bios. what you think ? is it possible? +damo22: Guest-FR: however, GGC is mismatching between that datasheet and in coreboot gma +Guest-FR: intel is a fu*** company +damo22: ahh no, i looked up the wrong file +damo22: it matches +damo22: Guest-FR: i am assuming you are using patched gma to test? +Guest-FR: damo22: no, I use the original one +damo22: Guest-FR: http://review.coreboot.org/#/c/5320/ +Guest-FR: I try to port my board to coorboot https://github.com/coreboot-for-945g-m4/945g-m4 +Guest-FR: thx damo22 +damo22: Guest-FR: you need extra config in devicetree.cb with that +Guest-FR: damo22: http://review.coreboot.org/#/c/5762/ +damo22: Guest-FR: i cant view it +Guest-FR: oops, it is draft +Guest-FR: may I add you as a reviewer ? +damo22: Guest-FR: sure +Guest-FR: damo at zamodio? +damo22: correct +Guest-FR: done +Guest-FR: please feel free put comments (and be verbos, I'm not a developper :p ) +Guest-FR: probably my devicetree is not good, +damo22: it still wont load +Guest-FR: damien at zamaudio.com ? +damo22: yes +damo22: ok better +Guest-FR: probably you got an email ? +Guest-FR: for a review +damo22: Guest-FR: i dont see native gfx init +damo22: are you using vgarom? +Guest-FR: I'm using a PCIE card (Radeon X300) +damo22: dont you want to try to initialise the onboard gfx? +Guest-FR: why not, I'll give it a go :) +damo22: you showed me a whole bunch of code, but what is the problem? +Guest-FR: the serial is working, but it hang on "setting up static southbridge register ..." +Guest-FR: and some times, it went to "setting up Root Complex Topology" +damo22: Guest-FR: well, look for that message in the code and find the next message that should be displayed and you know the problem is between the two messaged +Guest-FR: there is some thing unstable +damo22: messages* +Guest-FR: ok +damo22: Guest-FR: if its too hard to find, add some printk's +damo22: i could really use a tip on how to enable cbmem console +damo22: im running blind + +Guest-FR: the msg ih at " src/northbridge/intel/i945/early_init.c " i945_setup_bars function +Guest-FR: so my problem is between "Setting up static southbridge registers..." and "Done" :) + +damo22: cat .config|grep CBMEM ===> http://paste.debian.net/101541/ why do i still not have any cbmem console? "No console found in coreboot table." +content of debian paste: +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_DYNAMIC_CBMEM is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +damo22: No coreboot CBMEM area found! +* Guest-FR (d5f5ab0b@gateway/web/freenode/ip.213.245.171.11) has joined #coreboot +Guest-FR: I'd like to understand: is there any difference betweent: pci_write_config16(LPC_DEV, 0x84, 0x0a01); + pci_write_config16(LPC_DEV, 0x86, 0x00fc); vs pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); +Guest-FR: for exemple: lenovo/x60/romstage.c we have: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); however in the ich7 datasheet page 364 it is a conf32 + +phcoder-screen: damo22: for C segment. boot with oprom, then dd if=/dev/mem bs=64k of=seg_cdef.bin skip=12 count=4 +damo22: ok +damo22: is that the VBT table? +phcoder-screen: part of it is +damo22: phcoder-screen: http://www.zamaudio.com/mbox2/seg_cdef.bin +damo22: it looks correct because it mentions calistoga +damo22: phcoder-screen: as a general solution, would it be possible to write a script that takes a vgarom as input and outputs a vgarom stub that will have no executable code but still have the VBT stuff and signatures to fool the OS that real vgarom is there, and will detect panels etc +damo22: or is there a better way? + +phcoder-screen: damo22: there is a better way: generate it in coreboot. I have a tool to partially parse the roms. Trying it with yours. +damo22: cool + +phcoder-screen: damo22: http://pastebin.com/GsYhSaNB +Content of that paste: +signature: <$VBT CALISTOGA > +version: 1.00 +VBT size: 0xea0 +VBT checksum: 0x0 +BDB version: 1.29 +section type 254, size 0xea + type: 0 + relstage: 64 + chipset: 1 + LVDS + No TV + rsvd3[0]: 0x8 + rsvd3[1]: 0x3 + rsvd3[2]: 0x31 + rsvd3[3]: 0x33 + Signon: 13Intel(r)Calistoga PCI Accelerated SVGA BIOS +Build Number: 1313d.dal PC 14.20 Dev 10/17/2006 0:22:30 +DECOMPILATION OR DISASSEMBLY PROHIBITED + + Copyright: + Code segment: a + DOS Boot mode: 0 + Bandwidth percent: c0 + rsvd4: 0x3 + Bandwidth percent: 8 + rsvd5: 0x4 +section type 1, size 0x5 +General features: + panel_fitting = 0x3 + flexaim = 0x1 + download_ext_vbt = 0x1 + *enable_ssc = 0x1 + *ssc_freq = 0x1 + *display_clock_mode = 0x0 + disable_smooth_vision = 0x0 + *fdi_rx_polarity_inverted = 0x0 + legacy_monitor_detect = 0x1 + *int_crt_support = 0x1 + *int_tv_support = 0x0 +section type 254, size 0x20 +section type 2, size 0xcb + *CRT DDC GMBUS pin: 2 + DPMS ACPI: 0 + Skip boot CRT detect: 0 + DPMS aim: 1 + boot_display: { 0, 0 } + 6 devices + *device type: 1009 (TV) + *dvo_port: 5 + *i2c_pin: 0 + *slave_addr: 0 + *ddc_pin: 0 + *dvo_wiring: 0 + edid_ptr: 0 + *device type: 1022 (flat panel) + *dvo_port: 4 + *i2c_pin: 0 + *slave_addr: 0 + *ddc_pin: 3 + *dvo_wiring: 0 + edid_ptr: 0 + *device type: 0 (Empty) + *device type: 0 (Empty) + *device type: 0 (Empty) + *device type: 0 (Empty) +section type 3, size 0x1 +section type 4, size 0x1c +section type 254, size 0x69 +section type 6, size 0x16d +section type 7, size 0x7 +section type 8, size 0x3d +section type 10, size 0xcb +section type 11, size 0xc7 +section type 12, size 0xf + *LVDS config: 1 + *Dual frequency: 1 +section type 13, size 0x3 +section type 14, size 0x9 +section type 15, size 0x8b +section type 16, size 0x84 +section type 17, size 0x8 +section type 18, size 0xc +section type 19, size 0x20 +section type 20, size 0x9e +section type 22, size 0x15 + *Panel type: 3 +section type 23, size 0x48 +section type 24, size 0x28 +section type 25, size 0x28 +section type 26, size 0x2 +section type 40, size 0x8 +section type 41, size 0x91 +section type 42, size 0x4a0 +section type 43, size 0x61 +section type 44, size 0x15 +damo22: phcoder-screen: does that mean for every supported board, an extra step will be needed to parse the roms so that the port can be done +damo22: *CRT DDC GMBUS pin: 2 +damo22: i think it is trying pin 3 +phcoder-screen: damo22: CRT is VGA +phcoder-screen: ddc_pin is 3 under lvds section +damo22: oh yeah +phcoder-screen: damo22: we already need some info in device tree to init. I think we can reuse it +phcoder-screen: I can upload my parser if you want +damo22: sure, i can parse my T60 and X60t +damo22: and eventually T61 +phcoder-screen: CL 5842 +damo22: thanks + +damo22: phcoder-screen: do you think the EDID is failing to read in linux because the VBT is missing? + +phcoder-screen: damo22: it's a likely explanation. I'd reput first 64k of your dump back to place +damo22: where does it belong in the flash? +damo22: c0000? +phcoder-screen: damo22: nowhere. c0000 is in RAM +damo22: so how do i ensure it gets loaded into ram at c0000 +phcoder-screen: damo22: memcpy +damo22: im convinced it will work if i do that +damo22: thats like loading the vgarom +damo22: but without executing it +phcoder-screen: damo22: yes +damo22: couldnt i just select it in menuconfig, but comment out the code that runs it? +phcoder-screen: yes +phcoder-screen: and keep in mind that oprom is self-modifying +damo22: yes so i need the final dump to load not the original +phcoder-screen: yes + + + +-- + +Side discussion (in #libreboot, not #coreboot as above): + +fchmmr: damo22: what was the problem? +damo22: EDID is not being read in linux +damo22: well it is, but it fails +damo22: probably because the VBT signature is missing from the oprom +fchmmr: oprom? +fchmmr: You mean native init code? +fchmmr: that it doesn't put the proper data in vbt +damo22: there is some special metadata in the oprom that native init doesnt put in +damo22: linux looks for it +damo22: thats how it knows where to read the EDID from +damo22: otherwise it uses a default address that could be wrong +damo22: in some cases it works +damo22: other cases like my X60t it fails +fchmmr: that would explain why "read-edid" utility deosn't work on natisev gfx at the mament +fchmmr: moment +fchmmr: Basstard` ^ + +damo22: fchmmr: phcoder wrote an experimental utility to parse some of the VBT tables from a vgarom +fchmmr: Did he share it with you? +damo22: yes +fchmmr: Did he upload it publicly? +damo22: http://review.coreboot.org/#/c/5842/ +fchmmr: Ok cool. +fchmmr: Do you think I should try it? + +damo22: you could use it to get more info from all your known boards, collect the parsed tables in a folder correctly named with the type of panel and the type of laptop +fchmmr: So as per #coreboot, my understanding is: move to new stolen memory address, find that metadata and how it's calculated and write that (memcpy/write32) in native init, get VBT tables parsed from ROM, replicate that in native gfx (stub code, just the addresses and pointers to the native init code) +fchmmr: Should this be run an a vgabios.bin, or on a system where vga bios is running (parse it in memory) ? +fchmmr: or both? +damo22: we havent got a solution for native init yet, but we do need to collect info from different models +damo22: to see how they compare +fchmmr: yes so, vgabios.bin (file) or running vga bios? +damo22: and also we can add it to devicetree.cb somehow later +damo22: preferably the running vgabios +fchmmr: ok +damo22: you can dump it with this command: +damo22: sudo dd if=/dev/mem bs=64k of=runningvga.bin skip=12 count=1 + +damo22: coreboot/util/intelvbttool + +damo22: gcc intelvbttool.c -o intelvbttool + +fchmmr: it would be good for you to run intelvbttool on vgabios.bin and runningvgabios.bin. (where vgabios.bin is extracted from lenovo rom, and runningvgabios.bin is dd'd from memory after it executed) +fchmmr: right? +fchmmr: (I will do the same) +fchmmr: just runningvgabios.bin ? +damo22: its useless in the factory bios +damo22: for the purposes of this test +fchmmr: ok +fchmmr: Can't hurt though (might be useful later). +damo22: not really, it might be modified at runtime and we wont know anything about it +damo22: we need final values +damo22: the rest is irrelevant +fchmmr: Yes. I was saying to run it on final dump, and factory dump. +fchmmr: but ok, i will only do it for final dump + +-- + +further discussion, continued in #coreboot: + +damo22:we could generate fake_vbt arrays for each model +damo22:fchmmr: whats the link to the vbt stuff again +fchmmr: http://review.coreboot.org/#/c/5396 for X230 +damo22:fchmmr: no on libreboot +fchmmr: I also added this to the notes at http://libreboot.org/howto.html#i945_vbt and http://libreboot.org/howto.html#intelvbttool_results for future reference. +fchmmr: on libreboot? I don't understand. +damo22:its possible that the VBT is modified by the vgarom depending on the panel it detects, assuming it can do that +damo22:only problem is, you need info from the VBT to know where to read the EDID, so how does the vgarom do it? +damo22:maybe its safe to assume that the EDID i2c will be the same for all panels +fchmmr: Might be hardcoded (what CareBear calls "stupid magic numbers") +damo22:so we should check all VBTs of the same laptop model and verify that the EDID i2c or ddc pin is the same for all panel types +fchmmr: Sorry, when you say VBT do you mean the runningvga.bin dump taken with dd when vgarom is running? +damo22:then we can hardcode that value into the coreboot devicetree.cb + +fchmmr: I see. it's an i2c bus that connects lvds/vga/vga out +kmalkki:damo22: in your opinion, where is this EDID eeprom physically located? +damo22:kmalkki: on the panel, or the transformer for the panel +kmalkki:damo22: what do you think is a transformer for the panel? +damo22:some circuitry that interfaces between the lvds connector and the panel itself +damo22:on the T60 there is a separate module afaik +damo22:on other models it might be incorporated into the panel idk +damo22:kmalkki: i believe that the VBT has information regarding which pin of the i2c to read for the EDID eeprom/storage +damo22:and it varies panel to panel +kmalkki:would it surprise you DDC signals are often not on the panel connector +damo22:hmm + +kmalkki:like, x60 schematics is easily available, do check on some alternative ways how these are done +damo22:ok + +kmalkki:damo22: for t60 however... LCD connector does have EDID lines +damo22:kmalkki: well it would be nice to have a general solution to EDID reading +damo22:i need to understand the wiring more and the VBT +kmalkki:DDC signals originate from the graphics device +kmalkki:that will be Intel for some, ATI for some T60 ? + +damo22:kmalkki: linux expects the VBT to be in the vgarom memory area, because it uses it to identify when a panel exists, so coreboot should provide VBT like a vendor bios ? + +damo22:when vgarom is used with coreboot there is no problem , but for native gfx init it doesnt always work +kmalkki:ok.. so we can ignore ATI case for now +damo22:kmalkki: is that because no native init will be done for that case? +damo22:so the vgarom will always work +kmalkki:ok.. so do you know VBT format? +damo22:kmalkki: phcoder has done lots of work on it already +kmalkki:and.. is there a problem in reading the EDID? +damo22:kmalkki: idk yet, i need to test +damo22:im having trouble building a coreboot rom that uses coreboots native framebuffer so i can see if it worked +damo22:linux reinits the gfx so its not a good test +damo22:but in any case, without the VBT, linux cant reinit my gfx +damo22:it fails to read the EDID +damo22:and without a dock, and cbmem console isnt working, i cant get the coreboot log to check what actually happened +kmalkki:what do you mean cbmem console not working? +damo22:kmalkki: i enabled it in menuconfig and built a rom, but when i run it on my X60t cbmem -c reports No console found +kmalkki:we should get it fixed then +kmalkki:paste your .config +damo22:http://paste.debian.net/101644/ + +kmalkki:git hash is from local tree.. it does work on master, right? +damo22:idk +damo22:i just cherry picked some native gfx patches +damo22:why would it affect cbmem console +kmalkki:mess up MTRRs or memory space mapping or UMA region... +damo22:ok +kmalkki:are those patches on gerrit you picked? +damo22:well i need these patches because that is why i need the console +damo22:yes +damo22:actually i did minor changes too +damo22::S +kmalkki:yep.. which patches exactly +damo22:5320 +damo22:then i changed 2 lines +damo22:a minor devicetree.cb line and this: +damo22:- intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, +damo22:+ intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xfffff, +kmalkki:ok.. also paste 'git log' so I find common hash from master +damo22:http://paste.debian.net/101645/ + +damo22:does anyone have better google xen than me, i cant seem to find a pdf of x60 schematics +Basstard' damo22: Do you mean this? http://www.computerservice.es/wp-content/uploads/2013/05/IBM-X60.pdf + +damo22:yep thanks +kmalkki:and now that I am awake, I see DDC signals on x60 LCD too +kmalkki:just.. no DDC or I2C in the signal name but EDID +damo22:yeah +damo22:what bus does the lvds connector use +damo22:is that i2c? +damo22:or should i say, how standard is that lcd connector they are using on the X60 +kmalkki:mainboard side is completely non-standard AFAIK +damo22:ohhh +kmalkki:panel side has a few variants on the LVDS input +damo22:ok +damo22:this is not easy to generalise then +damo22:SPWG_EDID_CLK and SPWG_EDID_DATA are the signals i found on the connector + +kmalkki:yes. and it looks like phcoder-screen has done all the work to read the EDID +damo22:yes but the address and pins required are stored in the VBT i think +kmalkki:solve your CBMEM console, please +damo22:yea +Basstard' damo22: Here's a cleaner one: http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006054.pdf +kmalkki:just verify 1315730 works +damo22:1315730? + +GNUtoo-irssi: fchmmr: hi, 0x58BF58BE works fine --- cool. (not related to these discussions, but GNUtoo is happy). + +<a name="gnutoo_gtt"></a> +GNUtoo-irssi: phcoder-screen: if you're still working on native GPU init for i945(it seems so), I've an observation: +GNUtoo-irssi: gtt is not setup correctly anymore with your versions, the kenrel complains +GNUtoo-irssi: it was with a replay version, so if you're still working on it it may be an usefull hint +GNUtoo-irssi: I've added the code that works inside git, so if you want/need it, ping me +phcoder-screen:damo22: yes +GNUtoo-irssi: beside the kernel warning, the effect is slow 3D with a 3.10 lts kernel +damo22:GNUtoo-irssi: can you push it as a notformerge? +GNUtoo-irssi: ok, good idea +GNUtoo-irssi: ah sigh, again... +GNUtoo-irssi: ! [remote rejected] HEAD -> refs/for/master/NOTFORMERGE-reference-i915_gpu_init-x60 (change 3992 closed) +GNUtoo-irssi: I'll change the IDs +damo22:GNUtoo-irssi: have you seen 5230? +damo22:5320* +phcoder-screen:damo22: rank 0 of either channel is configured but not rank 1 +GNUtoo-irssi: let me look +GNUtoo-irssi: I've tried some recent branch for the t60 +GNUtoo-irssi: it works well, beside the gtt init issue I just described +damo22:GNUtoo-irssi: given that you were working on 3992 which is closed are you able to rebase your changes on top of 5320? +damo22:hmm 3992 was merged +damo22:phcoder-screen: my dimms are dual rank +<stefanct> GNUtoo-irssi: i am not too familiar with gerrit, but that error message seems to indicate that you should not try to push 3992 again because it is already merged... rebasing the remains of your changes on top of that (or origin/master) should fix that *i guess* + +URL to topic: http://review.coreboot.org/#/q/status:open+project:coreboot+branch:master+topic:NOTFORMERGE-reference-i915_gpu_init-x60,n,z +(note: this is old code, not *directly* useful but might be useful later. put this somewhere else in howto.html later) + +GNUtoo-irssi: done, NOTFORMERGE-reference-i915_gpu_init-x60 +GNUtoo-irssi: yes, I've removed the Ids +GNUtoo-irssi: so they were regenerated +GNUtoo-irssi: the goal is not to rebase at all here +GNUtoo-irssi: that's a reference code +GNUtoo-irssi: it's not for merge either +GNUtoo-irssi: If I start modifying it, I'll need to spend time testing it again +GNUtoo-irssi: I've no time right now +GNUtoo-irssi: maybe I'll have later in theses two weeks +GNUtoo-irssi: but not right now +damo22:GNUtoo-irssi: mainboard/lenovo/x60/i915* has been removed in favour of northbridge/intel/i945/gma.c in 5320 +damo22:i thought you had changes for that +GNUtoo-irssi: yes, I know +GNUtoo-irssi: what I just pushed is a *reference code* where the GTT setup works +GNUtoo-irssi: it's old +GNUtoo-irssi: it's not meant to be merged +GNUtoo-irssi: it's not rebased +GNUtoo-irssi: it's just frozen code where it's known to work +GNUtoo-irssi: that's all + +damo22:ok +GNUtoo-irssi: it doesn't even handle backlight +GNUtoo-irssi: even with devmem2... +damo22:i'll see if i can find the gtt stuff and compare to 5320 +damo22:could be a one liner +damo22:physbase -> uma_memory_base+256*KiB +phcoder-screen:damo22: yes and rank 1 config failed +damo22:phcoder-screen: ok, so i'll get you that mchbar dump +phcoder-screen:damo22: no need yet. I found out that in another ram config my X230 fails as well. I'll investigate this first + +kmalkki:GNUtoo-irssi: please abandon the duplicates in your gerrit space +kmalkki:also any microcode files will not be removed until working copies are in 3rdparty/ + +kmalkki:we probably want to keep the old version in gerrit, with all the comments made previously + +damo22:kmalkki: all those patches are noformerge +damo22:not* +kmalkki:damo22: still they are duplicates of already reviewed patches +kmalkki:why the heck the new change-ids +damo22:maybe a git diff to a pastebin would have been better + +GNUtoo-irssi: ls +GNUtoo-irssi: oops +<uberushaximus> hunter2 +kmalkki:GNUtoo-irssi: please explain your motivation to push that stuff on gerrit +kmalkki:it is not even rebased to current but 6 months old HEAD +GNUtoo-irssi: GTT is setup badly on x60 +GNUtoo-irssi: with the recent changes from phcoder +GNUtoo-irssi: what I pushed is a version that is known to have the GTT setup correctly +GNUtoo-irssi: it's for reference +GNUtoo-irssi: so people working on i945 native GPU init would use it to fix that issue faster +GNUtoo-irssi: like diff both +GNUtoo-irssi: or something like that +GNUtoo-irssi: kmalkki: do you have a better description for the topic branch name that describe what I just said? +kmalkki:well gerrit is not for the purpose of storing references +kmalkki:most of those patches already had Change-IDs +kmalkki:now we have duplicates.. and comments can end up in either place +kmalkki:it was already a havoc with native init before +GNUtoo-irssi: ok, so instead I should remove that branch, and push on gitorious? +kmalkki:all of You working on it, try to work a setup that suits you all well +GNUtoo-irssi: briefly: it's for tracking a regression + +kmalkki:well I do not do i915 gfx stuff.. but clearly you have a lot of problems trying to keep and follow each others work +kmalkki:and what works and where the regressions have happened +PaulePanter: GNUtoo-irssi: Hi. Do you know if the amount memory reserved for i945 IGD is always constant or if that is configurable? +PaulePanter: GNUtoo-irssi: I did not see a table in the 3rd Gen datasheet. +PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-family-mobile-vol-2-datasheet.pdf +GNUtoo-irssi: PaulePanter: you mean the GSM? +GNUtoo-irssi: (Graphics stolen memory) +PaulePanter: GNUtoo-irssi: Yes. + +PaulePanter: Section 2.5.33 BDSM—Base Data of Stolen Memory Register +GNUtoo-irssi: If I remmeber well it's configurable, but we use the values advised by the datasheet +GNUtoo-irssi: which are derived from the ammount of RAM +PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20). +PaulePanter: GNUtoo-irssi: Yes, I am unable to find the advised values. +damo22:PaulePanter: are you sure thats the right datasheet for the cpu inside the X60? + +GNUtoo-irssi: ok +GNUtoo-irssi: I can look +PaulePanter: damo22: Not 100 %. +damo22:afaik, BSDM is something kinky in the core iX processors +GNUtoo-irssi: uma_size = 1024; +PaulePanter: Chris Wilson from the Intel graphics Linux driver team said that BDSM ist incorrectly set up. +PaulePanter: … on the i945. +PaulePanter: … by coreboot. +PaulePanter: This is Volume 2 of the Datasheet for the following products: +PaulePanter: Mobile 3rd Generation Intel ® CoreTM processor family +GNUtoo-irssi: in pci_domain_set_resources in northbridge.c +PaulePanter: Mobile Intel ® Pentium ® processor family +GNUtoo-irssi: ok +PaulePanter: Mobile Intel ® Celeron ® processor family +PaulePanter: GNUtoo-irssi: Thanks. So it is constant for now. +PaulePanter: GNUtoo-irssi: So just 1 MB graphics memory? + +damo22:i dont remember him mentioning BDSM in the bug report, but he did say the GTT was incorrectly set up? +damo22:graphics stolen stuff +GNUtoo-irssi: no it's not +GNUtoo-irssi: read the function +PaulePanter: “Stolen memory has been set up incorrectly by coreboot.” +PaulePanter: GNUtoo-irssi: Ok. +PaulePanter: GNUtoo-irssi: No idea, if you are aware of https://bugs.freedesktop.org/show_bug.cgi?id=79038 . +GNUtoo-irssi: http://paste.debian.net/101662/ +[ 0.764084] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input3 +[ 0.771023] pci 0000:00:00.0: Intel 945GM Chipset +[ 0.771075] pci 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable +[ 0.771669] pci 0000:00:00.0: detected 8192K stolen memory +[ 0.771738] [drm] Memory usable by graphics device = 256M +[ 0.772124] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 0.772126] [drm] Driver supports precise vblank timestamp query. +[ 0.772133] i915 0000:00:02.0: Invalid ROM contents +[ 0.772141] [drm] failed to find VBIOS tables +[ 0.772192] [drm] GPU crash dump saved to /sys/class/drm/card0/error +[ 0.772196] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. +[ 0.772198] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel +[ 0.772200] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. +[ 0.772202] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. +[ 0.772207] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 0.772217] i915: render error detected, EIR: 0x00000010 +[ 0.772224] i915: page table error +[ 0.772227] i915: PGTBL_ER: 0x00000012 +[ 0.772233] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking +[ 0.772247] i915: render error detected, EIR: 0x00000010 +[ 0.772252] i915: page table error +[ 0.772255] i915: PGTBL_ER: 0x00000012 +[ 0.924707] [drm] initialized overlay support +[ 1.126501] fbcon: inteldrmfb (fb0) is primary device +[ 1.360027] tsc: Refined TSC clocksource calibration: 1828.749 MHz +[ 1.482148] Console: switching to colour frame buffer device 175x65 +[ 1.490507] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 1.490510] i915 0000:00:02.0: registered panic notifier +[ 1.490522] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 1.491931] console [netcon0] enabled +[ 1.491933] netconsole: network logging started +[ 1.494021] ACPI: bus type USB registered +GNUtoo-irssi: that is the regression ^^^^ +GNUtoo-irssi: See PGTBL_ER +GNUtoo-irssi: The bits are documented +damo22:i have compared GNUtoo-irssi's patchset with the 5320 stuff that phcoder did, and i found that 1 line needs to be changed +GNUtoo-irssi: (I don't remember where, probably in the datasheet that applies to the more recent GPUs (sic)) + +damo22:its the base address of the gma init call + +PaulePanter: damo22: Are you going to push a patch for testing? + +damo22:but in order for it to work you need vgarom with native init, it doesnt run the rom just uses it for VBT +PaulePanter: damo22: I still not see how that should fix the error, but we’ll see. +damo22:how do i squash my commits into one patch that can be applied to 5320? +PaulePanter: damo22: Is that patch really dependent on 5320? I thought it is also needed for the current native graphics init in the tree? + +PaulePanter: damo22: `git rebase -i +PaulePanter: ` +PaulePanter: damo22: git rebase -i commit-hash-of-5320 +damo22:thanks +PaulePanter: damo22: To squash you will need to change `pick` to `f` or `s` for `fixup` or `squash`. + +damo22:i have a patch that could be tested on X60: http://review.coreboot.org/#/c/5868/ +PaulePanter: damo22: On Nehalem: +PaulePanter: src/northbridge/intel/nehalem/gma.c: intel_gma_init(conf, gtt_res->base, physbase, pio_res->base, +PaulePanter: src/northbridge/intel/nehalem/gma.c- lfb_res->base); +damo22:PaulePanter: i fail to see relevance of nehalem in i945 +PaulePanter: damo22: Hopefully the code can be written in a way that common paths are written the same. +PaulePanter: damo22: Let’s first see if the patch fixes it. + +PaulePanter: damo22: By the way, which datasheet do you think is correct for the Intel 945 IGD in the Lenovo T60 and X60? + +damo22:whichever datasheet includes 945PM (Calistoga) Graphics +damo22:is it PM or GM? +PaulePanter: damo22: I thought GM. +damo22:PM has no integrated graphics so it must be GM +PaulePanter: damo22: Document Number: 309219-006 +damo22:PaulePanter: this must be the datasheet: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/mobile-945-express-chipset-datasheet.pdf + +PaulePanter: Mobile Intel® 945 Express Chipset Family +PaulePanter: damo22: ;-) + +damo22:309219-006 is correct +PaulePanter: Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From +kmalkki:PaulePanter: did you go through the list of patches in your gerrit space that I suggested needed rebase? +PaulePanter: the top of low used DRAM, (G)MCH claims 1 to 64 MBs of DRAM for internal graphics if +PaulePanter: enabled. +PaulePanter: kmalkki: I thought I did go through most of them. +kmalkki:do you have the list +kmalkki:I did not keep copy :/ +kmalkki:5388 +kmalkki:that is AMR +PaulePanter: kmalkki: Don’t waste you time with it. I have a copy of your list somewhere and will go through it in the next days. +kmalkki:PaulePanter: +1 5388 +damo22:PaulePanter: its an integrated GMA 950 afaik +idwer: oh... 5388 has no priority whatsover to me +idwer: not anymore ;) + +damo22:does GM45 support in coreboot have ddr2 AND ddr3 support? + +damo22:well that means X200 could be ported with ME disabled +phcoder-screen:damo22: that's my next fun project after raminit for ivy. +* thomasg_ is now known as thomasg + +damo22:fchmmr: LTN150XG-L08 is my T60 EDID string (for his T60 15" -- this is already noted below in intelvbttool results) + +fchmmr: damo22: ok, i should test 5868? I understand it puts the vgarom inside but without running it (just for getting VBT tables) but latre we could replace it with something like what the X230 "Deploy VBT" does +damo22:yeah +fchmmr: Let me read backlog... +damo22:fchmmr: you dont need backlog, everything you need is in the 5868 commit +fchmmr: how did your X60t unbricking go, damo22? +damo22:havent bothered finding my screwdrivers yet +fchmmr: I need to.... tidy myself up. Back in an hour or so. +fchmmr: damo22: upload a ROM for me, with 5868 and grub payload +fchmmr: I'll test it for you +damo22:im not good with grub payloads +damo22:i can give you one with seabios +fchmmr: ok give me that, +fchmmr: also hm ok, give me your .config. I'll add grub myself +damo22:ok +damo22:fchmmr: http://paste.debian.net/plain/101692 +# +# Automatically generated make config: don't edit +# coreboot version: 4.0-5614-gdb77532 +# Mon May 26 00:11:44 2014 +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_SCANBUILD_ENABLE is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VGA_BIOS=y +# CONFIG_CONSOLE_POST is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_SERIAL_CPU_INIT=y +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_VGA_BIOS_FILE="vgabios.bin" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +# CONFIG_VGA is not set +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_IOAPIC=y +CONFIG_SMP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60 / X60s" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set + +# +# Architecture (x86) +# +CONFIG_X86_ARCH_OPTIONS=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_X86_BOOTBLOCK_SIMPLE=y +# CONFIG_X86_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HAVE_ARCH_MEMSET=y +CONFIG_HAVE_ARCH_MEMCPY=y +CONFIG_HAVE_ARCH_MEMMOVE=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set + +# +# Chipset +# + +# +# CPU +# +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HAVE_INIT_TIMER=y +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_CBFS_SIZE=0x200000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_AMD_SB_SPI_TX_LEN=4 +# CONFIG_SPI_FLASH is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 + +# +# VGA BIOS +# + +# +# Display +# + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVERS_OXFORD_OXPCIE is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_RTL8168_ROM_DISABLE is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_HAVE_UART_IO_MAPPED=y +# CONFIG_HAVE_UART_MEMORY_MAPPED is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT=y + +# +# Console +# +CONFIG_EARLY_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_SERIAL8250=y +CONFIG_CONSOLE_SERIAL_COM1=y +# CONFIG_CONSOLE_SERIAL_COM2 is not set +# CONFIG_CONSOLE_SERIAL_COM3 is not set +# CONFIG_CONSOLE_SERIAL_COM4 is not set +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_CONSOLE_NE2K is not set +# CONFIG_CONSOLE_CBMEM is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_IO_POST=y +CONFIG_IO_POST_PORT=0x80 +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_GFXUMA=y +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_LINUX is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set + +damo22:you need to still add the vgabios filename +damo22:CONFIG_VGA_BIOS_FILE="vgabios.bin" is the current setting +damo22:# CONFIG_CONSOLE_CBMEM is not set woops + +fchmmr: damo22 » register "gpu_lvds_is_dual_channel" = "1" +fchmmr: on x60/devicetree.cb +damo22:fchmmr: well check your VBT i think its correct though +fchmmr: so 0 was wrong? +damo22:it might depend on panel + +fchmmr: Oh +fchmmr: I get it now. +fchmmr: I didn't see any code in 5868 that executes anything from the vgarom but, +fchmmr: you set coreboot to load it into memory, but not execute it. +fchmmr: I thought "load" only meant put it in cbfs +fchmmr: is this a correct assessment? +fchmmr: To let kernel find vbt tables. +fchmmr: And then we "fake" it later (withotu vga rom loaded). +fchmmr: damo22: are you testing 5868 on your X60t? +damo22:fchmmr: its to make linux kernel detect lvds after native init, but if you can also test coreboot native framebuffer with grub too, that would be handy + +fchmmr: So, vgarom has nothing to do with that patch. +fchmmr: ? +fchmmr: All I see is a change of stolen memory address, and the backlight values added +damo22:fchmmr: its tricky because the final vgabios in memory changes depending on the panel, because vgarom is self modifying + +fchmmr: So should I include the vgarunning.bin instead of vgabios.bin ? +damo22:yes + +damo22:fchmmr: if you can load grub as payload and you see something, its a success +fchmmr: damo22: the problem is, without that patch I just use 5320 as-is, and I see grub as payload already. +fchmmr: Hence my question above. +damo22:fchmmr: also, if you can boot into linux after that and dont get any error messages from drm module, its a double success +fchmmr: Which error messages (besides "Invalid ROM contents") am I looking for? +damo22:fchmmr: stuff like, page fault +fchmmr: And should I enable any specific debugging options (such as drm.debug=0x06) +damo22:yes that would help +fchmmr: Ok: which logs do you want? +fchmmr: I'll upload it for your reference +damo22:fchmmr: kernel boot log and Xorg.0.log, coreboot log if possible +fchmmr: probably kern.log and Xorg.0.log +fchmmr: coreboot log is possible, i have dock. +fchmmr: anything else? +damo22:that is all, thanks +fchmmr: ok. will do. + +fchmmr: damo22: I could test this on T60 aswell by cherry picking 5345, right? +damo22:fchmmr: idk +fchmmr: (and addinf backlight value to deivcetree) +fchmmr: We should devise a way to test this on T60 aswell. +damo22:fchmmr: lets just see if the x60 fix works + +damo22:it still needs work if the test passes +fchmmr: Ok but, you just have that one line changed in gma.c, and backlight value changed it x60/devicetree.cb +damo22:yes +damo22:phcoder did most of the work +fchmmr: So, I could run this same test on T60 by cherry picking 5345 on top of 5868, changing t60/devicetree.cb's backlight value and including T60 runningvga.bin and having that load (but not execute) +damo22:its a small bug i think +fchmmr: I will do that above, after X60 is tested. +damo22:fchmmr: youre always talking about more and more combinations of tests, lets just get one right +fchmmr: Yes. Just a thought. We'll test X60 exclusively. T60 can easily be tested later. +fchmmr: Ok..... back soon. I'll get you the results you wanted. I'll be using 3.14.4 (the one samnob made). +damo22:thanks + +fchmmr: We should do this with the latest runningvga.bin (from extracting with dd on the latest vgabios.bin) +fchmmr: My one is older +damo22:fchmmr: version number of vgabios is irrelevant if it was taken from a lenovo bios that used to run on your machine, and since pulled from ram +damo22:ie, it should have the correct VBT values +damo22:for your machine + + + +</pre> +</p> + diff --git a/docs/future/dumps/x b/docs/future/dumps/x new file mode 100644 index 0000000..1ef5139 --- /dev/null +++ b/docs/future/dumps/x @@ -0,0 +1,1442 @@ + + +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (417848 bytes), entry @ 0x100000 +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2975 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529332 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353806 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124473 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5804 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00160000, stack_end 00160ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11641 loops) +CPU1: stack: 00160000 - 00161000, lowest used address 00160c68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687708 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +Initializing VGA without OPROM. +GMADR=0xd0000008 GTTADR=0xe4400000 +i915lightup: graphics d0020000 mmio e4300000 addrport 50a0 physbase bf800000 +Extracted contents: +header: 00 ff ff ff ff ff ff 00 +serial number: 30 ae 00 40 00 00 00 00 00 0f +version: 01 03 +basic params: 80 19 12 78 ea +chroma info: ed 75 91 57 4f 8b 26 21 50 54 +established: 21 08 00 +standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 +descriptor 1: 28 15 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 2: ed 10 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 3: 00 00 00 0f 00 61 43 32 61 43 28 0f 01 00 4c a3 58 4a +descriptor 4: 00 00 00 fe 00 4c 54 4e 31 32 31 58 4a 2d 4c 30 37 0a +extensions: 00 +checksum: 00 + +Manufacturer: LEN Model 4000 Serial Number 0 +EDID version: 1.3 +Digital display +Maximum image size: 25 cm x 18 cm +Gamma: 220% +Check DPMS levels +DPMS levels: Standby Suspend Off +Supported color formats: RGB 4:4:4, YCrCb 4:2:2 +First detailed timing is preferred timing +Established timings supported: + 640x480@60Hz + 800x600@60Hz + 1024x768@60Hz +Standard timings supported: +Detailed timings +Hex of detail: 281500404100263018883600f6b900000018 +Did detailed timing +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: ed1000404100263018883600f6b900000018 +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: 0000000f006143326143280f01004ca3584a +Manufacturer-specified data, tag 15 +Hex of detail: 000000fe004c544e313231584a2d4c30370a +ASCII string: LTN121XJ +Checksum +Checksum: 0x0 (valid) + +Unknown extension block + +EDID block does NOT conform to EDID 1.3! + Missing name descriptor + Missing monitor ranges + Detailed block string not properly terminated +EDID block does not conform at all! + Bad year of manufacture + Detailed blocks filled with garbage +I915_WRITE(HTOTAL(pipe), 053f03ff) +I915_WRITE(HBLANK(pipe),0x053f03ff) +I915_WRITE(HSYNC(pipe),0x049f0417) +I915_WRITE(VTOTAL(pipe), 032502ff) +I915_WRITE(VBLANK(pipe),0x032502ff) +I915_WRITE(VSYNC(pipe),0x03080302) +Table has 2247 elements +Change verbosity to 0 +run: return 2246 +Run returns 2247 +gtt_setup: GTT PGETLB_CTL register: 0x0 +gtt_setup: GTT PGETLB_CTL register: 0x1 +gtt_setup: GTT PGETLB_CTL register: 0xbf800001 +gtt_setup: GTT PGETLB_CTL register: 0xbf800003 +gtt_setup is enabled: GTT PGETLB_CTL register: 0x1 +setgtt(0,1600,0xbf800000,4096); +GTT PGETLB_CTL register: 0xbf800001 +GTT Enabled +memset d0020000 to 0x00 for 3145728 bytes +229929 microseconds +PCI: 00:02.0 init 265041 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2382 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4490 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4489 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4925 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4926 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1683 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50455 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4942 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7210 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1669 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1668 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7377 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1670 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1670 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1670 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1582 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1584 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1584 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16205 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3593 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1411225 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp tabl +6653 bytes lost diff --git a/docs/future/dumps/x60_5893_native.tar.gz b/docs/future/dumps/x60_5893_native.tar.gz Binary files differnew file mode 100644 index 0000000..59266f8 --- /dev/null +++ b/docs/future/dumps/x60_5893_native.tar.gz diff --git a/docs/future/dumps/x60_5893_native_crashdump b/docs/future/dumps/x60_5893_native_crashdump new file mode 100644 index 0000000..a3aedb6 --- /dev/null +++ b/docs/future/dumps/x60_5893_native_crashdump @@ -0,0 +1,77 @@ +Time: 1401660987 s 272232 us +Kernel: 3.14.4-gnuowen +PCI ID: 0x27a2 +EIR: 0x00000010 +IER: 0x00028053 +PGTBL_ER: 0x00000012 +FORCEWAKE: 0x00000000 +DERRMR: 0x00000000 +CCID: 0x00000000 +Missed interrupts: 0x00000000 + fence[0] = 00000000 + fence[1] = 00000000 + fence[2] = 00000000 + fence[3] = 00000000 + fence[4] = 00000000 + fence[5] = 00000000 + fence[6] = 00000000 + fence[7] = 00000000 + fence[8] = 00000000 + fence[9] = 00000000 + fence[10] = 00000000 + fence[11] = 00000000 + fence[12] = 00000000 + fence[13] = 00000000 + fence[14] = 00000000 + fence[15] = 00000000 + INSTDONE_0: 0x7fffffc0 + INSTDONE_1: 0x00000000 + INSTDONE_2: 0x00000000 + INSTDONE_3: 0x00000000 +Active [0]: +Pinned [0]: +Num Pipes: 2 +Pipe [0]: + Power: off + SRC: 00000000 +Plane [0]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [0]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +Pipe [1]: + Power: off + SRC: 00000000 +Plane [1]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [1]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 diff --git a/docs/future/dumps/x60_5893_vbios.tar.gz b/docs/future/dumps/x60_5893_vbios.tar.gz Binary files differnew file mode 100644 index 0000000..4ff7840 --- /dev/null +++ b/docs/future/dumps/x60_5893_vbios.tar.gz diff --git a/docs/future/index.html b/docs/future/index.html new file mode 100644 index 0000000..c525439 --- /dev/null +++ b/docs/future/index.html @@ -0,0 +1,741 @@ +<!DOCTYPE html> +<html lang="en"> +<head> + <meta charset="utf-8"> + <title>libreboot tutorials</title> + + <style type="text/css"> + body { + font-family: sans-serif; + font-size: 1em; + background: #fff; + color: #000; + } + + </style> + + <meta name="viewport" content="width=device-width, initial-scale=1.0"> + <meta name="author" content="glugman"> + <meta name="description" content="tutorials for libreboot, the reboot library."> + <meta name="robots" content="all"> +</head> + +<body> + + <header> + <h1 id="pagetop">Development notes</h1> + <aside>These are development notes, for future use.</aside> + </header> + + <p> + Or go <a href="../">back to main document index</a>. + </p> + +<hr/> + + <h2>Contents</h2> + <ul> + <li><a href="#todo">TODO list</a></li> + <li><a href="#standard_test">Standard test</a></li> + <li><a href="#t60_cpu_microcode">T60 cpu microcode</a></li> + <li><a href="#lcd_i945_incompatibility">LCD panels on i945 - fix incompatible panels</a></li> + <li><a href="#blind_x60">Blind X60 - kernel git bisect</a></li> + <li><a href="#x60_native_notes">X60 native graphics initialization (backlight controls)</a></li> + <li><a href="#t60_native_notes">T60 native graphics initialization (backlight controls)</a></li> + <li><a href="#5320_kernel312fix">i945: 3D fix (based on 5927) for kernel 3.12+ on 5320</a></li> + <li><a href="#x60_cb5927_testing">i945/x60: coreboot 5927 testing (3D fix for kernel 3.12+ on replay code)</a></li> + <li><a href="#i945_vbt">i945 X60/T60 VBT implementation (experimental: testing)</a></li> + <li><a href="#intelvbttool_results">IntelVbtTool results</a></li> + <li><a href="#cpu_cstates_buzzing">CPU c-states (X60/T60) buzzing sound on CPU idle</a></li> + <li><a href="#battery_eventc">Battery 'event c' on X60 (and T60?)</a></li> + </ul> + +<hr/> + + <h1 id="todo">TODO (bold means high priority)</h1> + <ul> + <li><b><a href="#blind_x60">#blind_x60</a>: kernel git bisect (find which commit broke graphics when native graphics or vbios is not in use)</b></li> + <li><b>test the latest version of <a href="http://review.coreboot.org/#/c/5927">http://review.coreboot.org/#/c/5927</a> for Paul Menzel</b></li> + <li> + <b>test the latest versions of 5320/5345 on X60/T60</b> + <ul> + <li><b><s>Find how to implement the fix from <a href="http://review.coreboot.org/#/c/5927">5927/3</a></s> (see <a href="#5320_kernel312fix">#5320_kernel312fix</a>) and push with 5320 as dependency</b></li> + <li><b>Find how to implement the fix from <a href="http://review.coreboot.org/#/c/5927">5927</a> (latest version after patch set 3) and push with 5320 as dependency</b></li> + <li><b>Implement the X60 backlight support (<a href="#x60_native_notes">#x60_native_notes</a>) and push with 5320 as dependency</b></li> + <li><b>Implement the T60 backlight support (<a href="#t60_native_notes">#t60_native_notes</a>) and push with 5345 as dependency</b></li> + </ul> + </li> + <li> + <b><a href="#intelvbttool_results">#intelvbttool_results</a>: Finish getting runningvga.bin dumps and intelvbttool dumps for all known targets on X60 and T60.</b> + <ul> + <li>Figure out why 15" T60 with 1024x768 panel doesn't work on native graphics initialization. And fix it (implementing VBT might, also understanding how + to correctly interpret EDID, according to phcoder and damo22).</li> + <li><b><a href="#i945_vbt">#i945_vbt</a>: Finish getting results when running native init and loading (but not executing) the VBIOS option ROM.</b></li> + <li>When VBT is implemented/tested, also test SeaVGABIOS (part of SeaBIOS)</li> + </ul> + </li> + <li> + <b>Run oprom trace (coreboot + oprom + grub) on <a href="http://review.coreboot.org/#/c/5345">http://review.coreboot.org/#/c/5345</a> for phcoder.</b> + (see <a href="#t60_native_notes">#t60_native_notes</a>) + </li> + <li>test that patch (DYNAMIC_CBMEM, <a href="http://review.coreboot.org/#/c/6036">http://review.coreboot.org/#/c/6036</a>) on X60 and T60 for kmalkki</li> + <li>X60 Tablet digitizer support (<a href="http://review.coreboot.org/#/c/5243/">http://review.coreboot.org/#/c/5243/</a>, also see 5242)</li> + <li> + <li>Further study how backlight controls work</li> + <li> + <b>After all (or a satisfactory amount) of the above is done, finish deblobbing latest coreboot revisions.</b> + <ul> + <li><b>Totally re-tool linux-libre deblob scripts to automatically deblob other revisions of coreboot aswell</b></li> + <li><b>Ports for T60 and F2A85M</b></li> + </ul> + </li> + <li><b>Write information about software/hardware modifications (security)</b></li> + <li>funfunctor wants me to try building libreboot/coreboot on X60 with clang/llvm because he says there are some issues where boards fail when built with this: fchmmr: well you will need to compile the latest clang, here are some instructions: https://gist.github.com/victoredwardocallaghan/38689e88dd7b9a439468 and also: funfunctor: fchmmr: you will need the latest coreboot code and http://review.coreboot.org/#/c/5814/ to get clang to build whatever board. also! <br/><br/> + + fchmmr: see this topic http://review.coreboot.org/#/q/status:open+project:coreboot+branch:master+topic:clang-fixes,n,z you will need those fixes to get anywhere with building t60/x60 with clang. at the time of writing that was 6122/1, 6121/1, 6120/1 and 6119/1<br/><br/> + + fchmmr: its unclear if http://review.coreboot.org/#/c/6129/ has uncovered a bug yet or not..fchmmr: well this was a bug spotted http://review.coreboot.org/#/c/6052/<br/><br/> + + funfunctor says X60 (not sure about T60) ROM's can now be built with Clang/LLVM</li> + <li>Investigate <a href="#battery_eventc">#battery_eventc</a>.</li> + </ul> + + <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="standard_test">standard test</h1> + <p> + These logs are usually obtained when testing changes related to graphics on i945 (X60 and T60). + </p> + <ul> + <li> + Make a copy of these files: + <ul> + <li>/var/log/dmesg</li> + <li>/var/log/kern.log</li> + <li>/var/log/Xorg.0.log</li> + <li>/proc/ioports</li> + <li>/proc/iomem</li> + <li>/sys/class/drm/card0/error</li> + </ul> + </li> + <li> + Record these outputs: + <ul> + <li>sudo intel_reg_dumper</li> + <li>uname -r</li> + <li>lspci -vvvvnnnnxxxx</li> + <li>sudo modprobe msr</li> + <li>sudo inteltool -a</li> + <li>sudo cbmem -c</li> + </ul> + </li> + <li> + Try some 3D games with latest kernel. + </li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="t60_cpu_microcode">T60 cpu microcode</h1> + + <p> + TODO: T60: find (for rare buggy CPU's that are unstable without microcode updates) if there is a workaround (patched kernel, special parameter, etc) So far, only 1 processor has been found to have issues. See microcode errata sheets http://download.intel.com/design/mobile/SPECUPDT/31407918.pdf and http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf and then look at the debugging results collected in <a href="../t7200q">t7200q</a> directory (q means quirk). + </p> + + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="lcd_i945_incompatibility">LCD panels on i945 - fix incompatible panels</h1> + + <p> + Fix X60 Tablet issues (see incompatible panels listed at <a href="../index.html#supported_x60t_list">../index.html#supported_x60t_list</a>). + </p> + + <p> + Fix T60 issues (see incompatible panels listed at <a href="../index.html#supported_t60_list">../index.html#supported_t60_list</a>). + </p> + + <p> + Run that tool (resources/utilities/i945gpu/intel-regs.py) as root on machines with the offending panels in: + </p> + <ul> + <li>Coreboot (or libreboot, whatever) with VBIOS (disable native graphics also)</li> + <li>(Factory BIOS also?)</li> + </ul> + + <p> + This shows values in devicetree.cb and src/northbridge/intel/i945/gma.c, the idea is that you run it on factory bios or vbios + and that it will (might) show different values: then you try those in the native graphics (in libreboot). + </p> + + <p> + Other values/registers might also need to be added to the script for these tests. + </p> + + <p> + Original getregs.py script can be found at <a href="http://hg.mtjm.eu/scripts/file/tip/intel-regs.py">http://hg.mtjm.eu/scripts/file/tip/intel-regs.py</a> + written by Michał Masłowski. + </p> + + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="blind_x60">Blind X60 - kernel git bisect</h1> + <p> + Older kernels could init GPU on an X60 without a vbios or native graphics. + I have to do a git bisect to find out when that was broken. + </p> + + <ul> + <li>See <a href="https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=613979#102">https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=613979#102</a></li> + <li><b>git help bisect</b> has an example of how to bisect</li> + <li>See <a href="http://git-scm.com/book/en/Git-Tools-Debugging-with-Git#Binary-Search">http://git-scm.com/book/en/Git-Tools-Debugging-with-Git#Binary-Search</a></li> + <li> + I have ccache. Read on how to compile kernel using ccache instead of regular gcc. (speeds up compiling). How I installed it: + <ul> + <li>sudo apt-get install ccache</li> + <li>echo 'export PATH="/usr/lib/ccache:$PATH"' | tee -a ~/.bashrc \ && source ~/.bashrc && echo $PATH</li> + </ul> + </li> + </ul> + + <p> + Note: "memory_corruption_check=0 i915.lvds_channel_mode=2" kernel parameters were once used + successfully for linux-libre 3.10 on a ThinkPad T60 (distribution: Parabola) to get graphics working. + </p> + + <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="x60_native_notes">X60 native graphics initialization (with backlight controls)</h1> + <p> + <b><i>Also check <a href="#5320_kernel312fix">#5320_kernel312fix</a> (to fix 3D on kernel 3.12/higher)</i></b> + </p> + <p> + <b>The fix below was done on 5320/6 but should work just fine on later versions of 5320.</b> + </p> + <p> + Native gpu init + backlight controls! (Fn keys). Also confirmed on X60 Tablet (1024x768) and X60 Tablet (1400x1050) + </p> + <p> + <b>Checkout <a href="http://review.coreboot.org/#/c/5320">http://review.coreboot.org/#/c/5320</a> on top of a coreboot git clone.</b> + </p> + <p> + <b>Add backlight controls:</b> in <i>src/mainboard/lenovo/x60/devicetree.cb</i>, change <b>gpu_backlight</b> to <b>0x879F879E</b> + </p> + <p> + That's all! <b>This has also been backported into libreboot 5th release (line 1233 in src/mainboard/lenovo/x60/i915io.c)</b>. GNUtoo (Denis Carikli) + told me about the register <b>BLC_PWM_CTL</b> and that you could set it to control backlight. I read that address using devmem2 while running the VBIOS:<br/> + <b># devmem2 0xe4361254 w</b> + </p> + <p> + When doing this, it gave back that value. The same trick was used to get backlight controls for T60 (see <a href="#t60_native_notes">#t60_native_notes</a>). + </p> + + <h2>Further notes</h2> + <p> + Reading <b>0xe4361254</b> (address) in Lenovo BIOS always yields FFFFFFFF, even when writing to it (and writing to it doesn't affect brightness controls). + 'mtjm' on IRC found that the buttons (Fn keys) control /sys/class/backlight/acpi_video0 which has no affect on 61254 (BLC_PWM_CTL). He says + intel_backlight has different values and uses the register. devmem2 works, needs checking <b>lspci -vv</b> for where the memory is mapped, + which is different than on coreboot; mtjm found that it was 0xec061254 on his machine (X60 Tablet), and the register value is different too. + <b>This is relevant, because we still don't know how backlight controls are actually handled. We got it working by accident. We need to know more.</b>. + </p> + <p> + Intel-gpu-tools may prove useful for further debugging: <a href="http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/">http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/</a> + </p> + <p> + mtjm says 0xe4300000 is an MMIO region of the gpu (lspci -vv shows it), 0x61254 (BLC_PWM_CTL) is a documented register. Searching the kernel driver for backlight + shows that in intel_panel.c this register is used (there is an XXX comment about finding the right value, where recent kernels get it from. + </p> + <p> + What we want to do is calculate a good value, instead of setting it in devicetree.cb. mtjm says about backlight physics: + it has a light source , uses pulse width modulation (PWM) to turn it on/off, dimming is done by spending less time on. + <b>Note: this may not be correct; he says his understanding is based on how the Lenote yeeloong works</b>. + </p> + <p> + mtjm goes on to say, that the register specifies the frequency used for PWM in its depending on the GPU core frequency, so it + might be possible to calculate it without hardcoded laptop-specific values. Therefore, I am supposed to find out the 'display core frequency' + (mtjm says there might be a register for it; also, it might be in 5320 or the replay code) and the PWM modulation frequency. + https://en.wikipedia.org/wiki/Backlight#Flicker_due_to_backlight_dimming + </p> + <p> + phcoder (Vladimir Serbinenko) who is author of 5320 (review.coreboot.org) talks about 'duty cycle limit' and 'flickering frequency'. + </p> + + <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="t60_native_notes">T60 native graphics initialization (with backlight controls)</h1> + <p> + <b><i>Also check <a href="#5320_kernel312fix">#5320_kernel312fix</a> (to fix 3D on kernel 3.12/higher)</i></b> + </p> + <p> + <b>The fix below was done on an earlier version of 5345, but should work on the current version.</b> + </p> + <p> + Native gpu init + backlight controls! (Fn keys). <b>Working on all panels except for 14" XGA (1024x768) and 15" XGA (1024x768)!</b> + <p> + <p> + <b>Checkout <a href="http://review.coreboot.org/#/c/5320">http://review.coreboot.org/#/c/5320</a> + and then cherry-pick <a href="http://review.coreboot.org/#/c/5345">http://review.coreboot.org/#/c/5345</a> on top of a coreboot git clone.</b> + </p> + <p> + <b>Add backlight controls:</b> in <i>src/mainboard/lenovo/t60/devicetree.cb</i>, change <b>gpu_backlight</b> to <b>0x58BF58BE</b> + </p> + <p> + Hold on! Check <a href="../index.html#get_edid_panelname">../index.html#get_edid_panelname</a> to know what LCD panel you have. This is important for the next step! + </p> + + <h2>Supported panels</h2> + <p> + <a href="../index.html#supported_t60_list">../index.html#supported_t60_list</a>. + </p> + + <p> + Note to self: Run oprom trace for phcoder (T60 w/ 5320+5345 + oprom + grub) for phcoder. This (among other things) + might help to get all panels supported, without modification. + </p> + + <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="5320_kernel312fix">i945: 3D fix (based on 5927) for kernel 3.12+ on 5320</h1> + + <p><b>This needs to be rewritten (or better organized, or deleted?)</b>. This is also now included in libreboot 6 (using the proper way, not the 7c0000 method which was a hack)</p> + + <p> + <b>This was done on 5320/6 so far. The fix below is for 5320/6 which is now obsolete. This needs to be re-done for the latest version + of 5320. The fix below is (in practise) only for reference, therefore.</b> + </p> + + <p> + See <a href="#x60_cb5927_testing">#x60_cb5927_testing</a> for the original (and current) fix, for the replay code. Now we want + to implement that on top of <a href="http://review.coreboot.org/#/c/5320">http://review.coreboot.org/#/c/5320</a> + which is the current code for native graphics initialization on i945. + </p> + + <p> + src/northbridge/intel/i945/gma.c (using the 7c0000 hack) on 5320: <a href="dumps/5320_7c0000_gma.c">5320_7c0000_gma.c</a> (rename it to gma.c, + replacing the current one). + </p> + + <p> + The above is a hack (as is the original). A better (more correct) method is implemented in later versions of 5927, so + that should also be adapted for 5320. For now, you can use the above fix. + </p> + + <p> + The correct way to do it is to set gtt address to (end of stolen memory - gtt size), which is what later versions of 5927 do (successfully). + </p> + + <p> + Here is some debugging output using intel_gpu_tools v1.2-1 (from trisquel repositories) using tool "intel_gtt": + </p> + + <ul> + <li> + Trisquel 6. kernel 3.14.4: + <ul> + <li>with libreboot 5th release (using the 7c0000 gtt hack from 5927/3): <a href="http://paste.debian.net/104306">http://paste.debian.net/104306</a></li> + <li>with coreboot+vgarom: <a href="http://paste.debian.net/104309">http://paste.debian.net/104309</a></li> + </ul> + </li> + <li> + Trisquel 6. kernel 3.2.0-60 (from Trisquel repositories): + <ul> + <li>with coreboot (no vbios or native init): <a href="http://paste.debian.net/104341">http://paste.debian.net/104341</a></li> + </ul> + </li> + </ul> + + <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="x60_cb5927_testing">i945/X60: Coreboot 5927 testing (3D fix for kernel 3.12+ on replay code)</h1> + + <p><b>The latest version as-is (5927/11) has not been tested by me yet. Always boot with 'drm.debug=0x06' kernel parameter when testing this.</b></p> + + <p> + This is the fix for 3D on kernel 3.12 and higher on i945 (ThinkPad X60 in this case). This is for the replay code. + Libreboot 5th release has a version of this backported already (based on 5927/3 using the '7c0000' hack). + </p> + + <p> + <b> + The replay code is obsolete (see 5320 changeset on review.coreboot.org for better version + which supports more machines/screens, and then 5345 for T60). Information here for reference since that is where the fix was first applied. + </b> + </p> + + <p> + Read the information on <a href="http://review.coreboot.org/#/c/5927/">http://review.coreboot.org/#/c/5927/</a>. + </p> + + <p> + For historical purposes, here is a collection of IRC logs that once existed on this page, related to the issue: + <a href="dumps/kernel312_irc">kernel312_irc</a>. + </p> + + <p> + PGETBL_CTL differs between VBIOS (-) and native graphics init (+).<br/> + + - PGETBL_CTL: 0x3ffc0001<br/> + + PGETBL_CTL: 0x3f800001 + </p> + + <p>GTT (graphics translation table) size is PGETBL_save, max 256 KiB. BSM (Base of Stolen Memory) is given by the bios.</p> + + <ul> + <li>5927/7: <a href="dumps/5927_7.tar.gz">5927_7.tar.gz</a> (GRUB graphics are correct now, and 3D still works)</li> + <li>5927/6: <a href="dumps/5927_6.tar.gz">5927_6.tar.gz</a> (GRUB graphics still corrupt, 3D/everything still works after GRUB)</li> + <li>5927/5: <a href="dumps/5927_5.tar.gz">5927_5.tar.gz</a> (GRUB graphics corrupt, 3D/everything still works after GRUB)</li> + <li>5927/3: <a href="dumps/5927_3.tar.gz">5927_3.tar.gz</a> (3D still works! kernel 3.14.4) - the '7c0000' hack</li> + <li>5927/2: <a href="dumps/5927_2.tar.gz">5927_2.tar.gz</a> (3D works! kernel 3.14.4) - the '7c0000' hack</li> + <li> + 5927/1 (didn't fix the 3D issue): + <ul> + <li><a href="dumps/5927_cbmemc">cbmem -c</a></li> + <li><a href="dumps/5927_crashdump">/sys/class/drm/card0/error</a></li> + <li><a href="dumps/5927_config">.config</a></li> + </ul> + </li> + </ul> + + <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="i945_vbt">i945 gfx: X60/T60 VBT implementation (experimental: testing)</h1> + <p> + <b>Use 'drm.debug=0x06' kernel parameter when booting in grub! Make sure to use kernel 3.14.4 as before (or any recent kernel).</b> + </p> + <p> + Before each test run, boot a live USB and delete the old logs in /var/log (kernel log, xorg log, dmesg and so on). + </p> + <p> + Use latest 5927/5320/5345 on X60/T60 (with GTT/3D/kernel3.12 fix) with native graphics initialization. + Load (from the ROM) the runningvga.bin for each LCD panel on each machine; do not execute it, only load it! + Rename the ROM appropriately, based on the machine name and the panel name. coreboot_nativegfx_5868_plusrunningvga_t60_14_LTD141ECMB.rom, + for instance. Keep a copy for later use. + </p> + + <p>It is (theoretically) supposed to:</p> + <ul> + <li>Enable kernel to see VBT tables so that it can see the panel. (theoretically this will make T60 15" XGA/1024x768 work)</li> + </ul> + <p>You are supposed to:</p> + <ul> + <li>enable native graphics in menuconfig</li> + <li>include the self-modified VGA ROM (load, but not execute) - for reverse engineering the correct VBT tables.</li> + </ul> + + <p> + With each boot, make notes about what you see and get logs using the <a href="#standard_test">standard test</a>. + You will need the files from <a href="#intelvbttool_results">#intelvbttool_results</a> for each machine. + </p> + + Results (# means untested): + <ul> + <li> + <b>X60/X60s:</b> + <ul> + <li>TMD-Toshiba LTD121ECHB: #</li> + <li>CMO N121X5-L06: #</li> + <li>Samsung LTN121XJ-L07: #</li> + <li>BOE-Hydis HT121X01-101: #</li> + </ul> + </li> + <li> + <b>X60T XGA:</b> + <ul> + <li>BOE-Hydis HV121X03-100: #</li> + </ul> + </li> + <li> + <b>X60T SXGA+:</b> + <ul> + <li>BOE-Hydis HV121P01-100: #</li> + </ul> + </li> + <li> + <b>T60 14" XGA:</b> + <ul> + <li>Samsung LTN141XA-L01: #</li> + <li>CMO N141XC: #</li> + <li>BOE-Hydis HT14X14: #</li> + <li>TMD-Toshiba LTD141ECMB: #</li> + </ul> + </li> + <li> + <b>T60 14" SXGA+</b> + <ul> + <li>TMD-Toshiba LTD141EN9B: #</li> + <li>Samsung LTN141P4-L02: #</li> + <li>Boe-Hydis HT14P12: #</li> + </ul> + </li> + <li> + <b>T60 15" XGA</b> + <ul> + <li>Samsung LTN150XG-L08: #</li> + <li>LG-Philips LP150X09: #</li> + <li>13N7068 (IDtech): #</li> + <li>13N7069 (CMO): #</li> + + </ul> + </li> + <li> + <b>T60 15" SXGA+</b> + <ul> + <li>LG-Philips LP150E05-A2K1: #</li> + <li>BOE-Hydis HV150P01-100: #</li> + </ul> + </li> + <li> + <b>T60 15" UXGA</b> + <ul> + <li>BOE-Hydis HV150UX1-100: #</li> + <li>IDTech N150U3-L01: #</li> + <li>BOE-Hydis HV150UX1-102: #</li> + </ul> + </li> + <li> + <b>T50 15" QXGA</b> + <ul> + <li>IDtech IAQX10N: #</li> + <li>IDtech IAQX10S: #</li> + </ul> + </li> + </ul> + + <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="intelvbttool_results">intelvbttool test results (VGA ROM's)</h1> + <p> + The VBIOS on i945 (intel gpu) platforms is self-modifying; that is, + it's contents change when you run it. intelvbttool takes a dump of + the currently running vbios, and parses it. + </p> + + <p> + The idea is that we can extract the VBT tables using this knowledge, on the X60, X60 Tablet and T60 (Intel GPU). + </p> + + <p> + Here is an example of how VBT was implemented on the ThinkPad X230: + <a href="http://review.coreboot.org/#/c/5396" target="_blank">http://review.coreboot.org/#/c/5396</a>. + </p> + + <p> + Use this kernel: + <a href="http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_2_i386.deb">http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_2_i386.deb</a> + </p> + + <p> + You'll need to build a T60 ROM with SeaBIOS and the VGA ROM (for Intel GPU). An X60 ROM is also needed (same configuration, using the VGA ROM for X60). + </p> + + <p> + T60 has DVI on it's dock, make sure that the dock is attached when getting this output. + </p> + + <p> + Get intelvbttool here: <a href="http://review.coreboot.org/#/c/5842">http://review.coreboot.org/#/c/5842</a> (util/intelvbttool). + </p> + + <p> + Now dump a copy of the running VGA BIOS: + <b>$ sudo dd if=/dev/mem bs=64k of=runningvga.bin skip=12 count=1</b><br/> + Then do (and record the output):<br/> + <b>$ ./intelvbttool runningvga.bin > intelvbttool_out</b> + </p> + + <p> + Backup both files (runningvga.bin and intelvbttool_out), renaming them to match the machine and LCD panel used. + <a href="../index.html#get_edid_panelname">../index.html#get_edid_panelname</a> will show you how to get the name (model) of the LCD panel used. + </p> + + <h2>Test results (# means untested and all had docks, unless noted).</h2> + + <ul> + <li> + <b>X60/X60s:</b> + <ul> + <li>TMD-Toshiba LTD121ECHB: #</li> + <li>CMO N121X5-L06: #</li> + <li>Samsung LTN121XJ-L07: #</li> + <li>BOE-Hydis HT121X01-101: #</li> + </ul> + </li> + <li> + <b>X60T XGA (1024x768):</b> + <ul> + <li>BOE-Hydis HV121X03-100: #</li> + </ul> + </li> + <li> + <b>X60T SXGA+ (1400x1050):</b> + <ul> + <li>BOE-Hydis HV121P01-100: #</li> + </ul> + </li> + <li> + <b>T60 14" XGA (1024x768):</b> + <ul> + <li>Samsung LTN141XA-L01: #</li> + <li>CMO N141XC: #</li> + <li>BOE-Hydis HT14X14: #</li> + <li>TMD-Toshiba LTD141ECMB: #</li> + </ul> + </li> + <li> + <b>T60 14" SXGA+ (1400x1050):</b> + <ul> + <li>TMD-Toshiba LTD141EN9B: #</li> + <li>Samsung LTN141P4-L02: #</li> + <li>Boe-Hydis HT14P12: #</li> + </ul> + </li> + <li> + <b>T60 15" XGA (1024x768):</b> + <ul> + <li>Samsung LTN150XG-L08: #</li> + <li>LG-Philips LP150X09: #</li> + <li>13N7068 (IDtech): #</li> + <li>13N7069 (CMO): #</li> + </ul> + </li> + <li> + <b>T60 15" SXGA+ (1400x1050):</b> + <ul> + <li>LG-Philips LP150E05-A2K1: #</li> + <li>BOE-Hydis HV150P01-100: #</li> + </ul> + </li> + <li> + <b>T60 15" UXGA (1600x1200):</b> + <ul> + <li>BOE-Hydis HV150UX1-100: #</li> + <li>IDTech N150U3-L01: #</li> + <li>BOE-Hydis HV150UX1-102: #</li> + </ul> + </li> + <li> + <b>T60 15" QXGA (2048x1536):</b> + <ul> + <li>IDtech IAQX10N: #</li> + <li>IDtech IAQX10S: #</li> + </ul> + </li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="cpu_cstates_buzzing">Buzzing / static noise when not using idle=halt or processor.max_cstate=2 in GRUB</h1> + + <p> + When idle, the X60 and T60 make a high pitched whining sound. With a recorder, find out where it originates from. + 'processor.max_cstate=2' or 'idle=halt' kernel parameters can be used in GRUB to remove it. + Alternatively (and for better battery life), another method is to use 'powertop' (see docs/index.html in libreboot release + archives). + </p> + + <p> + funfunctor in IRC says: <i>"sounds like the gain is set to high, AGC of a ADC is not setup correctl probably"</i>. + </p> + <p> + damo22 in IRC says: <i>"damo22: it seems like the T60 (happens on X60 aswell) does not + support certain cpu C-states but is being forced to use them and this causes a noise. i believe it's because + it doesnt let the cpu go into low power state."</i>. + </p> + <p> + CareBear\ in IRC says: <i>"it has to do with the CPU and chipset switching power states differently with coreboot than with the factory BIOS and as a result the power supply circuitry on the mainboard emits that noise. the whine is quite clearly directly related to the CPU switching between power states + "</i> + </p> + + <p> + Another comment (mailing list):<br/> + If this noise doesn't occur with + the vendor firmware, has anybody checked if coreboot uses the same + power management timing settings? (e.g. C4-TIMING_CNT, see [1], there + might be more such settings not mentioned in the public datasheet) <br/> + <b>[1] Intel I/O Controller Hub 7 (ICH7) Family Datasheet Document Number: 307013-003 </b> + </p> + + <p> + + </p> + + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="battery_eventc">Battery 'event c' on X60 (and T60?)</h1> + <p> + Look into this later. This isn't necessarily a bug, just a part of the code which someone noticed that seems odd. + </p> + <p> + funfuctor: fchmmr: what is 'eventc' exactly in the devicetree of your board? Is that meant to be programed sequentially somehow?<br/> + fchmmr: looks like something with EC<br/> + fchmmr: src/ec/lenovo/h8/chip.h: u8 eventc_enable;<br/> + fchmmr: src/ec/lenovo/h8/h8.c: ec_write(0x1c, conf->eventc_enable);<br/> + funfuctor: fchmmr: yes, better ask phcoder-screen why eventc is defined twice<br/> + funfuctor: and which value is correct<br/> + fchmmr: looks like 0x3c is incorrect<br/> + fchmmr: just a guess<br/> + fchmmr: in devicetree.cb it goes event2 then 3 4 5 6 7 c 8 9 then a b c d<br/> + fchmmr: but i don't know what 'event c' is<br/> + funfuctor: fchmmr: interesting, well in that case you could prob figure it out yourself..<br/> + funfuctor: fchmmr: the order should not matter. basically devicetree is syntax for fill in a C struct<br/> + funfuctor: fchmmr: look closely at build/mainboard/lenovo/t60/static.c<br/> + fchmmr: funfunctor: it was sven schnelle who wrote that (I used 'git blame')<br/> + fchmmr: I think "eventc" has something to do with battery<br/> + fchmmr: commit 95ebe66f7f5fef64d363cb48e5a441ad505353d1<br/> + fchmmr: Author: Sven Schnelle <svens@stackframe.org><br/> + fchmmr: Date: Thu Apr 28 09:29:06 2011 +0000<br/> + fchmmr: that's the commit that added those lines.<br/> + fchmmr: funfunctor:<br/> + fchmmr: "" // C: OEM information<br/> + fchmmr: src/ec/lenovo/h8/acpi/battery.asl<br/> + funfuctor: fchmmr: i'll leave you with the issue of fixing the devicetree duplicate value<br/> + funfuctor: fchmmr: you need to read the datasheet to figure out what register 0x3C is<br/> + funfuctor: sorry *0x1C rather<br/> + funfuctor: grep eventc src/ec/lenovo/h8/h8.c<br/> + funfuctor: ec_write(0x1c, conf->eventc_enable);<br/> + Also look in src/ec/lenovo/h8/h8.c and src/ec/lenovo/h8/chip.h and src/mainboard/lenovo/x60/devicetree.cb<br/> + Do a 'git blame' and a 'git log path/to/file' etc. ask sven, even. + </p> + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="unlisted">Unlisted Notes</h1> + <p> + funfunctor: shadow compiling means you run both compilers (context: GCC and Clang/LLVM) at the same time. If one compiler misses a problem the other compiler hopefully finds it<br/> + funfunctor: fchmmr: blow your mind (compiler security and reprodicible builds) - http://scienceblogs.com/goodmath/2007/04/15/strange-loops-dennis-ritchie-a/ + </p> + <p> + <a href="#pagetop">Back to top of page.</a> + </p> + + <p> + Copyright © 2014 Francis Rowe, All Rights Reserved.<br/> + See <a href="../license.html">../license.html</a> for license conditions. + </p> + +</body> +</html> diff --git a/docs/howtos/x60_security.html b/docs/howtos/x60_security.html index fc9cb0b..fc631bf 100644 --- a/docs/howtos/x60_security.html +++ b/docs/howtos/x60_security.html @@ -44,6 +44,35 @@ <li>none (at least in the scope of the article as-is)</li> </ul> + <h1> + Rationale + </h1> + <p> + Most people think of security on the software side: the hardware is important aswell. + Hardware security is useful in particular to journalists (or activists in a given movement) who need absolute privacy in their work. + It is also generally useful to all those that believe security and privacy are inalienable rights. + Security starts with the hardware; crypto and network security come later. + </p> + <p> + Paradoxically, going this far to increase your security also makes you a bigger target. + At the same time, it protects you in the case that someone does attack your machine. + This paradox only exists while few people take adequate steps to protect yourself: it is your <b>duty</b> + to protect yourself, not only for your benefit but to make strong security <i>normal</i> so + that those who do need protection (and claim it) are a smaller target against the masses. + </p> + <p> + Even if there are levels of security beyond your ability (technically, financially and so on) + doing at least <i>something</i> (what you are able to do) is extremely important. + If you use the internet and your computer without protection, attacking you is cheap (some say it is + only a few US cents). If everyone (majority of people) use strong security by default, + it makes attacks more costly and time consuming; in effect, making them disappear. + </p> + <p> + This tutorial deals with reducing the number of devices that have direct memory access that + could communicate with inputs/outputs that could be used to remotely + command the machine (or leak data). + </p> + <h1 id="procedure">Disassembly</h1> <p> @@ -58,7 +87,7 @@ If your model was WWAN, remove the simcard (check anyway):<br/> Uncover those 2 screws at the bottom:<br/> <img src="x60_security/0000_simcard0.jpg" alt="" /><br/> - SIM card is in the marked location:<br/> + SIM card (not present in the picture) is in the marked location:<br/> <img src="x60_security/0000_simcard1.jpg" alt="" /><br/> Replacement: USB dongle. </p> @@ -99,9 +128,12 @@ <p> Remove the microphone (can desolder it, but you can also easily pull it off with you hands). Already removed here:<br/> <img src="x60_security/0001_microphone.jpg" alt="" /><br/> - We do not know what the built-in microcode (on the CPU) is doing. The theory is that it could be programmed to take commands that do something - and then the CPU returns results. (meaning, remote security hole). So we remove it, just in case.<br/> - Replacement: external microphone on USB or line-in jack. + <b>Rationale:</b><br/> + Another reason to remove the microphone: If your computer gets<a href="#ref1">[1]</a> compromised, it can + record what you say, and use it to receive data from nearby devices if + they're compromised too. Also, we do not know what the built-in microcode (in the CPU) is doing; it could theoretically + be programmed to accept remote commands from some speaker somewhere (remote security hole). <b>In other words, + the machine could already be compromised from the factory.</b> </p> <p> @@ -114,13 +146,25 @@ Remove the speaker:<br/> <img src="x60_security/0001_speaker.jpg" alt="" /><br/> Reason: combined with the microphone issue, this could be used to leak data.<br/> + If your computer gets<a href="#ref1">[1]</a> compromised, it can be used to + transmit data to nearby compromised devices. It's unknown if it can be + turned into a microphone<a href="#ref2">[2]</a>.<br/> Replacement: headphones/speakers (line-out) or external DAC (USB). </p> <p> Remove the wlan (also remove wwan if you have it):<br/> <img src="x60_security/0001_wlan_wwan.jpg" alt="" /><br/> - Reason: has direct (and very fast) memory access, and could (theoretically) leak data over a side-channel. + Reason: has direct (and very fast) memory access, and could (theoretically) leak data over a side-channel.<br/> + <b>Wifi:</b> The ath5k/ath9k cards might not have firmware at all. They might safe but could have + access to the computer's RAM trough DMA. If people have an intel + card(most X60's come with Intel wifi by default, until you change it),then that card runs + a non-free firwamre and has access to the computer's RAM trough DMA! So + it's risk-level is very high.<br/> + <b>Wwan (3d modem):</b> They run proprietary software and have access to the + computer's RAM! So it's like AMT but over the GSM network which is + probably even worse.<br/> + Replacement: external USB wifi dongle. (or USB wwan/3g dongle; note, this has all the same privacy issues as mobile phones. wwan not recommended). </p> <h2> @@ -139,7 +183,7 @@ or directly to the video: <a href="http://mirror.netcologne.de/CCC/congress/2013/webm/30c3-5529-en-Hardening_hardware_and_choosing_a_goodBIOS_webm.webm">http://mirror.netcologne.de/CCC/congress/2013/webm/30c3-5529-en-Hardening_hardware_and_choosing_a_goodBIOS_webm.webm</a>. </p> <p> - A lot of this tutorial is based on that video. Look towards the second half of the video to see how to do the abev. + A lot of this tutorial is based on that video. Look towards the second half of the video to see how to do the above. </p> <h2> @@ -158,8 +202,69 @@ <li> General tips/advice and web links showing how to detect physical intrusions. </li> + <li> + For example: <a href="http://cs.tau.ac.il/~tromer/acoustic/">http://cs.tau.ac.il/~tromer/acoustic/</a> + </li> + </ul> + + <h1> + Extra notes + </h1> + <p> + EC: Cannot be removed but can be mitigated: it contains non-free + non-loadable code, but it has no access to the computer's RAM. + It has access to the on-switch of the wifi, bluetooth, modem and some + other power management features. The issue is that it has access to the + keyboard, however if the software security howto <b>(not yet written)</b> is followed correctly, + it won't be able to leak data to a local attacker. It has no network + access but it may still be able to leak data remotely, but that + requires someone to be nearby to recover the data with the help of an + SDR and some directional antennas<a href="#ref3">[3]</a>. + </p> + + <h2> + Risk level + </h2> + <ul> + <li>Modem: highest</li> + <li>Intel wifi: Near highest</li> + <li>Atheros PCI wifi: unknown, but lower than intel wifi.</li> + <li>Microphone: only problematic if the computer gets compromised.</li> + <li>Speakers: only problematic if the computer gets compromised.</li> + <li>EC: can be mitigated if following the <b>(not yet written)</b> guide on software security.</li> </ul> + <h1> + References + </h1> + <h2 id="ref1">[1] physical access</h2> + <p> + Explain that black hats, TAO, and so on might use a 0day to get in, + and explain that in this case it mitigates what the attacker can do. + Also the TAO do some evaluation before launching an attack: they take + the probability of beeing caught into account, along with the kind of + target. A 0day costs a lot of money, I heard that it was from 100000$ + to 400000$, some other websites had prices 10 times lower but that + but it was probably a typo. So if people increase their security it + makes it more risky and more costly to attack people. + </p> + <h2 id="ref2">[2] microphone</h2> + <p> + It's possible to turn headphones into a microphone, you could try + yourself, however they don't record loud at all. Also intel cards have + the capability to change a connector's function, for instance the + microphone jack can now become a headphone plug, that's called + retasking. There is some support for it in GNU/Linux but it's not very + well known. + </p> + <h2 id="ref3">[3] Video (CCC)</h2> + <p> + 30c3-5356-en-Firmware_Fat_Camp_webm.webm from the 30th CCC. While + their demo is experimental(their hardware also got damaged during the + transport), the spies probably already have that since a long time. + <a href="http://berlin.ftp.media.ccc.de/congress/2013/webm/30c3-5356-en-Firmware_Fat_Camp_webm.webm">http://berlin.ftp.media.ccc.de/congress/2013/webm/30c3-5356-en-Firmware_Fat_Camp_webm.webm</a> + </p> + <hr/> <p> diff --git a/docs/index.html b/docs/index.html index 37fdd38..43d90d8 100644 --- a/docs/index.html +++ b/docs/index.html @@ -32,6 +32,15 @@ <aside>The latest release (along with documentation) can be found at <a href="http://libreboot.org/">libreboot.org</a></aside> </header> + <p> + It is assumed that you are running GNU/Linux. No other operating system is known to be compatible (with libreboot) for this release. + </p> + + <p> + The information here is user documentation mainly. For development notes and TODO's, see <a href="RELEASE.html">RELEASE.html</a> and + <a href="future/index.html">future/index.html</a> + </p> + <h2>GNU/Linux distributions</h2> <ul> <li><a href="howtos/grub_boot_installer.html">How to install a GNU/Linux distribution</a></li> @@ -41,7 +50,7 @@ <h2>Working with source code</h2> <ul> <li><a href="#build_meta">Building libreboot_src from libreboot_meta</a></li> - <li><a href="#build_bucts">How to build "bucts" (for LenovoBIOS X60/T60)</a></li> + <li><a href="#build_bucts">How to build "bucts" (for LenovoBIOS X60/X60S/X60T/T60)</a></li> <li><a href="#build_flashrom">How to build "flashrom"</a></li> <li> <a href="#config">Configuring libreboot</a> @@ -58,11 +67,13 @@ <h2>Hardware maintenance</h2> <ul> + <li><a href="#supported_x60_list">List of supported ThinkPad X60's</a></li> + <li><a href="#supported_x60t_list">List of supported ThinkPad X60 Tablets</a></li> <li><a href="#supported_t60_list">List of supported ThinkPad T60's</a></li> <li><a href="#t60_inverter">Inverter boards for ThinkPad T60 when upgrading the LCD panel.</a></li> <li><a href="#t60_ati_intel">ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences.</a></li> - <li><a href="howtos/x60_heatsink.html">ThinkPad X60: change the fan/heatsink</a></li> - <li><a href="howtos/x60_security.html">ThinkPad X60: security</a></li> + <li><a href="howtos/x60_heatsink.html">ThinkPad X60/X60S: change the fan/heatsink</a></li> + <li><a href="howtos/x60_security.html">ThinkPad X60/X60S: security</a></li> </ul> <h2>Macbook2,1</h2> @@ -73,13 +84,14 @@ <h2>Installing libreboot (software: using internal programmer)</h2> <ul> <li><a href="#rom">Recommended ROM's to flash</a></li> - <li><a href="#flashrom_lenovobios">X60/T60: How to flash your ROM (if running Lenovo BIOS)</a></li> - <li><a href="#flashrom">X60/T60: How to flash your ROM (if running libreboot or coreboot already)</a></li> + <li><a href="#flashrom_lenovobios">X60/X60S/X60T/T60: How to flash your ROM (if running Lenovo BIOS firmware)</a></li> + <li><a href="#flashrom_macbook21">macbook21: How to flash your ROM (if running Apple EFI firmware)</a></li> + <li><a href="#flashrom">X60/X60S/X60T/T60/macbook21: How to flash your ROM (if running libreboot or coreboot already)</a></li> </ul> <h2>Installing libreboot (hardware: using external programmer)</h2> <ul> - <li><a href="howtos/x60_unbrick.html">ThinkPad X60: How to unbrick</a></li> + <li><a href="howtos/x60_unbrick.html">ThinkPad X60/X60S: How to unbrick</a></li> </ul> <h2>GRUB2 payload</h2> @@ -94,7 +106,8 @@ <li><a href="#keyboards_usqwerty">QWERTY (United States)</a></li> <li><a href="#keyboards_ukdvorak">Dvorak (United Kingdom)</a></li> <li><a href="#keyboards_usdvorak">Dvorak (United States)</a></li> - <li><a href="#keyboards_frazerty">AZERTY (French)</a></li> + <li><a href="#keyboards_frazerty">Azerty (French)</a></li> + <li><a href="#keyboards_itqwerty">QWERTY (Italian)</a></li> </ul> </li> <li><a href="#grub_custom_keyboard">Custom keyboard layout in GRUB</a></li> @@ -102,7 +115,8 @@ <li><a href="#grub_ukqwerty_keyboard">UK Qwerty keyboard layout in GRUB</a></li> <li><a href="#grub_dvorak_keyboard">US Dvorak keyboard layout in GRUB</a></li> <li><a href="#grub_ukdvorak_keyboard">UK Dvorak keyboard layout in GRUB</a></li> - <li><a href="#grub_frazerty_keyboard">FR AZERTY keyboard layout in GRUB</a></li> + <li><a href="#grub_frazerty_keyboard">French AZERTY keyboard layout in GRUB</a></li> + <li><a href="#grub_itqwerty_keyboard">Italian QWERTY keyboard layout in GRUB</a></li> </ul> </li> </ul> @@ -164,14 +178,14 @@ <hr/> - <h1 id="build_bucts">How to build "bucts" (for LenovoBIOS X60/T60)</h1> + <h1 id="build_bucts">How to build "bucts" (for LenovoBIOS X60/X60S/X60T/T60)</h1> <p> - <b>This is for Lenovo BIOS users on the ThinkPad X60 and T60. If you have coreboot or libreboot running already, ignore this.</b> + <b>This is for Lenovo BIOS users on the ThinkPad X60/X60S, X60 Tablet and T60. If you have coreboot or libreboot running already, ignore this.</b> </p> <p> - Bucts is needed when flashing the X60/T60 ROM while Lenovo BIOS is running. + Bucts is needed when flashing the X60/X60S/X60T/T60 ROM while Lenovo BIOS is running. Each ROM contains identical data inside the two final 64K region in the file. This corresponds to the final two 64K regions in the flash chip. Lenovo BIOS will prevent you from writing the final one, so running "<b>bucts 1</b>" will set the machine to boot from the other block instead (which @@ -488,9 +502,71 @@ <hr/> + <h1 id="supported_x60_list">List of supported ThinkPad X60's</h1> + + <p> + Regarding native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('Video BIOS' or 'VBIOS'), + all known LCD panels are currently compatible: + </p> + <ul> + <li>TMD-Toshiba LTD121ECHB: #</li> + <li>CMO N121X5-L06: #</li> + <li>Samsung LTN121XJ-L07: #</li> + <li>BOE-Hydis HT121X01-101: #</li> + </ul> + + <p> + See <a href="#get_edid_panelname">#get_edid_panelname</a>. + </p> + + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="supported_x60t_list">List of supported ThinkPad X60 Tablets</h1> + + <p> + Regarding native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('Video BIOS' or 'VBIOS'). + </p> + + <p> + The following LCD panels are known to work: + </p> + <ul> + <li> + <b>X60T XGA (1024x768):</b> + <ul> + <li>BOE-Hydis HV121X03-100: #</li> + </ul> + </li> + <li> + <b>X60T SXGA+ (1400x1050):</b> + <ul> + <li>BOE-Hydis HV121P01-100: #</li> + </ul> + </li> + </ul> + + <p> + The following LCD panels are incompatible at the moment. + </p> + <ul> + <li>Samsung LTN121XP01 (<a href="future/index.html#lcd_i945_incompatibility">future/index.html#lcd_i945_incompatibility</a>)</li> + </ul> + + <p> + See <a href="#get_edid_panelname">#get_edid_panelname</a>. + </p> + +<hr/> + <h1 id="supported_t60_list">Supported T60 list</h1> <p> + Regarding native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('Video BIOS' or 'VBIOS'). + </p> + + <p> T60 15.4" (1280x800 and 1680x1050) with Intel GPU is untested in this release. Not much yet is known about panel names. They will be tested at a later date. </p> @@ -535,30 +611,6 @@ </li> </ul> - <div class="important"> - <p> - A user with 2 T60's, each with a Core 2 Duo T7200 processor tried libreboot on each machine. - One worked, one did not. It should be explained that in addition to the microcode (on the CPU), - updates are usually supplied in coreboot (from Intel) which patch the onboard microcode to fix bugs. - Errata's can be found at <a href="http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf">http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf</a> - and <a href="http://download.intel.com/design/mobile/SPECUPDT/31407918.pdf">http://download.intel.com/design/mobile/SPECUPDT/31407918.pdf</a>. - These microcode updates are not included in libreboot because they are proprietary (blobs). Most CPU's work fine without them: hundreds - of Core Duo T2300/T2400/T2500/L2300/L2400/L2500 processors have been tested on the X60, and a few T5600 CPU's have been tested on the T60 (and X60 and all work). - In the case of the T7200, it was found that one of the two tested had instability issues (kernel panics) without the updates: work is being done to find out - exactly what version of the microcode that particular CPU had in this case. - If you find that your CPU gives you similar issues (after trying libreboot), the current workaround is to simply try another CPU - (fortunately, the CPU's in the T60 are installed in a socket so replacing them is easy). - </p> - <p> - There might be a patched kernel that can be used, or a kernel parameter that can be used in GRUB to work around these (rare) buggy CPU's - (it is unknown at the moment whether this is possible). - The Core 2 Duo T7600 is untested, but will be tested soon (the lead developer of libreboot project has 3 of them to try out). - </p> - <p> - If reading this for 2nd beta, note that any debugging obtained so far will be included in the 3rd beta. - </p> - </div> - <p> To find what LCD panel you have, see: <a href="#get_edid_panelname">#get_edid_panelname</a>. </p> @@ -577,7 +629,7 @@ <li> Tested panels: <ul> - <li>Not working: Samsung LTN141XA-L01</li> + <li>Not working: Samsung LTN141XA-L01 (<a href="future/index.html#lcd_i945_incompatibility">future/index.html#lcd_i945_incompatibility</a>)</li> </ul> </li> <li> @@ -639,7 +691,7 @@ <li> Tested panels: <ul> - <li>Not working: LG-Philips LP150X09</li> + <li>Not working: LG-Philips LP150X09 (<a href="future/index.html#lcd_i945_incompatibility">future/index.html#lcd_i945_incompatibility</a>)</li> </ul> </li> <li> @@ -881,6 +933,13 @@ <ul> <li><a href="#">Parabola GNU/Linux installation on a macbook2,1 with Apple EFI firmware</a> (this is a copy of Mono's page, see above)</li> </ul> + <p> + How to boot an ISO: burn it to a CD (like you would normally) and hold down the Alt/Control key while booting. + The bootloader will detect the GNU/Linux CD as 'Windows' (because Apple doesn't think GNU/Linux exists). Install it like you normally would. + When you boot up again, hold Alt/Control once more. The installation (on the HDD) will once again be seen as 'Windows'. (it's not actually Windows, + but Apple likes to think that Apple and Microsoft are all that exist.) + Now to install libreboot, follow <a href="#flashrom_macbook21">#flashrom_macbook21</a>. + </p> <h2> Information about coreboot @@ -921,6 +980,12 @@ Also of interest: <a href="#config_macbook21">#config_macbook21</a>. </p> + <p> + <b> + The MacBook2,1 comes with a webcam, which does not work without proprietary software. Also, webcams are a security risk; cover it up! Or remove it. + </b> + </p> + <p><a href="#pagetop">Back to top of page.</a></p> <hr/> @@ -933,45 +998,51 @@ ThinkPad X60, X60s (<b>bin/x60/</b>) <ul> <li>US Qwerty keyboard, no dock: <b>libreboot_usqwerty.rom</b></li> - <li>UK Qwerty keyboard, no dock: <b>libreboot_ukqwerty.rom</b></li> - <li>US Dvorak keyboard, no dock: <b>libreboot_usdvorak.rom</b></li> - <li>UK Dvorak keyboard, no dock: <b>libreboot_ukdvorak.rom</b></li> - <li>FR Azerty keyboard, no dock: <b>libreboot_frazerty.rom</b></li> <li>US Qwerty keyboard, with dock: <b>libreboot_serial_usqwerty.rom</b></li> + <li>UK Qwerty keyboard, no dock: <b>libreboot_ukqwerty.rom</b></li> <li>UK Qwerty keyboard, with dock: <b>libreboot_serial_ukqwerty.rom</b></li> + <li>US Dvorak keyboard, no dock: <b>libreboot_usdvorak.rom</b></li> <li>US Dvorak keyboard, with dock: <b>libreboot_serial_usdvorak.rom</b></li> + <li>UK Dvorak keyboard, no dock: <b>libreboot_ukdvorak.rom</b></li> <li>UK Dvorak keyboard, with dock: <b>libreboot_serial_ukdvorak.rom</b></li> - <li>FR Azerty keyboard, with dock: <b>libreboot_serial_frazerty.rom</b></li> + <li>French Azerty keyboard, no dock: <b>libreboot_frazerty.rom</b></li> + <li>French Azerty keyboard, with dock: <b>libreboot_serial_frazerty.rom</b></li> + <li>Italian Qwerty keyboard, no dock: <b>libreboot_itqwerty.rom</b></li> + <li>Italian Qwerty keyboard, with dock: <b>libreboot_serial_itqwerty.rom</b></li> </ul> </li> <li> ThinkPad X60 Tablet (<b>bin/x60t/</b>) <ul> <li>US Qwerty keyboard, no dock: <b>libreboot_usqwerty.rom</b></li> - <li>UK Qwerty keyboard, no dock: <b>libreboot_ukqwerty.rom</b></li> - <li>US Dvorak keyboard, no dock: <b>libreboot_usdvorak.rom</b></li> - <li>UK Dvorak keyboard, no dock: <b>libreboot_ukdvorak.rom</b></li> - <li>FR Azerty keyboard, no dock: <b>libreboot_frazerty.rom</b></li> <li>US Qwerty keyboard, with dock: <b>libreboot_serial_usqwerty.rom</b></li> + <li>UK Qwerty keyboard, no dock: <b>libreboot_ukqwerty.rom</b></li> <li>UK Qwerty keyboard, with dock: <b>libreboot_serial_ukqwerty.rom</b></li> + <li>US Dvorak keyboard, no dock: <b>libreboot_usdvorak.rom</b></li> <li>US Dvorak keyboard, with dock: <b>libreboot_serial_usdvorak.rom</b></li> + <li>UK Dvorak keyboard, no dock: <b>libreboot_ukdvorak.rom</b></li> <li>UK Dvorak keyboard, with dock: <b>libreboot_serial_ukdvorak.rom</b></li> - <li>FR Azerty keyboard, with dock: <b>libreboot_serial_frazerty.rom</b></li> + <li>French Azerty keyboard, no dock: <b>libreboot_frazerty.rom</b></li> + <li>French Azerty keyboard, with dock: <b>libreboot_serial_frazerty.rom</b></li> + <li>Italian Qwerty keyboard, no dock: <b>libreboot_itqwerty.rom</b></li> + <li>Italian Qwerty keyboard, with dock: <b>libreboot_serial_itqwerty.rom</b></li> </ul> </li> <li> ThinkPad T60 (<b>bin/t60/</b>) (note, see <a href="#supported_t60_list">#supported_t60_list</a>) <ul> <li>US Qwerty keyboard, no dock: <b>libreboot_usqwerty.rom</b></li> - <li>UK Qwerty keyboard, no dock: <b>libreboot_ukqwerty.rom</b></li> - <li>US Dvorak keyboard, no dock: <b>libreboot_usdvorak.rom</b></li> - <li>UK Dvorak keyboard, no dock: <b>libreboot_ukdvorak.rom</b></li> - <li>FR Azerty keyboard, no dock: <b>libreboot_frazerty.rom</b></li> <li>US Qwerty keyboard, with dock: <b>libreboot_serial_usqwerty.rom</b></li> + <li>UK Qwerty keyboard, no dock: <b>libreboot_ukqwerty.rom</b></li> <li>UK Qwerty keyboard, with dock: <b>libreboot_serial_ukqwerty.rom</b></li> + <li>US Dvorak keyboard, no dock: <b>libreboot_usdvorak.rom</b></li> <li>US Dvorak keyboard, with dock: <b>libreboot_serial_usdvorak.rom</b></li> + <li>UK Dvorak keyboard, no dock: <b>libreboot_ukdvorak.rom</b></li> <li>UK Dvorak keyboard, with dock: <b>libreboot_serial_ukdvorak.rom</b></li> - <li>FR Azerty keyboard, with dock: <b>libreboot_serial_frazerty.rom</b></li> + <li>French Azerty keyboard, no dock: <b>libreboot_frazerty.rom</b></li> + <li>French Azerty keyboard, with dock: <b>libreboot_serial_frazerty.rom</b></li> + <li>Italian Qwerty keyboard, no dock: <b>libreboot_itqwerty.rom</b></li> + <li>Italian Qwerty keyboard, with dock: <b>libreboot_serial_itqwerty.rom</b></li> </ul> </li> <li> @@ -981,7 +1052,8 @@ <li>UK Qwerty keyboard: <b>libreboot_ukqwerty.rom</b></li> <li>US Dvorak keyboard: <b>libreboot_usdvorak.rom</b></li> <li>UK Dvorak keyboard: <b>libreboot_ukdvorak.rom</b></li> - <li>FR Azerty keyboard: <b>libreboot_frazerty.rom</b></li> + <li>French Azerty keyboard: <b>libreboot_frazerty.rom</b></li> + <li>Italian Qwerty keyboard: <b>libreboot_itqwerty.rom</b></li> <li>The MacBook2,1 uses the same chipset, i945, as the X60/X60s X60T and T60 but there is no dock or serial port available for this machine.</li> </ul> </li> @@ -1000,7 +1072,7 @@ <hr/> - <h1 id="flashrom_lenovobios">X60/T60: How to flash the ROM's onto your machine (if running Lenovo BIOS).</h1> + <h1 id="flashrom_lenovobios">X60/X60S/X60T/T60: How to flash the ROM's onto your machine (if running Lenovo BIOS firmware).</h1> <div class="important"> @@ -1107,20 +1179,41 @@ <hr/> - <h1 id="flashrom">X60/T60: How to flash the ROM's onto your machine (if running libreboot or coreboot already)</h1> + <h1 id="flashrom_macbook21">macbook21: How to flash your ROM (if running Apple EFI firmware)</h1> + + <div class="important"> + + <p> + Hover over the next paragraph to make it black. + </p> + <p class="lenovobios"> + Following this guide means simply flashing a libreboot ROM. This guide will not (directly) teach you how to make a backup (dump) of the original Apple EFI firmware + because to do so would be to explicitly endorse proprietary software. However, for the purposes of reverse engineering it can be useful + to have a backup. Each copy of the original Apple EFI is (believed, but unproven to be) tied to the specific machine that it came from; it will not (as is believed) run + on any other machine, even if it's the same type of machine as yours. What this means is that, effectively, you can back it up now (so that you can + re-flash it later if you want to run the original Apple EFI firmware again) or lose it forever. The macbook21 installation + guide on the coreboot wiki will show you how to do this: + <a href="http://www.coreboot.org/Board:apple/macbook21">http://www.coreboot.org/Board:apple/macbook21</a>.<br/> + Do not make this decision lightly! This is (very likely) your last and only chance. + </p> + + <p> + (this theory is untested at the time of writing) + </p> + + </div> <p> - <b>These instructions work for both the ThinkPad X60 and T60.</b> - </p> - <p> - <b>This assumes that you already have coreboot or libreboot running</b> - </p> - <p> - <b>If you have Lenovo BIOS running, go to <a href="#flashrom_lenovobios">#flashrom_lenovobios</a> instead.</b> + <b> + This is for the MacBook2,1 while running Apple EFI firmware. If you already have + coreboot or libreboot running, then go to <a href="#flashrom">#flashrom</a> instead! + </b> </p> + <p> - <b>If you are flashing a Lenovo ThinkPad T60, be sure to read <a href="#supported_t60_list">#supported_t60_list</a></b> + Be sure to read the information in <a href="#macbook21">#macbook21</a>. </p> + <p> If you need to recompile flashrom:<br/> <b>See: <a href="#build_flashrom">#build_flashrom</a></b> @@ -1130,31 +1223,108 @@ <b>$ sudo ./builddeb-flashrom</b> </p> <p> - Look at <a href="#rom">#rom</a> to see which ROM is suitable for your machine. Alternative you may be using your own + Look at <a href="#rom">#rom</a> to see which ROM is suitable for your machine. Alternatively you may be using your own custom ROM. Adapt. </p> + <p> - Flash the ROM:<br/> - <b>$ sudo ./flash bin/<a href="#rom">YOURBOARD/YOURROM</a></b> + Flashing is actually easy (compared to X60/T60).<br/> + <b>$ sudo flashrom -p internal:laptop=force_I_want_a_brick -w bin/<a href="#rom">YOURBOARD/YOURROM</a></b> </p> + <p> - You should see <b>"Verifying flash... VERIFIED."</b> written at the end of the flashrom output. <b>SHUT DOWN</b> - after you see this, and then boot up again after a few seconds. + Alternatively, a script is provided which does the same thing:<br/> + <b>$ sudo ./macbook21_firstflash bin/<a href="#rom">YOURBOARD/YOURROM</a></b> </p> + <div class="important"> + + <p> + You should also see within the output the following:<br/> + <b>"Verifying flash... VERIFIED."</b> + </p> + + <p> + If you see that, great! Shut down now (power off). Wait a few seconds and then boot! + </p> + + </div> + + <p><a href="#pagetop">Back to top of page.</a></p> + +<hr/> + + <h1 id="flashrom">X60/X60S/X60T/T60/macbook21: How to flash the ROM's onto your machine (if running libreboot or coreboot already)</h1> + <p> <b> - If you boot and you see nothing, try turning up the backlight (Fn+Home). - If this is a ThinkPad X60 and backlight resets to zero when turning it up while at max, look at <a href="#tft_brightness">#tft_brightness</a>. + These instructions work for the Lenovo ThinkPad X60/X60S/X60T/T60 and Apple MacBook2,1. </b> </p> - <p> <b> - If this is a ThinkPad X60 then you can look at <a href="#x60_wifi">#x60_wifi</a> for how to enable/disable wifi. - You can also look at <a href="#x60_trackpoint">#x60_trackpoint</a> for how to enable/disable the trackpoint (red mouse on keyboard). + This assumes that you already have coreboot or libreboot running. + </b> + </p> + <p> + <b> + If you have Lenovo BIOS running (X60/X60S/X60T/T60), go to <a href="#flashrom_lenovobios">#flashrom_lenovobios</a> instead. + </b> + </p> + <p> + <b> + If you have Apple EFI firmware running (macbook21), go to <a href="#flashrom_macbook21">#flashrom_macbook21</a> instead. + </b> + </p> + <p> + <b> + If you are flashing a Lenovo ThinkPad T60, be sure to read <a href="#supported_t60_list">#supported_t60_list</a>. + </b> + </p> + <p> + <b> + If you are flashing an Apple MacBook2,1, be sure to read the information in <a href="#macbook21">#macbook21</a>. </b> </p> + <p> + If you need to recompile flashrom:<br/> + <b>See: <a href="#build_flashrom">#build_flashrom</a></b> + </p> + <p> + You also need the run-time dependencies. This script works on apt-get distros:<br/> + <b>$ sudo ./builddeb-flashrom</b> + </p> + <p> + Look at <a href="#rom">#rom</a> to see which ROM is suitable for your machine. Alternative you may be using your own + custom ROM. Adapt. + </p> + <p> + Flash the ROM:<br/> + <b>$ sudo ./flash bin/<a href="#rom">YOURBOARD/YOURROM</a></b> + </p> + + <div class="important"> + + <p> + You should see <b>"Verifying flash... VERIFIED."</b> written at the end of the flashrom output. <b>SHUT DOWN</b> + after you see this, and then boot up again after a few seconds. + </p> + + <p> + <b> + If you boot and you see nothing, try turning up the backlight (Fn+Home). + If this is a ThinkPad X60 and backlight resets to zero when turning it up while at max, look at <a href="#tft_brightness">#tft_brightness</a>. + </b> + </p> + + <p> + <b> + If this is a ThinkPad X60 then you can look at <a href="#x60_wifi">#x60_wifi</a> for how to enable/disable wifi. + You can also look at <a href="#x60_trackpoint">#x60_trackpoint</a> for how to enable/disable the trackpoint (red mouse on keyboard). + </b> + </p> + + </div> <p><a href="#pagetop">Back to top of page</a></p> @@ -1222,10 +1392,14 @@ <a href="https://upload.wikimedia.org/wikipedia/commons/thumb/2/25/KB_United_States_Dvorak.svg/800px-KB_United_States_Dvorak.svg.png">https://upload.wikimedia.org/wikipedia/commons/thumb/2/25/KB_United_States_Dvorak.svg/800px-KB_United_States_Dvorak.svg.png</a> </p> - <h3 id="keyboards_azerty">AZERTY (French)</h3> + <h3 id="keyboards_frazerty">AZERTY (French)</h3> <p> <a href="https://upload.wikimedia.org/wikipedia/commons/thumb/b/b9/KB_France.svg/800px-KB_France.svg.png">https://upload.wikimedia.org/wikipedia/commons/thumb/b/b9/KB_France.svg/800px-KB_France.svg.png</a> </p> + <h3 id="keyboards_itqwerty">QWERTY (Italian)</h3> + <p> + <a href="https://upload.wikimedia.org/wikipedia/commons/thumb/e/e5/Italian_Keyboard_layout.svg/799px-Italian_Keyboard_layout.svg.png">https://upload.wikimedia.org/wikipedia/commons/thumb/e/e5/Italian_Keyboard_layout.svg/799px-Italian_Keyboard_layout.svg.png</a> + </p> <p><a href="#pagetop">Back to top of page</a></p> @@ -1260,72 +1434,48 @@ <h2 id="grub_qwerty_keyboard">US Qwerty keyboard layout in GRUB (for reference)</h2> - <p><b>$ cd libreboot_src/grub</b><br/> - compile grub ('build' script has the info on how to do this)<br/> - come back out into libreboot_src<br/> - <b>$ cd ../</b></p> - <p>Generate the layout file:<br/> <b>$ ckbcomp us > usqwerty</b><br/> <b>$ cat usqwerty | ./grub/grub-mklayout -o usqwerty.gkb</b></p> - <p>Note: these files are already included ('build' script also makes use of them). You don't need to do any of this.</p> - <p><a href="#pagetop">Back to top of page</a></p> <h2 id="grub_ukqwerty_keyboard">UK Qwerty keyboard layout in GRUB (for reference)</h2> - <p><b>$ ckbcomp gb > ukqwerty</b><br/> + <p>Generate the layout file:<br/> + <b>$ ckbcomp gb > ukqwerty</b><br/> <b>$ cat ukqwerty | ./grub/grub-mklayout -o ukqwerty.gkb</b></p> - <p>Note: these files are already included ('build' script makes use of them). You don't need to do it.</p> - <p><a href="#pagetop">Back to top of page</a></p> <h2 id="grub_dvorak_keyboard">US Dvorak keyboard layout in GRUB (for reference)</h2> - <p>How the dvorak.gkb was made (for US Dvorak layout in GRUB).</p> - - <p><b>$ cd libreboot_src/grub</b><br/> - compile grub ('build' script has the info on how to do this)<br/> - come back out into libreboot_src:<br/> - <b>$ cd ../</b></p> - <p>Generate the layout file:<br/> <b>$ ckbcomp dvorak > usdvorak</b><br/> - <b>$ cat usdvorak | ./grub/grub-mklayout -o dvorak.gkb</b></p> - - <p>Note: these files are already included ('build' script makes use of them). You don't need to do it.</p> + <b>$ cat usdvorak | ./grub/grub-mklayout -o usdvorak.gkb</b></p> <p><a href="#pagetop">Back to top of page</a></p> <h2 id="grub_ukdvorak_keyboard">UK Dvorak keyboard layout in GRUB (for reference)</h2> - <p>There isn't much difference to US Dvorak.<br/> - <b>$ cp usdvorak ukdvorak</b></p> - - <p>Patch ukdvorak like so (diff usdvorak ukdvorak):<br/> - diff the usdvorak file with ukdvorak to see how it was patched.</p> + <p> + ukdvorak had to be created manually, based on usdvorak. diff them (under resources/grub/keymap/original) + to see how ukdvorak file was created + </p> - <p>Now create ukdvorak.gkb<br/> <b>$ cat ukdvorak | ./grub/grub-mklayout -o ukdvorak.gkb</b></p> - <p>Note: these files are already included ('build' script makes use of them). You don't need to do any of this.</p> - - <h2 id="grub_frazerty_keyboard">FR AZERTY keyboard layout in GRUB (for reference)</h2> - - <p>How the frazerty.gkb was made (for FR AZERTY layout in GRUB).</p> - - <p><b>$ cd libreboot_src/grub</b><br/> - compile grub ('build' script has the info on how to do this)<br/> - come back out into libreboot_src:<br/> - <b>$ cd ../</b></p> + <h2 id="grub_frazerty_keyboard">French AZERTY keyboard layout in GRUB (for reference)</h2> <p>Generate the layout file:<br/> <b>$ ckbcomp fr > frazerty</b><br/> <b>$ cat frazerty | ./grub/grub-mklayout -o frazerty.gkb</b></p> - <p>Note: these files are already included ('build' script makes use of them). You don't need to do it.</p> + <h2 id="grub_itqwerty_keyboard">Italian QWERTY keyboard layout in GRUB (for reference)</h2> + + <p>Generate the layout file:<br/> + <b>$ ckbcomp it > itqwerty</b><br/> + <b>$ cat itqwerty | ./grub/grub-mklayout -o itqwerty.gkb</b></p> <p><a href="#pagetop">Back to top of page</a></p> @@ -1521,11 +1671,20 @@ WantedBy=multi-user.target <pre> Unlisted note: http://inertiawar.com/microcode/ + Read that thread: http://www.coreboot.org/pipermail/coreboot/2014-July/078261.html (link published to coreboot mailing list on July 8, 2014) + Document everything listed in this discussion (and the link) + + SeaVGABIOS+SeaBIOS support for X60/T60: + Read that: http://www.coreboot.org/pipermail/coreboot/2014-July/078342.html This page talks about 'calibration' in powertop: https://docs.fedoraproject.org/en-US/Fedora/15/html/Power_Management_Guide/PowerTOP.html I should think about adapting information here based on that page. + + Look into 'git archive' instead of deleting .git + eg (coreboot directory): + git archive --format=tar --prefix=libreboot/ -o ../libreboot_release.tar HEAD </pre> <hr/> diff --git a/docs/t7200q/cbmemc b/docs/t7200q/cbmemc new file mode 100644 index 0000000..15001ea --- /dev/null +++ b/docs/t7200q/cbmemc @@ -0,0 +1,1448 @@ +
+
+coreboot-4.0-6185-g7f1f3fb-dirty-79ETE7WW (2.27 ) Wed Jul 16 14:03:30 BST 2014 starting...
+
+Mobile Intel(R) 82945GM/GME Express Chipset
+(G)MCH capable of up to FSB 800 MHz
+(G)MCH capable of up to DDR2-667
+Setting up static southbridge registers... GPIOS... done.
+Disabling Watchdog reboot... done.
+Setting up static northbridge registers... done.
+Waiting for MCHBAR to come up...ok
+PM1_CNT: 00001c00
+SMBus controller enabled.
+Setting up RAM controller.
+This mainboard supports Dual Channel Operation.
+DDR II Channel 0 Socket 0: x8DDS
+DDR II Channel 1 Socket 0: x16SS
+Memory will be driven at 667MHz with CAS=5 clocks
+tRAS = 15 cycles
+tRP = 5 cycles
+tRCD = 5 cycles
+Refresh: 7.8us
+tWR = 5 cycles
+DIMM 0 side 0 = 512 MB
+DIMM 0 side 1 = 512 MB
+DIMM 2 side 0 = 256 MB
+tRFC = 35 cycles
+Setting Graphics Frequency...
+FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz
+Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok
+Setting mode of operation for memory channels...Dual Channel Assymetric.
+Programming Clock Crossing...MEM=667 FSB=667... ok
+Setting RAM size...
+C0DRB = 0x20202010
+C1DRB = 0x28282828
+TOLUD = 0x0050
+Setting row attributes...
+C0DRA = 0x0033
+C1DRA = 0x0003
+one dimm per channel config..
+Initializing System Memory IO...
+Programming Dual Channel RCOMP
+Table Index: 17
+Programming DLL Timings...
+Enabling System Memory IO...
+jedec enable sequence: bank 0
+jedec enable sequence: bank 1
+bankaddr from bank size of rank 0
+jedec enable sequence: bank 4
+bankaddr from bank size of rank 1
+receive_enable_autoconfig() for channel 0
+ find_strobes_low()
+ set_receive_enable() medium=0x3, coarse=0x5
+ set_receive_enable() medium=0x1, coarse=0x5
+ find_strobes_edge()
+ set_receive_enable() medium=0x1, coarse=0x5
+ set_receive_enable() medium=0x3, coarse=0x5
+ add_quarter_clock() mediumcoarse=17 fine=00
+ find_preamble()
+ set_receive_enable() medium=0x3, coarse=0x4
+ set_receive_enable() medium=0x3, coarse=0x3
+ add_quarter_clock() mediumcoarse=0f fine=80
+ set_receive_enable() medium=0x1, coarse=0x4
+ normalize()
+Weird. No C0WL0REOST
+receive_enable_autoconfig() for channel 1
+ find_strobes_low()
+ set_receive_enable() medium=0x3, coarse=0x5
+ set_receive_enable() medium=0x1, coarse=0x5
+ find_strobes_edge()
+ set_receive_enable() medium=0x1, coarse=0x5
+ add_quarter_clock() mediumcoarse=15 fine=c6
+ set_receive_enable() medium=0x3, coarse=0x5
+ find_preamble()
+ set_receive_enable() medium=0x3, coarse=0x4
+ set_receive_enable() medium=0x3, coarse=0x3
+ add_quarter_clock() mediumcoarse=0f fine=46
+ normalize()
+ set_receive_enable() medium=0x0, coarse=0x4
+RAM initialization finished.
+Setting up Egress Port RCRB
+Loading port arbitration table ...ok
+Wait for VC1 negotiation ...ok
+Setting up DMI RCRB
+Wait for VC1 negotiation ...done..
+Internal graphics: enabled
+Waiting for DMI hardware...ok
+Enabling PCI Express x16
+
+*** Log truncated, 296 characters dropped. ***
+
+Adding CBMEM entry as no. 3
+Trying CBFS ramstage loader.
+CBFS: loading stage fallback/ramstage @ 0x100000 (340024 bytes), entry @ 0x100000
+coreboot-4.0-6185-g7f1f3fb-dirty-79ETE7WW (2.27 ) Wed Jul 16 14:03:30 BST 2014 booting...
+BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
+Enumerating buses...
+Show all devs...Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:02.1: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 1
+PCI: 00:1d.0: enabled 1
+PCI: 00:1d.1: enabled 1
+PCI: 00:1d.2: enabled 1
+PCI: 00:1d.3: enabled 1
+PCI: 00:1d.7: enabled 1
+PCI: 00:1e.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:1f.0: enabled 1
+PNP: 00ff.1: enabled 1
+PNP: 00ff.2: enabled 1
+PNP: 164e.2: enabled 1
+PNP: 164e.3: enabled 0
+PNP: 164e.7: enabled 1
+PNP: 164e.19: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 0
+PNP: 002e.3: enabled 1
+PNP: 002e.7: enabled 1
+PNP: 002e.a: enabled 0
+PCI: 00:1f.1: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+I2C: 00:69: enabled 1
+I2C: 00:54: enabled 1
+I2C: 00:55: enabled 1
+I2C: 00:56: enabled 1
+I2C: 00:57: enabled 1
+I2C: 00:5c: enabled 1
+I2C: 00:5d: enabled 1
+I2C: 00:5e: enabled 1
+I2C: 00:5f: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:02.0: enabled 1
+ PCI: 00:02.1: enabled 1
+ PCI: 00:1b.0: enabled 1
+ PCI: 00:1c.0: enabled 1
+ PCI: 00:1c.1: enabled 1
+ PCI: 00:1d.0: enabled 1
+ PCI: 00:1d.1: enabled 1
+ PCI: 00:1d.2: enabled 1
+ PCI: 00:1d.3: enabled 1
+ PCI: 00:1d.7: enabled 1
+ PCI: 00:1e.0: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:1f.0: enabled 1
+ PNP: 00ff.1: enabled 1
+ PNP: 00ff.2: enabled 1
+ PNP: 164e.2: enabled 1
+ PNP: 164e.3: enabled 0
+ PNP: 164e.7: enabled 1
+ PNP: 164e.19: enabled 1
+ PNP: 002e.0: enabled 0
+ PNP: 002e.1: enabled 1
+ PNP: 002e.2: enabled 0
+ PNP: 002e.3: enabled 1
+ PNP: 002e.7: enabled 1
+ PNP: 002e.a: enabled 0
+ PCI: 00:1f.1: enabled 1
+ PCI: 00:1f.2: enabled 1
+ PCI: 00:1f.3: enabled 1
+ I2C: 00:69: enabled 1
+ I2C: 00:54: enabled 1
+ I2C: 00:55: enabled 1
+ I2C: 00:56: enabled 1
+ I2C: 00:57: enabled 1
+ I2C: 00:5c: enabled 1
+ I2C: 00:5d: enabled 1
+ I2C: 00:5e: enabled 1
+ I2C: 00:5f: enabled 1
+scan_static_bus for Root Device
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [8086/27a0] ops
+PCI: 00:00.0 [8086/27a0] enabled
+PCI: Static device PCI: 00:01.0 not found, disabling it.
+PCI: 00:02.0 [8086/27a2] ops
+PCI: 00:02.0 [8086/27a2] enabled
+PCI: 00:02.1 [8086/27a6] ops
+PCI: 00:02.1 [8086/27a6] enabled
+PCI: 00:1b.0 [8086/27d8] ops
+PCI: 00:1b.0 [8086/27d8] enabled
+PCI: 00:1c.0 [8086/0000] bus ops
+PCI: 00:1c.0 [8086/27d0] enabled
+PCI: 00:1c.1 [8086/0000] bus ops
+PCI: 00:1c.1 [8086/27d2] enabled
+PCI: 00:1c.2 [8086/0000] bus ops
+PCI: 00:1c.2 [8086/27d4] enabled
+PCI: 00:1c.3 [8086/0000] bus ops
+PCI: 00:1c.3 [8086/27d6] enabled
+PCI: 00:1d.0 [8086/27c8] ops
+PCI: 00:1d.0 [8086/27c8] enabled
+PCI: 00:1d.1 [8086/27c9] ops
+PCI: 00:1d.1 [8086/27c9] enabled
+PCI: 00:1d.2 [8086/27ca] ops
+PCI: 00:1d.2 [8086/27ca] enabled
+PCI: 00:1d.3 [8086/27cb] ops
+PCI: 00:1d.3 [8086/27cb] enabled
+PCI: 00:1d.7 [8086/27cc] ops
+PCI: 00:1d.7 [8086/27cc] enabled
+PCI: 00:1e.0 [8086/2448] bus ops
+PCI: 00:1e.0 [8086/2448] enabled
+PCI: 00:1f.0 [8086/27b9] bus ops
+PCI: 00:1f.0 [8086/27b9] enabled
+PCI: 00:1f.1 [8086/27df] ops
+PCI: 00:1f.1 [8086/27df] enabled
+PCI: 00:1f.2 [8086/0000] ops
+PCI: 00:1f.2 [8086/27c4] enabled
+PCI: 00:1f.3 [8086/27da] bus ops
+PCI: 00:1f.3 [8086/27da] enabled
+do_pci_scan_bridge for PCI: 00:1c.0
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [8086/109a] enabled
+PCI: pci_scan_bus returning with max=001
+do_pci_scan_bridge returns max 1
+do_pci_scan_bridge for PCI: 00:1c.1
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [8086/4227] enabled
+PCI: pci_scan_bus returning with max=002
+do_pci_scan_bridge returns max 2
+do_pci_scan_bridge for PCI: 00:1c.2
+PCI: pci_scan_bus for bus 03
+PCI: pci_scan_bus returning with max=003
+do_pci_scan_bridge returns max 3
+do_pci_scan_bridge for PCI: 00:1c.3
+PCI: pci_scan_bus for bus 04
+PCI: pci_scan_bus returning with max=004
+do_pci_scan_bridge returns max 4
+do_pci_scan_bridge for PCI: 00:1e.0
+PCI: pci_scan_bus for bus 05
+PCI: 05:00.0 [104c/ac56] ops
+PCI: 05:00.0 [104c/ac56] enabled
+PCI: pci_scan_bus returning with max=005
+do_pci_scan_bridge returns max 5
+scan_static_bus for PCI: 00:1f.0
+PNP: 00ff.1 enabled
+recv_ec_data: 0x37
+recv_ec_data: 0x39
+recv_ec_data: 0x48
+recv_ec_data: 0x54
+recv_ec_data: 0x35
+recv_ec_data: 0x30
+recv_ec_data: 0x57
+recv_ec_data: 0x57
+recv_ec_data: 0x04
+recv_ec_data: 0x03
+recv_ec_data: 0x70
+recv_ec_data: 0x10
+EC Firmware ID 79HT50WW-3.4, Version 7.01A
+recv_ec_data: 0x00
+recv_ec_data: 0x10
+recv_ec_data: 0x20
+recv_ec_data: 0x30
+recv_ec_data: 0x00
+recv_ec_data: 0xa6
+recv_ec_data: 0x01
+recv_ec_data: 0x70
+PNP: 00ff.2 enabled
+PNP: 164e.2 enabled
+PNP: 164e.3 disabled
+PNP: 164e.7 enabled
+PNP: 164e.19 enabled
+PNP: 002e.0 disabled
+PNP: 002e.1 enabled
+PNP: 002e.2 disabled
+PNP: 002e.3 enabled
+PNP: 002e.7 enabled
+PNP: 002e.a disabled
+scan_static_bus for PCI: 00:1f.0 done
+scan_static_bus for PCI: 00:1f.3
+smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
+smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
+scan_static_bus for PCI: 00:1f.3 done
+PCI: pci_scan_bus returning with max=005
+scan_static_bus for Root Device done
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 34254 exit 0
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+APIC: 00 missing read_resources
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
+PCI: 00:1c.0 read_resources bus 1 link: 0
+PCI: 00:1c.0 read_resources bus 1 link: 0 done
+PCI: 00:1c.1 read_resources bus 2 link: 0
+PCI: 00:1c.1 read_resources bus 2 link: 0 done
+PCI: 00:1c.2 read_resources bus 3 link: 0
+PCI: 00:1c.2 read_resources bus 3 link: 0 done
+PCI: 00:1c.3 read_resources bus 4 link: 0
+PCI: 00:1c.3 read_resources bus 4 link: 0 done
+PCI: 00:1e.0 read_resources bus 5 link: 0
+PCI: 00:1e.0 read_resources bus 5 link: 0 done
+PCI: 00:1f.0 read_resources bus 0 link: 0
+PNP: 00ff.1 missing read_resources
+PNP: 00ff.2 missing read_resources
+PCI: 00:1f.0 read_resources bus 0 link: 0 done
+PCI: 00:1f.3 read_resources bus 1 link: 0
+PCI: 00:1f.3 read_resources bus 1 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0 child on link 0 PCI: 00:00.0
+ PCI: 00:00.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10
+ PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14
+ PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18
+ PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c
+ PCI: 00:02.1
+ PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 01:00.0
+ PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+ PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+ PCI: 00:1c.1 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:1c.2
+ PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:1c.3
+ PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1d.1
+ PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1d.2
+ PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1d.3
+ PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1d.7
+ PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1e.0 child on link 0 PCI: 05:00.0
+ PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 05:00.0
+ PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 2c
+ PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 34
+ PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c
+ PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24
+ PCI: 00:1f.0 child on link 0 PNP: 00ff.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 00ff.1
+ PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
+ PNP: 00ff.2
+ PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
+ PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
+ PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
+ PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
+ PNP: 164e.2
+ PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 164e.2 resource base b0 size 0 align 0 gran 0 limit 0 flags c0000400 index 29
+ PNP: 164e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 164e.2 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
+ PNP: 164e.2 resource base 82 size 0 align 0 gran 0 limit 0 flags c0000400 index f0
+ PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
+ PNP: 164e.3
+ PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 164e.7
+ PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60
+ PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 164e.19
+ PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60
+ PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60
+ PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 1620 size 10 align 4 gran 4 limit ffff flags c0000100 index 60
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.a
+ PCI: 00:1f.1
+ PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
+ PCI: 00:1f.3 child on link 0 I2C: 01:69
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ I2C: 01:69
+ I2C: 01:54
+ I2C: 01:55
+ I2C: 01:56
+ I2C: 01:57
+ I2C: 01:5c
+ I2C: 01:5d
+ I2C: 01:5e
+ I2C: 01:5f
+DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 01:00.0 18 * [0x0 - 0x1f] io
+PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 05:00.0 2c * [0x0 - 0xfff] io
+PCI: 05:00.0 34 * [0x1000 - 0x1fff] io
+PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1e.0 1c * [0x0 - 0x1fff] io
+PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io
+PCI: 00:1d.0 20 * [0x3000 - 0x301f] io
+PCI: 00:1d.1 20 * [0x3020 - 0x303f] io
+PCI: 00:1d.2 20 * [0x3040 - 0x305f] io
+PCI: 00:1d.3 20 * [0x3060 - 0x307f] io
+PCI: 00:1f.1 20 * [0x3080 - 0x308f] io
+PCI: 00:1f.2 20 * [0x3090 - 0x309f] io
+PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io
+PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io
+PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io
+PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io
+PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io
+PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io
+PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io
+PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io
+PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io
+DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem
+PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0xfff] mem
+PCI: 00:1c.1 compute_resources_mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem
+PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem
+PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem
+PCI: 00:1e.0 compute_resources_mem: base: 2001000 size: 2100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
+PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem
+PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem
+PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem
+PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem
+PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem
+PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem
+PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem
+PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem
+PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem
+PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem
+DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: DOMAIN: 0000
+constrain_resources: PCI: 00:00.0
+constrain_resources: PCI: 00:02.0
+constrain_resources: PCI: 00:02.1
+constrain_resources: PCI: 00:1b.0
+constrain_resources: PCI: 00:1c.0
+constrain_resources: PCI: 01:00.0
+constrain_resources: PCI: 00:1c.1
+constrain_resources: PCI: 02:00.0
+constrain_resources: PCI: 00:1c.2
+constrain_resources: PCI: 00:1c.3
+constrain_resources: PCI: 00:1d.0
+constrain_resources: PCI: 00:1d.1
+constrain_resources: PCI: 00:1d.2
+constrain_resources: PCI: 00:1d.3
+constrain_resources: PCI: 00:1d.7
+constrain_resources: PCI: 00:1e.0
+constrain_resources: PCI: 05:00.0
+constrain_resources: PCI: 00:1f.0
+constrain_resources: PNP: 00ff.1
+constrain_resources: PNP: 00ff.2
+skipping PNP: 00ff.2@60 fixed resource, size=0!
+skipping PNP: 00ff.2@62 fixed resource, size=0!
+skipping PNP: 00ff.2@64 fixed resource, size=0!
+skipping PNP: 00ff.2@66 fixed resource, size=0!
+constrain_resources: PNP: 164e.2
+skipping PNP: 164e.2@29 fixed resource, size=0!
+skipping PNP: 164e.2@f0 fixed resource, size=0!
+constrain_resources: PNP: 164e.7
+constrain_resources: PNP: 164e.19
+constrain_resources: PNP: 002e.1
+constrain_resources: PNP: 002e.3
+constrain_resources: PNP: 002e.7
+constrain_resources: PCI: 00:1f.1
+constrain_resources: PCI: 00:1f.2
+constrain_resources: PCI: 00:1f.3
+constrain_resources: I2C: 01:69
+constrain_resources: I2C: 01:54
+constrain_resources: I2C: 01:55
+constrain_resources: I2C: 01:56
+constrain_resources: I2C: 01:57
+constrain_resources: I2C: 01:5c
+constrain_resources: I2C: 01:5d
+constrain_resources: I2C: 01:5e
+constrain_resources: I2C: 01:5f
+avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
+ lim->base 00001690 lim->limit 0000ffff
+avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
+ lim->base 00000000 lim->limit efffffff
+Setting resources...
+DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff
+Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io
+Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io
+Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io
+Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io
+Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io
+Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io
+Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io
+Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io
+Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io
+Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io
+Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io
+Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io
+Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io
+Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io
+Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io
+Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io
+Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io
+DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done
+PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff
+Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io
+PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done
+PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff
+Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io
+Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io
+PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done
+DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff
+Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
+Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem
+Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem
+Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem
+Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem
+Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem
+Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem
+Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem
+Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem
+Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem
+Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem
+DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done
+PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff
+Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem
+PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff
+Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe4200fff] mem
+PCI: 00:1c.1 allocate_resources_mem: next_base: e4201000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff
+Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem
+PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done
+PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff
+Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem
+Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem
+PCI: 00:1e.0 allocate_resources_mem: next_base: e2001000 size: 2100000 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+pci_tolm: 0xd0000000
+Base of stolen memory: 0x4f800000
+Top of Low Used DRAM: 0x50000000
+IGD decoded, subtracting 8M UMA
+Available memory: 1302528K (1272M)
+Adding PCIe config bar
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
+PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem
+PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io
+PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem
+PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem
+PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem
+PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io
+PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 00:1c.0 assign_resources, bus 1 link: 0
+PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem
+PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io
+PCI: 00:1c.0 assign_resources, bus 1 link: 0
+PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:1c.1 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e4200fff] size 0x00001000 gran 0x0c mem
+PCI: 00:1c.1 assign_resources, bus 2 link: 0
+PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
+PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
+PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem
+PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
+PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem
+PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem
+PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io
+PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io
+PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io
+PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io
+PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io
+PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem
+PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem
+PCI: 00:1e.0 assign_resources, bus 5 link: 0
+PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem
+PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io
+PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io
+PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem
+PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem
+PCI: 00:1e.0 assign_resources, bus 5 link: 0
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PNP: 00ff.1 missing set_resources
+PNP: 00ff.2 missing set_resources
+PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
+PNP: 164e.2 29 <- [0x00000000b0 - 0x00000000af] size 0x00000000 gran 0x00 irq
+PNP: 164e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
+PNP: 164e.2 74 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 drq
+PNP: 164e.2 f0 <- [0x0000000082 - 0x0000000081] size 0x00000000 gran 0x00 irq
+ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned
+PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io
+ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned
+PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io
+ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned
+PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io
+PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
+ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned
+PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PNP: 002e.7 60 <- [0x0000001620 - 0x000000162f] size 0x00000010 gran 0x04 io
+ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io
+PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io
+PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io
+PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io
+PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io
+PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io
+PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1f.3 assign_resources, bus 1 link: 0
+PCI: 00:1f.3 assign_resources, bus 1 link: 0
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+CBMEM region 4f6d0000-4f7fffff (cbmem_late_set_table)
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
+ DOMAIN: 0000 resource base c0000 size 4ff40000 align 0 gran 0 limit 0 flags e0004200 index 4
+ DOMAIN: 0000 resource base 4f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
+ DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0 child on link 0 PCI: 00:00.0
+ PCI: 00:00.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10
+ PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14
+ PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18
+ PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c
+ PCI: 00:02.1
+ PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 01:00.0
+ PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10
+ PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
+ PCI: 00:1c.1 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base e4200000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10
+ PCI: 00:1c.2
+ PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 00:1c.3
+ PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
+ PCI: 00:1d.1
+ PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
+ PCI: 00:1d.2
+ PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
+ PCI: 00:1d.3
+ PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
+ PCI: 00:1d.7
+ PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
+ PCI: 00:1e.0 child on link 0 PCI: 05:00.0
+ PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 05:00.0
+ PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10
+ PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c
+ PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34
+ PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c
+ PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24
+ PCI: 00:1f.0 child on link 0 PNP: 00ff.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 00ff.1
+ PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
+ PNP: 00ff.2
+ PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
+ PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
+ PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
+ PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
+ PNP: 164e.2
+ PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+ PNP: 164e.2 resource base b0 size 0 align 0 gran 0 limit 0 flags e0000400 index 29
+ PNP: 164e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 164e.2 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
+ PNP: 164e.2 resource base 82 size 0 align 0 gran 0 limit 0 flags e0000400 index f0
+ PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
+ PNP: 164e.3
+ PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 164e.7
+ PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60
+ PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 164e.19
+ PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60
+ PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60
+ PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 1620 size 10 align 4 gran 4 limit ffff flags e0000100 index 60
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.a
+ PCI: 00:1f.1
+ PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
+ PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
+ PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
+ PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
+ PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
+ PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
+ PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
+ PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
+ PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24
+ PCI: 00:1f.3 child on link 0 I2C: 01:69
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ I2C: 01:69
+ I2C: 01:54
+ I2C: 01:55
+ I2C: 01:56
+ I2C: 01:57
+ I2C: 01:5c
+ I2C: 01:5d
+ I2C: 01:5e
+ I2C: 01:5f
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 162457 exit 0
+Enabling resources...
+PCI: 00:00.0 subsystem <- 17aa/2015
+PCI: 00:00.0 cmd <- 06
+PCI: 00:02.0 subsystem <- 17aa/201a
+PCI: 00:02.0 cmd <- 03
+PCI: 00:02.1 subsystem <- 17aa/201a
+PCI: 00:02.1 cmd <- 02
+PCI: 00:1b.0 subsystem <- 17aa/2010
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 17aa/2001
+PCI: 00:1c.0 cmd <- 107
+PCI: 00:1c.1 bridge ctrl <- 0003
+PCI: 00:1c.1 subsystem <- 0000/0000
+PCI: 00:1c.1 cmd <- 106
+PCI: 00:1c.2 bridge ctrl <- 0003
+PCI: 00:1c.2 cmd <- 00
+PCI: 00:1c.3 bridge ctrl <- 0003
+PCI: 00:1c.3 cmd <- 00
+PCI: 00:1d.0 subsystem <- 17aa/200a
+PCI: 00:1d.0 cmd <- 01
+PCI: 00:1d.1 subsystem <- 17aa/200a
+PCI: 00:1d.1 cmd <- 01
+PCI: 00:1d.2 subsystem <- 17aa/200a
+PCI: 00:1d.2 cmd <- 01
+PCI: 00:1d.3 subsystem <- 17aa/200a
+PCI: 00:1d.3 cmd <- 01
+PCI: 00:1d.7 subsystem <- 17aa/200b
+PCI: 00:1d.7 cmd <- 102
+PCI: 00:1e.0 bridge ctrl <- 0003
+PCI: 00:1e.0 subsystem <- 0000/0000
+PCI: 00:1e.0 cmd <- 107 (NOT WRITTEN!)
+PCI: 00:1f.0 subsystem <- 17aa/2009
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.1 subsystem <- 17aa/200c
+PCI: 00:1f.1 cmd <- 01
+PCI: 00:1f.2 subsystem <- 17aa/200d
+PCI: 00:1f.2 cmd <- 03
+PCI: 00:1f.3 subsystem <- 17aa/200f
+PCI: 00:1f.3 cmd <- 101
+PCI: 01:00.0 cmd <- 03
+PCI: 02:00.0 cmd <- 02
+PCI: 05:00.0 bridge ctrl <- 0143
+PCI: 05:00.0 subsystem <- 17aa/2012
+PCI: 05:00.0 cmd <- 03
+done.
+BS: BS_DEV_ENABLE times (us): entry 0 run 6329 exit 0
+Initializing devices...
+Root Device init
+recv_ec_data: 0x00
+Root Device init 731 usecs
+CPU_CLUSTER: 0 init
+start_eip=0x00001000, code_size=0x00000031
+Initializing SMM handler... ... pmbase = 0x0500
+
+SMI_STS: MCSMI PM1
+PM1_STS: WAK PWRBTN
+GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
+ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
+TCO_STS: INTRD_DET
+ ... raise SMI#
+Initializing CPU #0
+CPU: vendor Intel device 6f6
+CPU: family 06, model 0f, stepping 06
+Enabling cache
+microcode: sig=0x6f6 pf=0x20 revision=0x0
+Microcode size field is 0
+Microcode size field is 0
+Microcode size field is 0
+Microcode size field is 0
+fchmmr: built-in microcode revision 0x0 date=2010-10-01
+microcode: updated to revision 0xd1 date=2010-10-01
+CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz.
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x000000004f800000 size 0x4f740000 type 6
+0x000000004f800000 - 0x00000000d0000000 size 0x80800000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+MTRR: default type WB/UC MTRR counts: 7/4.
+MTRR: UC selected as default type.
+MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6
+MTRR: 1 base 0x0000000040000000 mask 0x0000000ff0000000 type 6
+MTRR: 2 base 0x000000004f800000 mask 0x0000000fff800000 type 0
+MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local apic... apic_id: 0x00 done.
+CPU: 0 2 siblings
+CPU: 0 has sibling 1
+CPU #0 initialized
+CPU1: stack_base 0014d000, stack_end 0014dff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+Waiting for 1 CPUS to stop
+CPU: vendor Intel device 6f6
+CPU: family 06, model 0f, stepping 06
+Enabling cache
+microcode: sig=0x6f6 pf=0x20 revision=0x0
+Microcode size field is 0
+Microcode size field is 0
+Microcode size field is 0
+Microcode size field is 0
+fchmmr: built-in microcode revision 0x0 date=2010-10-01
+microcode: updated to revision 0xd1 date=2010-10-01
+CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6
+MTRR: 1 base 0x0000000040000000 mask 0x0000000ff0000000 type 6
+MTRR: 2 base 0x000000004f800000 mask 0x0000000fff800000 type 0
+MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local apic... apic_id: 0x01 done.
+CPU: 1 2 siblings
+CPU #1 initialized
+CPU 1 going down...
+All AP CPUs stopped (3090 loops)
+CPU1: stack: 0014d000 - 0014e000, lowest used address 0014dc68, stack used: 920 bytes
+CPU_CLUSTER: 0 init 81155 usecs
+PCI: 00:00.0 init
+Normal boot.
+PCI: 00:00.0 init 140 usecs
+PCI: 00:02.0 init
+Initializing VGA without OPROM.
+GMADR=0xd0000008 GTTADR=0xe4400000
+i915lightup: graphics d0000000 mmio e4300000 addrport 50a0 physbase 4f820000
+EDID:
+00 ff ff ff ff ff ff 00 30 ae 22 40 00 00 00 00
+2f 10 01 03 80 1d 15 78 ea 6f 95 9c 54 4c 87 26
+21 50 54 21 08 00 81 80 01 01 01 01 01 01 01 01
+01 01 01 01 01 01 30 2a 78 20 51 1a 10 40 30 70
+13 00 1f d7 10 00 00 18 25 23 78 20 51 1a 10 40
+30 70 13 00 1f d7 10 00 00 18 00 00 00 0f 00 90
+43 32 90 43 28 0f 01 00 30 64 90 55 00 00 00 fe
+00 4c 54 44 31 34 31 45 4e 39 42 0a 20 20 00 33
+Extracted contents:
+header: 00 ff ff ff ff ff ff 00
+serial number: 30 ae 22 40 00 00 00 00 2f 10
+version: 01 03
+basic params: 80 1d 15 78 ea
+chroma info: 6f 95 9c 54 4c 87 26 21 50 54
+established: 21 08 00
+standard: 81 80 01 01 01 01 01 01 01 01 01 01 01 01 01 01
+descriptor 1: 30 2a 78 20 51 1a 10 40 30 70 13 00 1f d7 10 00 00 18
+descriptor 2: 25 23 78 20 51 1a 10 40 30 70 13 00 1f d7 10 00 00 18
+descriptor 3: 00 00 00 0f 00 90 43 32 90 43 28 0f 01 00 30 64 90 55
+descriptor 4: 00 00 00 fe 00 4c 54 44 31 34 31 45 4e 39 42 0a 20 20
+extensions: 00
+checksum: 33
+
+Manufacturer: LEN Model 4022 Serial Number 0
+Made week 47 of 2006
+EDID version: 1.3
+Digital display
+Maximum image size: 29 cm x 21 cm
+Gamma: 220%
+Check DPMS levels
+DPMS levels: Standby Suspend Off
+Supported color formats: RGB 4:4:4, YCrCb 4:2:2
+First detailed timing is preferred timing
+Established timings supported:
+ 640x480@60Hz
+ 800x600@60Hz
+ 1024x768@60Hz
+Standard timings supported:
+ 1280x1024@60Hz
+Detailed timings
+Hex of detail: 302a7820511a1040307013001fd710000018
+Did detailed timing
+Detailed mode (IN HEX): Clock 108000 KHz, 11f mm x d7 mm
+ 0578 05a8 0618 0698 hborder 0
+ 041a 041b 041e 042a vborder 0
+ -hsync -vsync
+Hex of detail: 25237820511a1040307013001fd710000018
+Detailed mode (IN HEX): Clock 108000 KHz, 11f mm x d7 mm
+ 0578 05a8 0618 0698 hborder 0
+ 041a 041b 041e 042a vborder 0
+ -hsync -vsync
+Hex of detail: 0000000f009043329043280f010030649055
+Manufacturer-specified data, tag 15
+Hex of detail: 000000fe004c5444313431454e39420a2020
+ASCII string: LTD141EN9B
+Checksum
+Checksum: 0x33 (valid)
+
+Unknown extension block
+
+EDID block does NOT conform to EDID 1.3!
+ Missing name descriptor
+ Missing monitor ranges
+EDID block does not conform at all!
+ Detailed blocks filled with garbage
+bringing up panel at resolution 1408 x 1050
+Borders 0 x 0
+Blank 288 x 16
+Sync 112 x 3
+Front porch 48 x 1
+Spread spectrum clock
+Dual channel
+Polarities 1, 1
+Pixel N=10, M1=23, M2=11, P1=2
+Pixel clock 108000 kHz
+waiting for panel powerup
+panel powered up
+gtt_setup is enabled.
+GTT PGETBL_CTL register: 0x4ffc0001
+GTT Enabled
+memset d0000000 to 0x00 for 5913600 bytes
+PCI: 00:02.0 init 37273 usecs
+PCI: 00:02.1 init
+PCI: 00:02.1 init 80 usecs
+PCI: 00:1b.0 init
+Azalia: codec type: Azalia
+Azalia: base = e4440000
+Azalia: codec_mask = 03
+Azalia: Initializing codec #1
+Azalia: codec viddid: 14f12bfa
+Azalia: No verb!
+Azalia: Initializing codec #0
+Azalia: codec viddid: 11d41981
+Azalia: No verb!
+PCI: 00:1b.0 init 4172 usecs
+PCI: 00:1c.0 init
+Initializing ICH7 PCIe bridge.
+PCI: 00:1c.0 init 230 usecs
+PCI: 00:1c.1 init
+Initializing ICH7 PCIe bridge.
+PCI: 00:1c.1 init 231 usecs
+PCI: 00:1c.2 init
+Initializing ICH7 PCIe bridge.
+PCI: 00:1c.2 init 230 usecs
+PCI: 00:1c.3 init
+Initializing ICH7 PCIe bridge.
+PCI: 00:1c.3 init 230 usecs
+PCI: 00:1d.0 init
+UHCI: Setting up controller.. done.
+PCI: 00:1d.0 init 239 usecs
+PCI: 00:1d.1 init
+UHCI: Setting up controller.. done.
+PCI: 00:1d.1 init 239 usecs
+PCI: 00:1d.2 init
+UHCI: Setting up controller.. done.
+PCI: 00:1d.2 init 239 usecs
+PCI: 00:1d.3 init
+UHCI: Setting up controller.. done.
+PCI: 00:1d.3 init 238 usecs
+PCI: 00:1d.7 init
+EHCI: Setting up controller.. done.
+PCI: 00:1d.7 init 244 usecs
+PCI: 00:1e.0 init
+PCI: 00:1e.0 init 91 usecs
+PCI: 00:1f.0 init
+i82801gx: lpc_init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+Set power on after power failure.
+NMI sources disabled.
+rtc_failed = 0x0
+RTC Init
+i8259_configure_irq_trigger: current interrupts are 0x0
+i8259_configure_irq_trigger: try to set interrupts 0x200
+Disabling ACPI via APMC:
+done.
+Locking SMM.
+PCI: 00:1f.0 init 2749 usecs
+PCI: 00:1f.1 init
+i82801gx_ide: initializing... IDE0
+PCI: 00:1f.1 init 246 usecs
+PCI: 00:1f.2 init
+i82801gx_sata: initializing...
+SATA controller in AHCI mode.
+PCI: 00:1f.2 init 366 usecs
+PCI: 01:00.0 init
+PCI: 01:00.0 init 80 usecs
+PCI: 02:00.0 init
+PCI: 02:00.0 init 80 usecs
+PCI: 05:00.0 init
+Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller
+PCI: 05:00.0 init 336 usecs
+PNP: 164e.2 init
+PNP: 164e.2 init 76 usecs
+PNP: 164e.7 init
+PNP: 164e.7 init 75 usecs
+PNP: 164e.19 init
+PNP: 164e.19 init 80 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:69 init
+I2C: 01:69 init 12780 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
+I2C: 01:54 init 172 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
+I2C: 01:55 init 172 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
+I2C: 01:56 init 172 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
+I2C: 01:57 init 171 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
+Locking EEPROM RFID
+init EEPROM done
+I2C: 01:5c init 21937 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
+I2C: 01:5d init 172 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
+I2C: 01:5e init 172 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
+I2C: 01:5f init 172 usecs
+Devices initialized
+Show all devs...After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:02.1: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 1
+PCI: 00:1d.0: enabled 1
+PCI: 00:1d.1: enabled 1
+PCI: 00:1d.2: enabled 1
+PCI: 00:1d.3: enabled 1
+PCI: 00:1d.7: enabled 1
+PCI: 00:1e.0: enabled 1
+PCI: 05:00.0: enabled 1
+PCI: 00:1f.0: enabled 1
+PNP: 00ff.1: enabled 1
+PNP: 00ff.2: enabled 1
+PNP: 164e.2: enabled 1
+PNP: 164e.3: enabled 0
+PNP: 164e.7: enabled 1
+PNP: 164e.19: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 0
+PNP: 002e.3: enabled 1
+PNP: 002e.7: enabled 1
+PNP: 002e.a: enabled 0
+PCI: 00:1f.1: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+I2C: 01:69: enabled 1
+I2C: 01:54: enabled 1
+I2C: 01:55: enabled 1
+I2C: 01:56: enabled 1
+I2C: 01:57: enabled 1
+I2C: 01:5c: enabled 1
+I2C: 01:5d: enabled 1
+I2C: 01:5e: enabled 1
+I2C: 01:5f: enabled 1
+PCI: 00:1c.2: enabled 1
+PCI: 00:1c.3: enabled 1
+PCI: 01:00.0: enabled 1
+PCI: 02:00.0: enabled 1
+APIC: 01: enabled 1
+BS: BS_DEV_INIT times (us): entry 0 run 175093 exit 0
+CBMEM region 4f6d0000-4f7fffff (cbmem_check_toc)
+Adding CBMEM entry as no. 4
+Moving GDT to 4f6e0600...ok
+Finalize devices...
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 477 run 168 exit 0
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
+Copying Interrupt Routing Table to 0x000f0000... done.
+Adding CBMEM entry as no. 5
+Copying Interrupt Routing Table to 0x4f6e0800... done.
+PIRQ table: 272 bytes.
+Wrote the mp table end at: 000f0410 - 000f05b4
+Adding CBMEM entry as no. 6
+Wrote the mp table end at: 4f6e1810 - 4f6e19b4
+MP table: 436 bytes.
+Adding CBMEM entry as no. 7
+ACPI: Writing ACPI tables at 4f6e2800.
+ACPI: * HPET
+ACPI: added table 1/32, length now 40
+ACPI: * MADT
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: added table 3/32, length now 48
+ACPI: * FACS
+ACPI: Patching up global NVS in DSDT at offset 0x0263 -> 0x4f6e5ca0
+ACPI: * DSDT @ 4f6e2b40 Length 315e
+ACPI: * FADT
+ACPI: added table 4/32, length now 52
+ACPI: * SSDT
+Found 1 CPU(s) with 2 core(s) each.
+clocks between 1000 and 2000 MHz.
+adding 4 P-States between busratio 6 and c, incl. P0
+PSS: 2000MHz power 35000 control 0xc27 status 0xc27
+PSS: 1666MHz power 31666 control 0xa1f status 0xa1f
+PSS: 1333MHz power 28333 control 0x819 status 0x819
+PSS: 1000MHz power 25000 control 0x613 status 0x613
+clocks between 1000 and 2000 MHz.
+adding 4 P-States between busratio 6 and c, incl. P0
+PSS: 2000MHz power 35000 control 0xc27 status 0xc27
+PSS: 1666MHz power 31666 control 0xa1f status 0xa1f
+PSS: 1333MHz power 28333 control 0x819 status 0x819
+PSS: 1000MHz power 25000 control 0x613 status 0x613
+ACPI: added table 5/32, length now 56
+current = 4f6e61e0
+ACPI: done.
+Laptop handling...
+ACPI tables: 14816 bytes.
+Adding CBMEM entry as no. 8
+smbios_write_tables: 4f6edc00
+Root Device (Lenovo ThinkPad T60 / T60p)
+recv_ec_data: 0x37
+recv_ec_data: 0x39
+recv_ec_data: 0x48
+recv_ec_data: 0x54
+recv_ec_data: 0x35
+recv_ec_data: 0x30
+recv_ec_data: 0x57
+recv_ec_data: 0x57
+recv_ec_data: 0x04
+recv_ec_data: 0x03
+CPU_CLUSTER: 0 (Intel i945 Northbridge)
+APIC: 00 (Socket mFCPGA478 CPU)
+DOMAIN: 0000 (Intel i945 Northbridge)
+PCI: 00:00.0 (Intel i945 Northbridge)
+PCI: 00:01.0 (Intel i945 Northbridge)
+PCI: 00:00.0 (Intel i945 Northbridge)
+PCI: 00:02.0 (Intel i945 Northbridge)
+PCI: 00:02.1 (Intel i945 Northbridge)
+PCI: 00:1b.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1c.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1c.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1d.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1d.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1d.2 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1d.3 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1d.7 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1e.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 05:00.0 (TI PCI1x2x Cardbus controller)
+PCI: 00:1f.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
+PNP: 00ff.2 (Lenovo H8 EC)
+PNP: 164e.2 (NSC PC87382 Docking LPC Switch)
+PNP: 164e.3 (NSC PC87382 Docking LPC Switch)
+PNP: 164e.7 (NSC PC87382 Docking LPC Switch)
+PNP: 164e.19 (NSC PC87382 Docking LPC Switch)
+PNP: 002e.0 (NSC PC87384 Super I/O)
+PNP: 002e.1 (NSC PC87384 Super I/O)
+PNP: 002e.2 (NSC PC87384 Super I/O)
+PNP: 002e.3 (NSC PC87384 Super I/O)
+PNP: 002e.7 (NSC PC87384 Super I/O)
+PNP: 002e.a (NSC PC87384 Super I/O)
+PCI: 00:1f.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1f.2 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+PCI: 00:1f.3 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
+I2C: 01:69 (ICS 954309 Clock generator)
+I2C: 01:54 (AT24RF08C)
+I2C: 01:55 (AT24RF08C)
+I2C: 01:56 (AT24RF08C)
+I2C: 01:57 (AT24RF08C)
+I2C: 01:5c (AT24RF08C)
+I2C: 01:5d (AT24RF08C)
+I2C: 01:5e (AT24RF08C)
+I2C: 01:5f (AT24RF08C)
+PCI: 00:1c.2 (unknown)
+PCI: 00:1c.3 (unknown)
+PCI: 01:00.0 (unknown)
+PCI: 02:00.0 (unknown)
+APIC: 01 (unknown)
+SMBIOS tables: 425 bytes.
+Adding CBMEM entry as no. 9
+Adding CBMEM entry as no. 10
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum cc5f
+Table forward entry ends at 0x00000528.
+... aligned to 0x00001000
+Writing coreboot table at 0x4f7ee400
+rom_table_end = 0x4f7ee400
+... aligned to 0x4f7f0000
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000c0000-000000004f6cffff: RAM
+ 3. 000000004f6d0000-000000004f7fffff: CONFIGURATION TABLES
+ 4. 000000004f800000-000000004fffffff: RESERVED
+ 5. 00000000f0000000-00000000f3ffffff: RESERVED
+Wrote coreboot table at: 4f7ee400, 0x1b0 bytes, checksum 9ec5
+coreboot table: 456 bytes.
+FREE SPACE 0. 4f7f6400 00009c00
+CAR GLOBALS 1. 4f6d0200 00000200
+CONSOLE 2. 4f6d0400 00010000
+ROMSTAGE 3. 4f6e0400 00000200
+GDT 4. 4f6e0600 00000200
+IRQ TABLE 5. 4f6e0800 00001000
+SMP TABLE 6. 4f6e1800 00001000
+ACPI 7. 4f6e2800 0000b400
+SMBIOS 8. 4f6edc00 00000800
+ACPI RESUME 9. 4f6ee400 00100000
+COREBOOT 10. 4f7ee400 00008000
+BS: BS_WRITE_TABLES times (us): entry 0 run 140264 exit 0
+CBFS: located payload @ ffe3e1f8, 329522 bytes.
+Loading segment from rom address 0xffe3e1f8
+ code (compression=1)
+ New segment dstaddr 0x8200 memsize 0x17e40 srcaddr 0xffe3e24c filesize 0x83ec
+ (cleaned up) New segment addr 0x8200 size 0x17e40 offset 0xffe3e24c filesize 0x83ec
+Loading segment from rom address 0xffe3e214
+ code (compression=1)
+ New segment dstaddr 0x100000 memsize 0x10316c srcaddr 0xffe46638 filesize 0x482f2
+ (cleaned up) New segment addr 0x100000 size 0x10316c offset 0xffe46638 filesize 0x482f2
+Loading segment from rom address 0xffe3e230
+ Entry Point 0x00008200
+Bounce Buffer at 4f579000, 1401252 bytes
+Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017e40 filesz: 0x00000000000083ec
+lb: [0x0000000000100000, 0x0000000000153038)
+Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017e40 filesz: 0x00000000000083ec
+using LZMA
+[ 0x00008200, 0001870b, 0x00020040) <- ffe3e24c
+Clearing Segment: addr: 0x000000000001870b memsz: 0x0000000000007935
+dest 00008200, end 00020040, bouncebuffer 4f579000
+Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000010316c filesz: 0x00000000000482f2
+lb: [0x0000000000100000, 0x0000000000153038)
+segment: [0x0000000000100000, 0x00000000001482f2, 0x000000000020316c)
+ bounce: [0x000000004f579000, 0x000000004f5c12f2, 0x000000004f67c16c)
+Post relocation: addr: 0x000000004f579000 memsz: 0x000000000010316c filesz: 0x00000000000482f2
+using LZMA
+[ 0x4f579000, 4f67c16c, 0x4f67c16c) <- ffe46
+432 bytes lost
\ No newline at end of file diff --git a/docs/t7200q/kernel b/docs/t7200q/kernel new file mode 100644 index 0000000..944735c --- /dev/null +++ b/docs/t7200q/kernel @@ -0,0 +1,1016 @@ +Jan 1 01:00:21 X60Trisquel kernel: imklog 5.8.6, log source = /proc/kmsg started.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Initializing cgroup subsys cpuset
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Initializing cgroup subsys cpu
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Linux version 3.2.0-64-generic (root@devel.trisquel.info) (gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5) ) #1trisquel1 SMP Fri Jun 6 11:49:52 UTC 2014 (Ubuntu 3.2.0-64.97+6.0.1trisquel1-generic 3.2.59-gnu)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] KERNEL supported cpus:
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Intel GenuineIntel
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] AMD AuthenticAMD
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] NSC Geode by NSC
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Cyrix CyrixInstead
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Centaur CentaurHauls
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Transmeta GenuineTMx86
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Transmeta TransmetaCPU
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] UMC UMC UMC UMC
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] BIOS-provided physical RAM map:
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] BIOS-e820: 0000000000000000 - 0000000000001000 type 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] BIOS-e820: 00000000000c0000 - 000000004f6e0000 (usable)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] BIOS-e820: 000000004f6e0000 - 000000004f800000 type 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] BIOS-e820: 000000004f800000 - 0000000050000000 (reserved)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] BIOS-e820: 00000000f0000000 - 00000000f4000000 (reserved)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Notice: NX (Execute Disable) protection cannot be enabled in hardware: non-PAE kernel!
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] NX (Execute Disable) protection: approximated by x86 segment limits
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] SMBIOS 2.7 present.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] DMI: LENOVO 195143U, BIOS t60 05/18/2014
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] last_pfn = 0x4f6e0 max_arch_pfn = 0x100000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] MTRR default type: uncachable
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] MTRR fixed ranges enabled:
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 00000-9FFFF write-back
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] A0000-BFFFF uncachable
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] C0000-FFFFF write-back
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] MTRR variable ranges enabled:
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 0 base 000000000 mask FC0000000 write-back
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 1 base 040000000 mask FF0000000 write-back
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 2 base 04F800000 mask FFF800000 uncachable
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 3 base 0D0000000 mask FF0000000 write-combining
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 4 disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 5 disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 6 disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 7 disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] found SMP MP-table at [c00f0400] f0400
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] initial memory mapped : 0 - 01c00000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Base memory trampoline at [c009b000] 9b000 size 16384
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] init_memory_mapping: 0000000000000000-00000000377fe000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 0000000000 - 0000400000 page 4k
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 0000400000 - 0037400000 page 2M
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 0037400000 - 00377fe000 page 4k
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] kernel direct mapping tables up to 377fe000 @ 1bf8000-1c00000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] RAMDISK: 35c14000 - 36e02000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: RSDP 000f0800 00024 (v02 CORE )
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: XSDT 4f6e28e0 0004C (v01 CORE COREBOOT 00000000 CORE 00000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: HPET 4f6e2a10 00038 (v01 CORE COREBOOT 00000000 CORE 00000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: APIC 4f6e2a50 00068 (v01 CORE COREBOOT 00000000 CORE 00000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: MCFG 4f6e2ac0 0003C (v01 CORE COREBOOT 00000000 CORE 00000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: FACP 4f6e5d70 000F4 (v03 CORE COREBOOT 00000000 CORE 00000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: DSDT 4f6e2b40 03123 (v03 COREv4 COREBOOT 20090419 INTL 20140114)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: FACS 4f6e2b00 00040
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: SSDT 4f6e5e70 00340 (v02 CORE COREBOOT 0000002A CORE 0000002A)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 382MB HIGHMEM available.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 887MB LOWMEM available.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] mapped low ram: 0 - 377fe000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] low ram: 0 - 377fe000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Zone PFN ranges:
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] DMA 0x00000010 -> 0x00001000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Normal 0x00001000 -> 0x000377fe
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] HighMem 0x000377fe -> 0x0004f6e0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Movable zone start PFN for each node
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] early_node_map[2] active PFN ranges
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 0: 0x00000010 -> 0x000000a0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] 0: 0x00000100 -> 0x0004f6e0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] On node 0 totalpages: 325232
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] free_area_init_node: node 0, pgdat c1819ec0, node_mem_map f6e0d200
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] DMA zone: 32 pages used for memmap
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] DMA zone: 0 pages reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] DMA zone: 3952 pages, LIFO batch:0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Normal zone: 1744 pages used for memmap
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Normal zone: 221486 pages, LIFO batch:31
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] HighMem zone: 766 pages used for memmap
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] HighMem zone: 97252 pages, LIFO batch:31
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Using APIC driver default
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: PM-Timer IO Port: 0x508
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 high edge)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: IRQ0 used by override.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: IRQ2 used by override.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: IRQ9 used by override.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Using ACPI (MADT) for SMP configuration information
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] nr_irqs_gsi: 40
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] PM: Registered nosave memory: 0000000000001000 - 0000000000010000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 0000000000100000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Allocating PCI resources starting at 50000000 (gap: 50000000:a0000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Booting paravirtualized kernel on bare hardware
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:2 nr_node_ids:1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] PERCPU: Embedded 13 pages/cpu @f5bfa000 s31616 r0 d21632 u53248
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] pcpu-alloc: s31616 r0 d21632 u53248 alloc=13*4096
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] pcpu-alloc: [0] 0 [0] 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 322690
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Kernel command line: BOOT_IMAGE=(ahci0,1)/vmlinuz root=/dev/sda1 processor.max_cstate=2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Initializing CPU#0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] allocated 5205248 bytes of page_cgroup
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Initializing HighMem for node 0 (000377fe:0004f6e0)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Memory: 1256388k/1301376k available (5647k kernel code, 44540k reserved, 2697k data, 716k init, 392072k highmem)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] virtual kernel memory layout:
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] fixmap : 0xfff16000 - 0xfffff000 ( 932 kB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] pkmap : 0xff800000 - 0xffc00000 (4096 kB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] vmalloc : 0xf7ffe000 - 0xff7fe000 ( 120 MB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] lowmem : 0xc0000000 - 0xf77fe000 ( 887 MB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] .init : 0xc1827000 - 0xc18da000 ( 716 kB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] .data : 0xc1583f04 - 0xc1826600 (2697 kB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] .text : 0xc1000000 - 0xc1583f04 (5647 kB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Hierarchical RCU implementation.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] RCU dyntick-idle grace-period acceleration is enabled.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] NR_IRQS:2304 nr_irqs:512 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] CPU 0 irqstacks, hard=f5008000 soft=f500a000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Extended CMOS year: 12400
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] WARNING: Persistent clock returned invalid value!
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Check your CMOS/BIOS settings.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Console: colour dummy device 80x25
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] console [tty0] enabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] hpet clockevent registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Fast TSC calibration using PIT
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.000000] Detected 1995.017 MHz processor.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004002] Calibrating delay loop (skipped), value calculated using timer frequency.. 3990.03 BogoMIPS (lpj=7980068)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004012] pid_max: default: 32768 minimum: 301
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004038] Security Framework initialized
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004057] AppArmor: AppArmor initialized
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004061] Yama: becoming mindful.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004122] Mount-cache hash table entries: 512
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004262] Initializing cgroup subsys cpuacct
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004271] Initializing cgroup subsys memory
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004282] Initializing cgroup subsys devices
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004286] Initializing cgroup subsys freezer
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004291] Initializing cgroup subsys blkio
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004300] Initializing cgroup subsys perf_event
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004330] CPU: Physical Processor ID: 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004334] CPU: Processor Core ID: 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004340] mce: CPU supports 6 MCE banks
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004350] CPU0: Thermal monitoring enabled (TM2)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.004356] using mwait in idle threads.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.006568] ACPI: Core revision 20110623
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.011507] ftrace: allocating 25532 entries in 50 pages
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.012053] Enabling APIC mode: Flat. Using 1 I/O APICs
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.012516] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.055668] CPU0: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz stepping 06
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] Performance Events: PEBS fmt0-, Core2 events, Intel PMU driver.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] PEBS disabled due to CPU errata.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] ... version: 2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] ... bit width: 40
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] ... generic registers: 2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] ... value mask: 000000ffffffffff
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] ... max period: 000000007fffffff
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] ... fixed-purpose events: 3
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] ... event mask: 0000000700000003
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] NMI watchdog enabled, takes one hw-pmu counter.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] CPU 1 irqstacks, hard=f50cc000 soft=f50ce000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] Booting Node 0, Processors #1 Ok.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.056003] smpboot cpu 1: start_ip = 9b000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.008000] Initializing CPU#1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.144046] NMI watchdog enabled, takes one hw-pmu counter.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.144100] Brought up 2 CPUs
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.144105] Total of 2 processors activated (7979.94 BogoMIPS).
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.146309] devtmpfs: initialized
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.146309] EVM: security.selinux
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.146309] EVM: security.SMACK64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.146309] EVM: security.capability
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.146309] print_constraints: dummy:
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.146309] RTC time: 0:48:49, date: 141/25/41
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.146309] NET: Registered protocol family 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.148069] Trying to unpack rootfs image as initramfs...
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.148133] EISA bus registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.148171] ACPI: bus type pci registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.148242] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf0000000-0xf3ffffff] (base 0xf0000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.148251] PCI: MMCONFIG at [mem 0xf0000000-0xf3ffffff] reserved in E820
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.148256] PCI: Using MMCONFIG for extended config space
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.148260] PCI: Using configuration type 1 for base access
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.149700] bio: create slab <bio-0> at 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.149803] ACPI: Added _OSI(Module Device)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.149809] ACPI: Added _OSI(Processor Device)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.149814] ACPI: Added _OSI(3.0 _SCP Extensions)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.149818] ACPI: Added _OSI(Processor Aggregator Device)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.151084] ACPI: EC: Look up EC in DSDT
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.153408] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.153818] ACPI: Interpreter enabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.153828] ACPI: (supports S0 S3 S4 S5)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.153855] ACPI: Using IOAPIC for interrupt routing
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.158603] ACPI: EC: GPE = 0x1c, I/O: command/status = 0x66, data = 0x62
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160296] ACPI: ACPI Dock Station Driver: 1 docks/bays found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160303] HEST: Table not found.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160309] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160419] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160572] pci_root PNP0A08:00: host bridge window [io 0x0000-0x0cf7]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160579] pci_root PNP0A08:00: host bridge window [io 0x0d00-0xffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160585] pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160591] pci_root PNP0A08:00: host bridge window [mem 0x000c0000-0x000c3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160598] pci_root PNP0A08:00: host bridge window [mem 0x000c4000-0x000c7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160604] pci_root PNP0A08:00: host bridge window [mem 0x000c8000-0x000cbfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160610] pci_root PNP0A08:00: host bridge window [mem 0x000cc000-0x000cffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160617] pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000d3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160623] pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160629] pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160636] pci_root PNP0A08:00: host bridge window [mem 0x000dc000-0x000dffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160642] pci_root PNP0A08:00: host bridge window [mem 0x000e0000-0x000e3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160648] pci_root PNP0A08:00: host bridge window [mem 0x000e4000-0x000e7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160655] pci_root PNP0A08:00: host bridge window [mem 0x000e8000-0x000ebfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160661] pci_root PNP0A08:00: host bridge window [mem 0x000ec000-0x000effff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160667] pci_root PNP0A08:00: host bridge window [mem 0x000f0000-0x000fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160674] pci_root PNP0A08:00: host bridge window [mem 0x50000000-0xfebfffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160680] pci_root PNP0A08:00: host bridge window [mem 0xfed40000-0xfed44fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160704] pci 0000:00:00.0: [8086:27a0] type 0 class 0x000600
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160765] pci 0000:00:02.0: [8086:27a2] type 0 class 0x000300
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160779] pci 0000:00:02.0: reg 10: [mem 0xe4300000-0xe437ffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160787] pci 0000:00:02.0: reg 14: [io 0x50a0-0x50a7]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160794] pci 0000:00:02.0: reg 18: [mem 0xd0000000-0xdfffffff pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160802] pci 0000:00:02.0: reg 1c: [mem 0xe4400000-0xe443ffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160853] pci 0000:00:02.1: [8086:27a6] type 0 class 0x000380
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160864] pci 0000:00:02.1: reg 10: [mem 0xe4380000-0xe43fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.160982] pci 0000:00:1b.0: [8086:27d8] type 0 class 0x000403
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161007] pci 0000:00:1b.0: reg 10: [mem 0xe4440000-0xe4443fff 64bit]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161120] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161126] pci 0000:00:1b.0: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161157] pci 0000:00:1c.0: [8086:27d0] type 1 class 0x000604
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161274] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161280] pci 0000:00:1c.0: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161314] pci 0000:00:1c.1: [8086:27d2] type 1 class 0x000604
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161431] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161437] pci 0000:00:1c.1: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161471] pci 0000:00:1c.2: [8086:27d4] type 1 class 0x000604
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161586] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161591] pci 0000:00:1c.2: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161625] pci 0000:00:1c.3: [8086:27d6] type 1 class 0x000604
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161741] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161747] pci 0000:00:1c.3: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161783] pci 0000:00:1d.0: [8086:27c8] type 0 class 0x000c03
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161867] pci 0000:00:1d.0: reg 20: [io 0x5000-0x501f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.161926] pci 0000:00:1d.1: [8086:27c9] type 0 class 0x000c03
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162006] pci 0000:00:1d.1: reg 20: [io 0x5020-0x503f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162053] pci 0000:00:1d.2: [8086:27ca] type 0 class 0x000c03
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162113] pci 0000:00:1d.2: reg 20: [io 0x5040-0x505f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162158] pci 0000:00:1d.3: [8086:27cb] type 0 class 0x000c03
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162218] pci 0000:00:1d.3: reg 20: [io 0x5060-0x507f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162275] pci 0000:00:1d.7: [8086:27cc] type 0 class 0x000c03
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162301] pci 0000:00:1d.7: reg 10: [mem 0xe4444000-0xe44443ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162416] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162423] pci 0000:00:1d.7: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162448] pci 0000:00:1e.0: [8086:2448] type 1 class 0x000604
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162553] pci 0000:00:1f.0: [8086:27b9] type 0 class 0x000601
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162677] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 1 PIO at 1600 (mask 007f)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162686] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 2 PIO at 15e0 (mask 000f)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162694] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 3 PIO at 1680 (mask 001f)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162760] pci 0000:00:1f.1: [8086:27df] type 0 class 0x000101
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162779] pci 0000:00:1f.1: reg 10: [io 0x50a8-0x50af]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162792] pci 0000:00:1f.1: reg 14: [io 0x50c8-0x50cb]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162805] pci 0000:00:1f.1: reg 18: [io 0x50b0-0x50b7]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162818] pci 0000:00:1f.1: reg 1c: [io 0x50cc-0x50cf]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162832] pci 0000:00:1f.1: reg 20: [io 0x5080-0x508f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162887] pci 0000:00:1f.2: [8086:27c5] type 0 class 0x000106
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162912] pci 0000:00:1f.2: reg 10: [io 0x50b8-0x50bf]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162925] pci 0000:00:1f.2: reg 14: [io 0x50d0-0x50d3]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162939] pci 0000:00:1f.2: reg 18: [io 0x50c0-0x50c7]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162952] pci 0000:00:1f.2: reg 1c: [io 0x50d4-0x50d7]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162965] pci 0000:00:1f.2: reg 20: [io 0x5090-0x509f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.162979] pci 0000:00:1f.2: reg 24: [mem 0xe4444400-0xe44447ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163038] pci 0000:00:1f.2: PME# supported from D3hot
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163044] pci 0000:00:1f.2: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163066] pci 0000:00:1f.3: [8086:27da] type 0 class 0x000c05
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163145] pci 0000:00:1f.3: reg 20: [io 0x0400-0x041f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163296] pci 0000:01:00.0: [8086:109a] type 0 class 0x000200
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163328] pci 0000:01:00.0: reg 10: [mem 0xe4100000-0xe411ffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163372] pci 0000:01:00.0: reg 18: [io 0x4000-0x401f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163563] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163572] pci 0000:01:00.0: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163607] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163633] pci 0000:00:1c.0: PCI bridge to [bus 01-01]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163641] pci 0000:00:1c.0: bridge window [io 0x4000-0x4fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163646] pci 0000:00:1c.0: bridge window [mem 0xe4100000-0xe41fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163782] pci 0000:02:00.0: [8086:4227] type 0 class 0x000280
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.163837] pci 0000:02:00.0: reg 10: [mem 0xe4200000-0xe4200fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164271] pci 0000:02:00.0: PME# supported from D0 D3hot
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164284] pci 0000:02:00.0: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164347] pci 0000:02:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164381] pci 0000:00:1c.1: PCI bridge to [bus 02-02]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164391] pci 0000:00:1c.1: bridge window [mem 0xe4200000-0xe42fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164465] pci 0000:00:1c.2: PCI bridge to [bus 03-03]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164544] pci 0000:00:1c.3: PCI bridge to [bus 04-04]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164607] pci 0000:05:00.0: [104c:ac56] type 2 class 0x000607
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164634] pci 0000:05:00.0: reg 10: [mem 0xe2000000-0xe2000fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164681] pci 0000:05:00.0: supports D1 D2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164684] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164690] pci 0000:05:00.0: PME# disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164760] pci 0000:00:1e.0: PCI bridge to [bus 05-05] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164769] pci 0000:00:1e.0: bridge window [io 0x2000-0x3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164774] pci 0000:00:1e.0: bridge window [mem 0xe0000000-0xe20fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164783] pci 0000:00:1e.0: bridge window [mem 0xe2100000-0xe40fffff 64bit pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164786] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164789] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164792] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164795] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000c3fff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164798] pci 0000:00:1e.0: bridge window [mem 0x000c4000-0x000c7fff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164801] pci 0000:00:1e.0: bridge window [mem 0x000c8000-0x000cbfff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164804] pci 0000:00:1e.0: bridge window [mem 0x000cc000-0x000cffff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164807] pci 0000:00:1e.0: bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164810] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164813] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164816] pci 0000:00:1e.0: bridge window [mem 0x000dc000-0x000dffff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164819] pci 0000:00:1e.0: bridge window [mem 0x000e0000-0x000e3fff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164822] pci 0000:00:1e.0: bridge window [mem 0x000e4000-0x000e7fff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164825] pci 0000:00:1e.0: bridge window [mem 0x000e8000-0x000ebfff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164828] pci 0000:00:1e.0: bridge window [mem 0x000ec000-0x000effff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164831] pci 0000:00:1e.0: bridge window [mem 0x000f0000-0x000fffff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164834] pci 0000:00:1e.0: bridge window [mem 0x50000000-0xfebfffff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164837] pci 0000:00:1e.0: bridge window [mem 0xfed40000-0xfed44fff] (subtractive decode)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164841] pci 0000:05:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164897] pci_bus 0000:06: [bus 06-09] partially hidden behind transparent bridge 0000:05 [bus 05-05]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164938] pci_bus 0000:00: on NUMA node 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.164943] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.165104] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP01._PRT]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.165158] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP02._PRT]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.165209] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP03._PRT]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.165261] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP04._PRT]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.165337] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCIB._PRT]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.165496] pci0000:00: Requesting ACPI _OSC control (0x1d)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.165557] pci0000:00: ACPI _OSC control (0x1d) granted
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.171939] ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 12 14 15) *11
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172017] ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 *11 12 14 15)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172082] ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 10 12 14 15) *11
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172146] ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 *11 12 14 15)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172208] ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 7 10 12 14 15) *11
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172271] ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 *11 12 14 15)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172334] ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 10 12 14 15) *11
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172398] ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 4 5 6 7 *11 12 14 15)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172528] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172549] vgaarb: loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172552] vgaarb: bridge control possible 0000:00:02.0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172695] i2c-core: driver [aat2870] using legacy suspend method
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172700] i2c-core: driver [aat2870] using legacy resume method
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.172808] SCSI subsystem initialized
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.176123] libata version 3.00 loaded.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.176123] usbcore: registered new interface driver usbfs
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.176123] usbcore: registered new interface driver hub
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.176139] usbcore: registered new device driver usb
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.176258] PCI: Using ACPI for IRQ routing
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.178840] PCI: pci_cache_line_size set to 64 bytes
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.178967] reserve RAM buffer: 000000004f6e0000 - 000000004fffffff
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.179098] NetLabel: Initializing
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.179103] NetLabel: domain hash size = 128
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.179106] NetLabel: protocols = UNLABELED CIPSOv4
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.179121] NetLabel: unlabeled traffic allowed by default
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.179198] HPET: 3 timers in total, 0 timers will be used for per-cpu timer
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.179209] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.179218] hpet0: 3 comparators, 64-bit 14.318180 MHz counter
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.188071] Switching to clocksource hpet
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.197850] AppArmor: AppArmor Filesystem Enabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.197891] pnp: PnP ACPI init
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.197915] ACPI: bus type pnp registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198032] pnp 00:00: [bus 00-ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198036] pnp 00:00: [io 0x0000-0x0cf7 window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198039] pnp 00:00: [io 0x0cf8-0x0cff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198042] pnp 00:00: [io 0x0d00-0xffff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198045] pnp 00:00: [mem 0x000a0000-0x000bffff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198047] pnp 00:00: [mem 0x000c0000-0x000c3fff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198050] pnp 00:00: [mem 0x000c4000-0x000c7fff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198053] pnp 00:00: [mem 0x000c8000-0x000cbfff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198056] pnp 00:00: [mem 0x000cc000-0x000cffff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198059] pnp 00:00: [mem 0x000d0000-0x000d3fff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198061] pnp 00:00: [mem 0x000d4000-0x000d7fff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198064] pnp 00:00: [mem 0x000d8000-0x000dbfff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198067] pnp 00:00: [mem 0x000dc000-0x000dffff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198069] pnp 00:00: [mem 0x000e0000-0x000e3fff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198072] pnp 00:00: [mem 0x000e4000-0x000e7fff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198075] pnp 00:00: [mem 0x000e8000-0x000ebfff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198078] pnp 00:00: [mem 0x000ec000-0x000effff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198081] pnp 00:00: [mem 0x000f0000-0x000fffff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198083] pnp 00:00: [mem 0x50000000-0xfebfffff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198086] pnp 00:00: [mem 0xfed40000-0xfed44fff window]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198171] pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198195] pnp 00:01: [mem 0xfed1c000-0xfed1ffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198198] pnp 00:01: [mem 0xfed14000-0xfed17fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198200] pnp 00:01: [mem 0xfed18000-0xfed18fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198203] pnp 00:01: [mem 0xfed19000-0xfed19fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198208] pnp 00:01: [mem 0xf0000000-0xf3ffffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198211] pnp 00:01: [mem 0xfed20000-0xfed3ffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198213] pnp 00:01: [mem 0xfed40000-0xfed44fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198216] pnp 00:01: [mem 0xfed45000-0xfed8ffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198285] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198292] system 00:01: [mem 0xfed14000-0xfed17fff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198298] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198304] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198310] system 00:01: [mem 0xf0000000-0xf3ffffff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198315] system 00:01: [mem 0xfed20000-0xfed3ffff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198321] system 00:01: [mem 0xfed40000-0xfed44fff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198327] system 00:01: [mem 0xfed45000-0xfed8ffff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198333] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198775] pnp 00:02: [io 0x0000-0x001f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198778] pnp 00:02: [io 0x0081-0x0091]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198780] pnp 00:02: [io 0x0093-0x009f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198782] pnp 00:02: [io 0x00c0-0x00df]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198785] pnp 00:02: [dma 4]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198839] pnp 00:02: Plug and Play ACPI device, IDs PNP0200 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198850] pnp 00:03: [mem 0xff000000-0xffffffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198901] pnp 00:03: Plug and Play ACPI device, IDs INT0800 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.198984] pnp 00:04: [mem 0xfed00000-0xfed003ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199065] system 00:04: [mem 0xfed00000-0xfed003ff] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199073] system 00:04: Plug and Play ACPI device, IDs PNP0103 PNP0c01 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199087] pnp 00:05: [io 0x00f0]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199100] pnp 00:05: [irq 13]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199154] pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199167] pnp 00:06: [io 0x002e-0x002f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199169] pnp 00:06: [io 0x004e-0x004f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199172] pnp 00:06: [io 0x0061]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199174] pnp 00:06: [io 0x0063]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199176] pnp 00:06: [io 0x0065]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199178] pnp 00:06: [io 0x0067]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199180] pnp 00:06: [io 0x0080]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199182] pnp 00:06: [io 0x0092]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199185] pnp 00:06: [io 0x00b2-0x00b3]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199187] pnp 00:06: [io 0x0800-0x080f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199189] pnp 00:06: [io 0x0500-0x057f]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199192] pnp 00:06: [io 0x0480-0x04bf]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199277] system 00:06: [io 0x0800-0x080f] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199284] system 00:06: [io 0x0500-0x057f] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199290] system 00:06: [io 0x0480-0x04bf] has been reserved
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199296] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199307] pnp 00:07: [io 0x0070-0x0077]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199361] pnp 00:07: Plug and Play ACPI device, IDs PNP0b00 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199382] pnp 00:08: [io 0x0060]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199384] pnp 00:08: [io 0x0064]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199391] pnp 00:08: [irq 1]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199447] pnp 00:08: Plug and Play ACPI device, IDs PNP0303 PNP030b (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199469] pnp 00:09: [irq 12]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199527] pnp 00:09: Plug and Play ACPI device, IDs PNP0f13 (active)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199570] pnp: PnP ACPI: found 10 devices
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199575] ACPI: ACPI bus type pnp unregistered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.199581] PnPBIOS: Disabled by ACPI PNP
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236427] PCI: max bus depth: 2 pci_try_num: 3
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236504] pci 0000:00:1c.0: BAR 15: assigned [mem 0x50000000-0x501fffff 64bit pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236515] pci 0000:00:1c.0: PCI bridge to [bus 01-01]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236522] pci 0000:00:1c.0: bridge window [io 0x4000-0x4fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236532] pci 0000:00:1c.0: bridge window [mem 0xe4100000-0xe41fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236541] pci 0000:00:1c.0: bridge window [mem 0x50000000-0x501fffff 64bit pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236553] pci 0000:00:1c.1: PCI bridge to [bus 02-02]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236562] pci 0000:00:1c.1: bridge window [mem 0xe4200000-0xe42fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236576] pci 0000:00:1c.2: PCI bridge to [bus 03-03]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236594] pci 0000:00:1c.3: PCI bridge to [bus 04-04]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236616] pci 0000:05:00.0: BAR 16: assigned [mem 0x54000000-0x57ffffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236625] pci 0000:05:00.0: BAR 15: assigned [mem 0x58000000-0x5bffffff pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236632] pci 0000:05:00.0: BAR 14: assigned [io 0x2000-0x20ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236637] pci 0000:05:00.0: BAR 13: assigned [io 0x2400-0x24ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236643] pci 0000:05:00.0: CardBus bridge to [bus 06-09]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236648] pci 0000:05:00.0: bridge window [io 0x2400-0x24ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236657] pci 0000:05:00.0: bridge window [io 0x2000-0x20ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236665] pci 0000:05:00.0: bridge window [mem 0x58000000-0x5bffffff pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236675] pci 0000:05:00.0: bridge window [mem 0x54000000-0x57ffffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236684] pci 0000:00:1e.0: PCI bridge to [bus 05-05]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236690] pci 0000:00:1e.0: bridge window [io 0x2000-0x3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236700] pci 0000:00:1e.0: bridge window [mem 0xe0000000-0xe20fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236708] pci 0000:00:1e.0: bridge window [mem 0xe2100000-0xe40fffff 64bit pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236748] pci 0000:00:1c.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236761] pci 0000:00:1c.0: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236774] pci 0000:00:1c.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236785] pci 0000:00:1c.1: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236798] pci 0000:00:1c.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236809] pci 0000:00:1c.2: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236820] pci 0000:00:1c.3: PCI INT D -> GSI 23 (level, low) -> IRQ 23
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236832] pci 0000:00:1c.3: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236838] pci 0000:00:1e.0: enabling device (0104 -> 0107)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236849] pci 0000:00:1e.0: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236863] pci 0000:05:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236879] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236882] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236885] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236888] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236890] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236893] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236896] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236899] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236902] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236904] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236907] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236910] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236913] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236916] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236918] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236921] pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236924] pci_bus 0000:00: resource 20 [mem 0x50000000-0xfebfffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236927] pci_bus 0000:00: resource 21 [mem 0xfed40000-0xfed44fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236930] pci_bus 0000:01: resource 0 [io 0x4000-0x4fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236932] pci_bus 0000:01: resource 1 [mem 0xe4100000-0xe41fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236935] pci_bus 0000:01: resource 2 [mem 0x50000000-0x501fffff 64bit pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236939] pci_bus 0000:02: resource 1 [mem 0xe4200000-0xe42fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236942] pci_bus 0000:05: resource 0 [io 0x2000-0x3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236944] pci_bus 0000:05: resource 1 [mem 0xe0000000-0xe20fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236947] pci_bus 0000:05: resource 2 [mem 0xe2100000-0xe40fffff 64bit pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236950] pci_bus 0000:05: resource 4 [io 0x0000-0x0cf7]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236953] pci_bus 0000:05: resource 5 [io 0x0d00-0xffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236955] pci_bus 0000:05: resource 6 [mem 0x000a0000-0x000bffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236958] pci_bus 0000:05: resource 7 [mem 0x000c0000-0x000c3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236961] pci_bus 0000:05: resource 8 [mem 0x000c4000-0x000c7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236964] pci_bus 0000:05: resource 9 [mem 0x000c8000-0x000cbfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236966] pci_bus 0000:05: resource 10 [mem 0x000cc000-0x000cffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236969] pci_bus 0000:05: resource 11 [mem 0x000d0000-0x000d3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236972] pci_bus 0000:05: resource 12 [mem 0x000d4000-0x000d7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236975] pci_bus 0000:05: resource 13 [mem 0x000d8000-0x000dbfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236977] pci_bus 0000:05: resource 14 [mem 0x000dc000-0x000dffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236980] pci_bus 0000:05: resource 15 [mem 0x000e0000-0x000e3fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236983] pci_bus 0000:05: resource 16 [mem 0x000e4000-0x000e7fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236986] pci_bus 0000:05: resource 17 [mem 0x000e8000-0x000ebfff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236988] pci_bus 0000:05: resource 18 [mem 0x000ec000-0x000effff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236991] pci_bus 0000:05: resource 19 [mem 0x000f0000-0x000fffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236994] pci_bus 0000:05: resource 20 [mem 0x50000000-0xfebfffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.236997] pci_bus 0000:05: resource 21 [mem 0xfed40000-0xfed44fff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237000] pci_bus 0000:06: resource 0 [io 0x2400-0x24ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237002] pci_bus 0000:06: resource 1 [io 0x2000-0x20ff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237005] pci_bus 0000:06: resource 2 [mem 0x58000000-0x5bffffff pref]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237008] pci_bus 0000:06: resource 3 [mem 0x54000000-0x57ffffff]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237062] NET: Registered protocol family 2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237150] IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237430] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.237952] TCP bind hash table entries: 65536 (order: 7, 524288 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238205] TCP: Hash tables configured (established 131072 bind 65536)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238210] TCP reno registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238215] UDP hash table entries: 512 (order: 2, 16384 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238227] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238326] NET: Registered protocol family 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238349] pci 0000:00:02.0: Boot video device
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238379] pci 0000:00:1d.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238409] pci 0000:00:1d.0: PCI INT A disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238430] pci 0000:00:1d.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238458] pci 0000:00:1d.1: PCI INT B disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238473] pci 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238500] pci 0000:00:1d.2: PCI INT C disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238515] pci 0000:00:1d.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238543] pci 0000:00:1d.3: PCI INT D disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238556] pci 0000:00:1d.7: PCI INT D -> GSI 19 (level, low) -> IRQ 19
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238595] pci 0000:00:1d.7: PCI INT D disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.238634] PCI: CLS 64 bytes, default 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.239096] audit: initializing netlink socket (disabled)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.239111] type=2000 audit(0.232:1): initialized
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.262811] highmem bounce pool size: 64 pages
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.262823] HugeTLB registered 4 MB page size, pre-allocated 0 pages
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.265206] VFS: Disk quotas dquot_6.5.2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.265284] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.265965] fuse init (API version 7.17)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266087] msgmni has been set to 1688
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266467] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266502] io scheduler noop registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266507] io scheduler deadline registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266517] io scheduler cfq registered (default)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266681] pcieport 0000:00:1c.0: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266747] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266877] pcieport 0000:00:1c.1: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.266935] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267051] pcieport 0000:00:1c.2: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267109] pcieport 0000:00:1c.2: irq 42 for MSI/MSI-X
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267217] pcieport 0000:00:1c.3: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267275] pcieport 0000:00:1c.3: irq 43 for MSI/MSI-X
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267417] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267423] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267432] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267458] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267463] pci 0000:02:00.0: Signaling PME through PCIe PME interrupt
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267472] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267498] pcieport 0000:00:1c.2: Signaling PME through PCIe PME interrupt
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267507] pcie_pme 0000:00:1c.2:pcie01: service driver pcie_pme loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267534] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267542] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267565] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267610] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 27d0 ss_vid 17aa ss_did 2001
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267646] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267656] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.267769] efifb: probing for efifb
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.268537] efifb: framebuffer at 0xd0000000, mapped to 0xf8080000, using 5824k, total 5824k
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.268545] efifb: mode is 1408x1050x32, linelength=5632, pages=1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.268549] efifb: scrolling: redraw
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.268554] efifb: Truecolor: size=0:8:8:8, shift=0:16:8:0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.274944] Console: switching to colour frame buffer device 176x65
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.281275] fb0: EFI VGA frame buffer device
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.281330] intel_idle: MWAIT substates: 0x22220
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.281333] intel_idle: does not run on family 6 model 15
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.281498] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.281699] ACPI: AC Adapter [AC] (on-line)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.281870] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:23/PNP0C09:00/PNP0C0E:00/input/input0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.281972] ACPI: Sleep Button [SLPB]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.282057] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:23/PNP0C09:00/PNP0C0D:00/input/input1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.282264] ACPI: Lid Switch [LID]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.282347] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.282405] ACPI: Power Button [PWRF]
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.282571] ACPI: processor limited to max C-state 2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.283553] Monitor-Mwait will be used to enter C-1 state
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.283562] Marking TSC unstable due to TSC halts in idle
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.283613] ACPI: acpi_idle registered with cpuidle
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.293926] thermal LNXTHERM:00: registered as thermal_zone0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.293983] ACPI: Thermal Zone [THM0] (40 C)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294410] thermal LNXTHERM:01: registered as thermal_zone1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294454] ACPI: Thermal Zone [THM1] (28 C)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294523] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294605] ACPI: Battery Slot [BAT0] (battery present)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294651] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294727] ACPI: Battery Slot [BAT1] (battery absent)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294831] ERST: Table is not found!
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294861] GHES: HEST is not enabled!
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.294994] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.298487] isapnp: Scanning for PnP cards...
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.316375] ACPI: Battery Slot [BAT0] (battery present)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.391299] ACPI: Battery Slot [BAT1] (battery absent)
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.606404] Freeing initrd memory: 18360k freed
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.653171] isapnp: No Plug & Play device found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.724574] Linux agpgart interface v0.103
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.724714] agpgart-intel 0000:00:00.0: Intel 945GM Chipset
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.724835] agpgart-intel 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.726674] agpgart-intel 0000:00:00.0: detected 8192K stolen memory
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.726880] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.728923] brd: module loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.729972] loop: module loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.730140] ahci 0000:00:1f.2: version 3.0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.730155] ahci 0000:00:1f.2: PCI INT B -> GSI 16 (level, low) -> IRQ 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.730261] ahci 0000:00:1f.2: irq 44 for MSI/MSI-X
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.730299] ahci: SSS flag set, parallel bus scan disabled
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.730368] ahci 0000:00:1f.2: AHCI 0001.0100 32 slots 4 ports 1.5 Gbps 0x1 impl SATA mode
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.730431] ahci 0000:00:1f.2: flags: 64bit ncq ilck stag pm led clo pmp pio slum part
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.730491] ahci 0000:00:1f.2: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.731030] scsi0 : ahci
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.731178] scsi1 : ahci
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.733794] scsi2 : ahci
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.736368] scsi3 : ahci
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.738931] ata1: SATA max UDMA/133 abar m1024@0xe4444400 port 0xe4444500 irq 44
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.741432] ata2: DUMMY
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.743878] ata3: DUMMY
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.746311] ata4: DUMMY
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.748803] ata_piix 0000:00:1f.1: version 2.13
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.748813] ata_piix 0000:00:1f.1: PCI INT C -> GSI 16 (level, low) -> IRQ 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.751329] ata_piix 0000:00:1f.1: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.751710] scsi4 : ata_piix
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.754256] scsi5 : ata_piix
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.756851] ata5: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x5080 irq 14
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.759309] ata6: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x5088 irq 15
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.761937] ata6: port disabled--ignoring
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.762348] Fixed MDIO Bus: probed
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.764801] tun: Universal TUN/TAP device driver, 1.6
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.767248] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.769775] PPP generic driver version 2.4.2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.772354] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.774809] ehci_hcd 0000:00:1d.7: PCI INT D -> GSI 19 (level, low) -> IRQ 19
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.777270] ehci_hcd 0000:00:1d.7: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.777274] ehci_hcd 0000:00:1d.7: EHCI Host Controller
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.779744] ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.782180] ehci_hcd 0000:00:1d.7: using broken periodic workaround
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.784592] ehci_hcd 0000:00:1d.7: debug port 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.790845] ehci_hcd 0000:00:1d.7: cache line size of 64 is not supported
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.790863] ehci_hcd 0000:00:1d.7: irq 19, io mem 0xe4444000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.808020] ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.810576] hub 1-0:1.0: USB hub found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.812934] hub 1-0:1.0: 8 ports detected
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.815373] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.817708] uhci_hcd: USB Universal Host Controller Interface driver
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.820027] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.822306] uhci_hcd 0000:00:1d.0: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.822310] uhci_hcd 0000:00:1d.0: UHCI Host Controller
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.824585] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.826815] uhci_hcd 0000:00:1d.0: irq 16, io base 0x00005000
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.829148] hub 2-0:1.0: USB hub found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.831291] hub 2-0:1.0: 2 ports detected
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.833488] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.835645] uhci_hcd 0000:00:1d.1: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.835649] uhci_hcd 0000:00:1d.1: UHCI Host Controller
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.837841] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.840032] uhci_hcd 0000:00:1d.1: irq 17, io base 0x00005020
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.842322] hub 3-0:1.0: USB hub found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.844458] hub 3-0:1.0: 2 ports detected
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.846642] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.848776] uhci_hcd 0000:00:1d.2: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.848780] uhci_hcd 0000:00:1d.2: UHCI Host Controller
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.850902] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.853002] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00005040
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.855177] hub 4-0:1.0: USB hub found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.857208] hub 4-0:1.0: 2 ports detected
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.859296] uhci_hcd 0000:00:1d.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.861357] uhci_hcd 0000:00:1d.3: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.861362] uhci_hcd 0000:00:1d.3: UHCI Host Controller
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.863426] uhci_hcd 0000:00:1d.3: new USB bus registered, assigned bus number 5
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.865486] uhci_hcd 0000:00:1d.3: irq 19, io base 0x00005060
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.867693] hub 5-0:1.0: USB hub found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.869747] hub 5-0:1.0: 2 ports detected
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.871905] usbcore: registered new interface driver libusual
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.874020] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.887190] serio: i8042 KBD port at 0x60,0x64 irq 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.889281] serio: i8042 AUX port at 0x60,0x64 irq 12
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.891506] mousedev: PS/2 mouse device common for all mice
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.893793] rtc_cmos 00:07: RTC can wake from S4
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.895987] rtc_cmos 00:07: rtc core: registered rtc_cmos as rtc0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.898139] rtc0: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.900318] device-mapper: uevent: version 1.0.3
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.902496] device-mapper: ioctl: 4.22.0-ioctl (2011-10-19) initialised: dm-devel@redhat.com
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.904621] EISA: Probing bus 0 at eisa.0
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.906698] EISA: Cannot allocate resource for mainboard
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.908766] Cannot allocate resource for EISA slot 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.910917] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.913092] Cannot allocate resource for EISA slot 2
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.915644] Cannot allocate resource for EISA slot 3
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.917781] Cannot allocate resource for EISA slot 4
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.919882] Cannot allocate resource for EISA slot 5
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.922780] Cannot allocate resource for EISA slot 6
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.924878] Cannot allocate resource for EISA slot 7
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.926922] Cannot allocate resource for EISA slot 8
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.928944] EISA: Detected 0 cards.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.930972] cpufreq-nforce2: No nForce2 chipset.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.933066] cpuidle: using governor ladder
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.935184] cpuidle: using governor menu
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.937182] EFI Variables Facility v0.08 2004-May-17
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.939481] TCP cubic registered
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.940394] ata5.00: ATAPI: HL-DT-ST DVDRAM GSA-4083N, 1.08, max UDMA/33
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.943623] NET: Registered protocol family 10
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.946335] NET: Registered protocol family 17
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.948310] Registering the dns_resolver key type
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.950288] Using IPI No-Shortcut mode
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.952401] PM: Hibernation image not present or could not be loaded.
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.952414] registered taskstats version 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.956293] ata5.00: configured for UDMA/33
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.963685] Magic number: 9:510:811
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.965744] rtc_cmos 00:07: hctosys: invalid date/time
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.968437] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
+Jan 1 01:00:21 X60Trisquel kernel: [ 0.970411] EDD information not available.
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.244058] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.286258] ata1.00: ATA-8: WDC WD2500BEVT-08A23T1, 02.01A02, max UDMA/133
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.288362] ata1.00: 488397168 sectors, multi 0: LBA48 NCQ (depth 31/32), AA
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.291943] ata1.00: configured for UDMA/133
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.294116] scsi 0:0:0:0: Direct-Access ATA WDC WD2500BEVT-0 02.0 PQ: 0 ANSI: 5
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.296317] sd 0:0:0:0: [sda] 488397168 512-byte logical blocks: (250 GB/232 GiB)
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.296350] sd 0:0:0:0: Attached scsi generic sg0 type 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.300527] sd 0:0:0:0: [sda] Write Protect is off
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.302606] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.302631] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.306560] scsi 4:0:0:0: CD-ROM HL-DT-ST DVDRAM GSA-4083N 1.08 PQ: 0 ANSI: 5
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.347158] sda: sda1 sda2 < sda5 >
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.349797] sd 0:0:0:0: [sda] Attached SCSI disk
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.422601] sr0: scsi3-mmc drive: 24x/24x writer dvd-ram cd/rw xa/form2 cdda tray
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.424845] cdrom: Uniform CD-ROM driver Revision: 3.20
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.427113] sr 4:0:0:0: Attached scsi CD-ROM sr0
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.427295] sr 4:0:0:0: Attached scsi generic sg1 type 5
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.429551] Freeing unused kernel memory: 716k freed
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.431913] Write protecting the kernel text: 5648k
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.434083] Write protecting the kernel read-only data: 2256k
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.530584] e1000e: Intel(R) PRO/1000 Network Driver - 1.5.1-k
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.532749] e1000e: Copyright(c) 1999 - 2011 Intel Corporation.
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.537194] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input4
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.545766] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no)
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.549902] e1000e 0000:01:00.0: Disabling ASPM L0s L1
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.566940] e1000e 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.571903] e1000e 0000:01:00.0: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.572139] e1000e 0000:01:00.0: irq 45 for MSI/MSI-X
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.580288] [drm] Initialized drm 1.1.0 20060810
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.588073] usb 3-1: new full-speed USB device number 2 using uhci_hcd
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.598435] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.600603] i915 0000:00:02.0: setting latency timer to 64
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.601011] checking generic (d0000000 5b0000) vs hw (d0000000 10000000)
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.601014] fb: conflicting fb hw usage inteldrmfb vs EFI VGA - removing generic driver
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.603192] Console: switching to colour dummy device 80x25
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.626656] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.626664] [drm] Driver supports precise vblank timestamp query.
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.626676] i915 0000:00:02.0: Invalid ROM contents
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.626681] [drm:intel_parse_bios] *ERROR* VBT signature missing
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.626685] [drm] failed to find VBIOS tables
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.626721] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.696892] e1000e 0000:01:00.0: eth0: (PCI Express:2.5GT/s:Width x1) 00:16:41:12:8b:29
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.696902] e1000e 0000:01:00.0: eth0: Intel(R) PRO/1000 Network Connection
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.696982] e1000e 0000:01:00.0: eth0: MAC: 2, PHY: 2, PBA No: 005301-003
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.875525] [drm] initialized overlay support
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.875556] [drm] capturing error event; look for more information in /debug/dri/0/i915_error_state
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.876336] render error detected, EIR: 0x00000010
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.876341] page table error
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.876344] PGTBL_ER: 0x00000012
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.876350] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.876361] render error detected, EIR: 0x00000010
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.876365] page table error
+Jan 1 01:00:21 X60Trisquel kernel: [ 1.876368] PGTBL_ER: 0x00000012
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.004061] usb 5-1: new full-speed USB device number 2 using uhci_hcd
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.097438] fbcon: inteldrmfb (fb0) is primary device
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.175114] Console: switching to colour frame buffer device 175x65
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.181718] fb0: inteldrmfb frame buffer device
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.181752] drm: registered panic notifier
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.182937] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.420039] usb 5-2: new full-speed USB device number 3 using uhci_hcd
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.774369] Btrfs loaded
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.780814] xor: automatically using best checksumming function: pIII_sse
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.800017] pIII_sse : 7305.000 MB/sec
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.800047] xor: using function: pIII_sse (7305.000 MB/sec)
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.800767] device-mapper: dm-raid45: initialized v0.2594b
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.802567] md: linear personality registered for level -1
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.804406] md: multipath personality registered for level -4
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.806182] md: raid0 personality registered for level 0
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.808268] md: raid1 personality registered for level 1
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.810069] async_tx: api initialized (async)
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.876067] raid6: int32x1 750 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 2.944104] raid6: int32x2 641 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.012084] raid6: int32x4 589 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.080099] raid6: int32x8 670 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.148037] raid6: mmxx1 2613 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.216018] raid6: mmxx2 2855 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.284033] raid6: sse1x1 1574 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.352020] raid6: sse1x2 2166 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.420024] raid6: sse2x1 2869 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.488018] raid6: sse2x2 3812 MB/s
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.488045] raid6: using algorithm sse2x2 (3812 MB/s)
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.489021] md: raid6 personality registered for level 6
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.489061] md: raid5 personality registered for level 5
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.489098] md: raid4 personality registered for level 4
+Jan 1 01:00:21 X60Trisquel kernel: [ 3.494894] md: raid10 personality registered for level 10
+Jan 1 01:00:21 X60Trisquel kernel: [ 9.071462] EXT4-fs (sda1): INFO: recovery required on readonly filesystem
+Jan 1 01:00:21 X60Trisquel kernel: [ 9.071514] EXT4-fs (sda1): write access will be enabled during recovery
+Jan 1 01:00:21 X60Trisquel kernel: [ 9.397275] EXT4-fs (sda1): recovery complete
+Jan 1 01:00:21 X60Trisquel kernel: [ 9.397872] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null)
+Jan 1 01:00:21 X60Trisquel kernel: [ 20.812492] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro
+Jan 1 01:00:21 X60Trisquel kernel: [ 21.723158] ADDRCONF(NETDEV_UP): eth0: link is not ready
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.217119] Bluetooth: Core ver 2.16
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.217143] NET: Registered protocol family 31
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.217145] Bluetooth: HCI device and connection manager initialized
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.217148] Bluetooth: HCI socket layer initialized
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.217150] Bluetooth: L2CAP socket layer initialized
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.217157] Bluetooth: SCO socket layer initialized
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.218911] lp: driver loaded but no devices found
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.270375] ppdev: user-space parallel port driver
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.285697] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.285701] Bluetooth: BNEP filters: protocol multicast
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.309953] Bluetooth: RFCOMM TTY layer initialized
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.309959] Bluetooth: RFCOMM socket layer initialized
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.309961] Bluetooth: RFCOMM ver 1.11
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.355490] Bluetooth: Generic Bluetooth USB driver ver 0.6
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.358365] usbcore: registered new interface driver btusb
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.410130] Non-volatile memory driver v1.3
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.504396] intel_rng: FWH not detected
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.509262] device-mapper: multipath: version 1.3.2 loaded
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.707977] usbcore: registered new interface driver usbserial
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.707993] USB Serial support registered for generic
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.708203] usbcore: registered new interface driver usbserial_generic
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.708206] usbserial: USB Serial Driver core
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.712918] USB Serial support registered for Sierra USB modem
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.712941] sierra 3-1:1.0: Sierra USB modem converter detected
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.714669] usb 3-1: Sierra USB modem converter now attached to ttyUSB0
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.714737] usb 3-1: Sierra USB modem converter now attached to ttyUSB1
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.714799] usb 3-1: Sierra USB modem converter now attached to ttyUSB2
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.714827] usbcore: registered new interface driver sierra
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.714830] sierra: v.1.7.16:USB Driver for Sierra Wireless USB modems
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.715635] leds_ss4200: no LED devices found
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.756344] cfg80211: Calling CRDA to update world regulatory domain
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.782934] yenta_cardbus 0000:05:00.0: CardBus bridge found [0000:0000]
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.782959] yenta_cardbus 0000:05:00.0: Using CSCINT to route CSC interrupts to PCI
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.782962] yenta_cardbus 0000:05:00.0: Routing CardBus interrupts to PCI
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.782969] yenta_cardbus 0000:05:00.0: TI: mfunc 0x01d01002, devctl 0x66
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.904848] cfg80211: World regulatory domain updated:
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.904852] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.904855] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.904858] cfg80211: (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.904862] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.904864] cfg80211: (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.904867] cfg80211: (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.926292] iwl3945: Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux, in-tree:s
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.926296] iwl3945: Copyright(c) 2003-2011 Intel Corporation
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.926364] iwl3945 0000:02:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
+Jan 1 01:00:22 X60Trisquel kernel: [ 22.926396] iwl3945 0000:02:00.0: setting latency timer to 64
+Jan 1 01:00:23 X60Trisquel kernel: [ 22.993993] iwl3945 0000:02:00.0: Tunable channels: 11 802.11bg, 13 802.11a channels
+Jan 1 01:00:23 X60Trisquel kernel: [ 22.993998] iwl3945 0000:02:00.0: Detected Intel Wireless WiFi Link 3945ABG
+Jan 1 01:00:23 X60Trisquel kernel: [ 22.994151] iwl3945 0000:02:00.0: irq 46 for MSI/MSI-X
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.004162] Registered led device: phy0-led
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.004232] cfg80211: Ignoring regulatory request Set by core since the driver uses its own custom regulatory domain
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.016844] yenta_cardbus 0000:05:00.0: ISA IRQ mask 0x0cf8, PCI irq 16
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.016849] yenta_cardbus 0000:05:00.0: Socket status: 30000007
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.016854] pci_bus 0000:05: Raising subordinate bus# of parent bus (#05) from #05 to #09
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.016864] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [io 0x2000-0x3fff]
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.016868] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x2000-0x3fff: excluding 0x2000-0x20ff 0x2400-0x24ff
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.045522] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [mem 0xe0000000-0xe20fffff]
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.045527] pcmcia_socket pcmcia_socket0: cs: memory probe 0xe0000000-0xe20fffff: excluding 0xe1ef0000-0xe20fffff
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.045542] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [mem 0xe2100000-0xe40fffff 64bit pref]
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.045546] pcmcia_socket pcmcia_socket0: cs: memory probe 0xe2100000-0xe40fffff: excluding 0xe2100000-0xe40fffff
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.177380] ieee80211 phy0: Selected rate control algorithm 'iwl-3945-rs'
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.217008] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x100-0x3af: excluding 0x170-0x177 0x1f0-0x1f7 0x370-0x377
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.219015] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x3e0-0x4ff: excluding 0x3f0-0x3f7 0x400-0x41f 0x480-0x4bf 0x4d0-0x4d7
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.219577] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x820-0x8ff: clean.
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.224420] pcmcia_socket pcmcia_socket0: cs: IO port probe 0xc00-0xcf7: clean.
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.225172] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff: excluding 0xf0000-0xfffff
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.225213] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff: clean.
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.225259] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff: clean.
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.225305] pcmcia_socket pcmcia_socket0: cs: IO port probe 0xa00-0xaff: clean.
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.281257] type=1400 audit(23.277:2): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=665 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.281406] type=1400 audit(23.277:3): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=665 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.281499] type=1400 audit(23.277:4): apparmor="STATUS" operation="profile_load" name="/usr/lib/connman/scripts/dhclient-script" pid=665 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.395423] type=1400 audit(23.389:5): apparmor="STATUS" operation="profile_replace" name="/sbin/dhclient" pid=746 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.395575] type=1400 audit(23.389:6): apparmor="STATUS" operation="profile_replace" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=746 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.395673] type=1400 audit(23.389:7): apparmor="STATUS" operation="profile_replace" name="/usr/lib/connman/scripts/dhclient-script" pid=746 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.456805] psmouse serio1: synaptics: Touchpad model: 1, fw: 6.2, id: 0x81a0b1, caps: 0xa04793/0x300000/0x0
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.456812] psmouse serio1: synaptics: serio: Synaptics pass-through port at isa0060/serio1/input0
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.502122] input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input5
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.561248] init: failsafe main process (842) killed by TERM signal
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.643895] type=1400 audit(23.637:8): apparmor="STATUS" operation="profile_load" name="/usr/lib/cups/backend/cups-pdf" pid=656 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.644862] type=1400 audit(23.641:9): apparmor="STATUS" operation="profile_load" name="/usr/sbin/cupsd" pid=656 comm="apparmor_parser"
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.752331] e1000e 0000:01:00.0: irq 45 for MSI/MSI-X
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.808134] e1000e 0000:01:00.0: irq 45 for MSI/MSI-X
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.808714] ADDRCONF(NETDEV_UP): eth3: link is not ready
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.809120] ADDRCONF(NETDEV_UP): eth3: link is not ready
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.811292] 0000:02:00.0: Missing Free firmware
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.826370] snd_hda_intel 0000:00:1b.0: PCI INT B -> GSI 17 (level, low) -> IRQ 17
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.826378] hda_intel: probe_mask set to 0x1 for device 17aa:2010
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.826446] snd_hda_intel 0000:00:1b.0: irq 47 for MSI/MSI-X
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.826483] snd_hda_intel 0000:00:1b.0: setting latency timer to 64
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.829518] iwl3945 0000:02:00.0: /*(DEBLOBBED)*/ firmware file req failed: -22
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.829575] iwl3945 0000:02:00.0: Could not read microcode: -22
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.829722] ADDRCONF(NETDEV_UP): wlan8: link is not ready
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.846753] 0000:02:00.0: Missing Free firmware
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.848824] iwl3945 0000:02:00.0: /*(DEBLOBBED)*/ firmware file req failed: -22
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.848879] iwl3945 0000:02:00.0: Could not read microcode: -22
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.851120] 0000:02:00.0: Missing Free firmware
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.854519] iwl3945 0000:02:00.0: /*(DEBLOBBED)*/ firmware file req failed: -22
+Jan 1 01:00:23 X60Trisquel kernel: [ 23.856360] iwl3945 0000:02:00.0: Could not read microcode: -22
+Jan 1 01:00:24 X60Trisquel kernel: [ 24.022103] type=1400 audit(24.017:10): apparmor="STATUS" operation="profile_replace" name="/sbin/dhclient" pid=826 comm="apparmor_parser"
+Jan 1 01:00:24 X60Trisquel kernel: [ 24.022254] type=1400 audit(24.017:11): apparmor="STATUS" operation="profile_replace" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=826 comm="apparmor_parser"
+Jan 1 01:00:24 X60Trisquel kernel: [ 24.987006] init: alsa-restore main process (1021) terminated with status 99
+Jan 1 01:00:25 X60Trisquel kernel: [ 25.154008] [drm:i915_gem_execbuffer2] *ERROR* copy 1 exec entries failed 56
+Jan 1 01:00:26 X60Trisquel kernel: [ 26.329969] init: plymouth-stop pre-start process (1321) terminated with status 1
+Jan 1 01:00:26 X60Trisquel kernel: [ 26.528749] psmouse serio2: hgpk: ID: 10 00 64
+Jan 1 01:00:30 X60Trisquel kernel: [ 30.040699] IBM TrackPoint firmware: 0x0e, buttons: 3/3
+Jan 1 01:00:30 X60Trisquel kernel: [ 30.275522] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/serio2/input/input6
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.753313] BUG: unable to handle kernel paging request at 30000008
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] IP: [<c1109503>] handle_pte_fault+0xa3/0x220
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] *pde = 00000000
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] Oops: 0000 [#1] SMP
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] Modules linked in: kvm_intel dm_crypt kvm snd_hda_codec_analog snd_hda_intel snd_hda_codec snd_hwdep joydev snd_pcm snd_seq_midi snd_rawmidi snd_seq_midi_event snd_seq pcmcia arc4 snd_timer snd_seq_device iwl3945 iwl_legacy mac80211 snd yenta_socket psmouse cfg80211 pcmcia_rsrc serio_raw pcmcia_core sierra usbserial soundcore mac_hid snd_page_alloc dm_multipath nvram btusb rfcomm bnep parport_pc ppdev bluetooth lp parport raid10 raid456 async_raid6_recov async_pq raid6_pq async_xor async_memcpy async_tx raid1 raid0 multipath linear dm_raid45 xor dm_mirror dm_region_hash dm_log btrfs zlib_deflate libcrc32c i915 drm_kms_helper drm i2c_algo_bit video e1000e
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010]
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] Pid: 1345, comm: udevd Not tainted 3.2.0-64-generic #1trisquel1 LENOVO 195143U
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] EIP: 0060:[<c1109503>] EFLAGS: 00010206 CPU: 0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] EIP is at handle_pte_fault+0xa3/0x220
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] EAX: 30000000 EBX: f2b483c8 ECX: 00ed82f8 EDX: f2b483c8
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] ESI: 00000000 EDI: 00ed82f8 EBP: f212dde8 ESP: f212ddc4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] Process udevd (pid: 1345, ti=f212c000 task=f2bd58d0 task.ti=f212c000)
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] Stack:
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] eaa9eadb f212dde0 c102cf3e fffff000 f257400c f4b8a400 f257400c f4b8a400
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] f2b483c8 f212de18 c11097d7 fffbab60 f257400c 00000028 360f3674 00000000
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] 00ed82f8 0000000c f2b483c8 f212de9c c157ef30 f212de94 c157f088 00000028
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] Call Trace:
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c102cf3e>] ? kmap_atomic_prot+0xde/0x100
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c11097d7>] handle_mm_fault+0x157/0x210
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157f088>] do_page_fault+0x158/0x4b0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157c417>] error_code+0x67/0x6c
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c110b7e7>] ? find_vma+0x37/0x60
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157f04b>] do_page_fault+0x11b/0x4b0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c157c417>] error_code+0x67/0x6c
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c10300d8>] ? xo1_sci_intr+0xc8/0x100
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c12a8f45>] ? __put_user_4+0x11/0x18
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c1045776>] ? schedule_tail+0x56/0xa0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c1582cc6>] ret_from_fork+0x6/0x1c
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] [<c1580000>] ? kprobe_optimizer+0xc0/0xd0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] Code: 01 f0 89 44 24 04 8b 45 f0 89 14 24 89 da e8 d5 c8 ff ff 8b 5d f4 8b 75 f8 8b 7d fc 89 ec 5d c3 8b 42 44 85 c0 0f 84 35 01 00 00 <8b> 48 08 85 c9 0f 84 2a 01 00 00 8b 45 08 89 fe 81 e6 00 f0 ff
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] EIP: [<c1109503>] handle_pte_fault+0xa3/0x220 SS:ESP 0068:f212ddc4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.756010] CR2: 0000000030000008
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863345] ---[ end trace a3dd6a099e80bf23 ]---
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863351] note: udevd[1345] exited with preempt_count 1
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863356] BUG: scheduling while atomic: udevd/1345/0x10000001
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863359] Modules linked in: kvm_intel dm_crypt kvm snd_hda_codec_analog snd_hda_intel snd_hda_codec snd_hwdep joydev snd_pcm snd_seq_midi snd_rawmidi snd_seq_midi_event snd_seq pcmcia arc4 snd_timer snd_seq_device iwl3945 iwl_legacy mac80211 snd yenta_socket psmouse cfg80211 pcmcia_rsrc serio_raw pcmcia_core sierra usbserial soundcore mac_hid snd_page_alloc dm_multipath nvram btusb rfcomm bnep parport_pc ppdev bluetooth lp parport raid10 raid456 async_raid6_recov async_pq raid6_pq async_xor async_memcpy async_tx raid1 raid0 multipath linear dm_raid45 xor dm_mirror dm_region_hash dm_log btrfs zlib_deflate libcrc32c i915 drm_kms_helper drm i2c_algo_bit video e1000e
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863492] Pid: 1345, comm: udevd Tainted: G D 3.2.0-64-generic #1trisquel1
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863496] Call Trace:
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863502] [<c1566abf>] ? printk+0x2d/0x2f
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863508] [<c1566307>] __schedule_bug+0x5e/0x64
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863514] [<c1579d14>] __schedule+0x614/0x620
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863521] [<c104c02d>] ? console_unlock+0x11d/0x160
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863528] [<c1027858>] ? default_spin_lock_flags+0x8/0x10
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863534] [<c157bbbd>] ? _raw_spin_lock_irqsave+0x2d/0x40
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863541] [<c1044c0b>] __cond_resched+0x1b/0x30
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863546] [<c1579d99>] _cond_resched+0x29/0x30
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863552] [<c157af00>] down_read+0x10/0x1f
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863558] [<c1090ed4>] acct_collect+0x44/0x180
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863564] [<c104fc07>] do_exit+0x2e7/0x3c0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863570] [<c157cc66>] oops_end+0x96/0xd0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863576] [<c156597a>] no_context+0x13c/0x144
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863582] [<c1565aa3>] __bad_area_nosemaphore+0x121/0x129
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863588] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863594] [<c1565ac2>] bad_area_nosemaphore+0x17/0x19
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863599] [<c157f342>] do_page_fault+0x412/0x4b0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863605] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863611] [<c157c417>] error_code+0x67/0x6c
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863617] [<c1109503>] ? handle_pte_fault+0xa3/0x220
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863622] [<c102cf3e>] ? kmap_atomic_prot+0xde/0x100
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863628] [<c11097d7>] handle_mm_fault+0x157/0x210
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863634] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863639] [<c157f088>] do_page_fault+0x158/0x4b0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863645] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863651] [<c157c417>] error_code+0x67/0x6c
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863656] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863662] [<c110b7e7>] ? find_vma+0x37/0x60
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863667] [<c157f04b>] do_page_fault+0x11b/0x4b0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863674] [<c157ef30>] ? vmalloc_fault+0xf4/0xf4
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863680] [<c157c417>] error_code+0x67/0x6c
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863685] [<c10300d8>] ? xo1_sci_intr+0xc8/0x100
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863691] [<c12a8f45>] ? __put_user_4+0x11/0x18
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863697] [<c1045776>] ? schedule_tail+0x56/0xa0
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863703] [<c1582cc6>] ret_from_fork+0x6/0x1c
+Jan 1 01:00:34 X60Trisquel kernel: [ 34.863709] [<c1580000>] ? kprobe_optimizer+0xc0/0xd0
\ No newline at end of file diff --git a/docs/t7200q/t7200_01.jpg b/docs/t7200q/t7200_01.jpg Binary files differnew file mode 100644 index 0000000..ccf8618 --- /dev/null +++ b/docs/t7200q/t7200_01.jpg diff --git a/docs/t7200q/t7200_02.jpg b/docs/t7200q/t7200_02.jpg Binary files differnew file mode 100644 index 0000000..e17279c --- /dev/null +++ b/docs/t7200q/t7200_02.jpg @@ -43,6 +43,11 @@ git reset --hard dc27919d7a66a6e8685ce07c71aefa4f03ef7c07 # no patches required +# We don't need .git* (please submit all upstreamable changes directly to bucts upstream) +# removing them, to reduce the size of the archive +rm -rf .git +rm -rf .gitignore + # we're done cd ../ diff --git a/getflashrom b/getflashrom index fee72c5..8908dd4 100755 --- a/getflashrom +++ b/getflashrom @@ -38,6 +38,14 @@ svn co -r 1822 svn://flashrom.org/flashrom/trunk flashrom # there are no permanent patches needed to be applied here: # the patches are applied selectively at build time (when running "builddeps-flashrom") +# delete the .svn directory +# (not needed to work with source code) +# (reduces size of the archive) +# flashrom development should be upstream! +cd flashrom +rm -rf .svn +cd ../ + echo "FINISHED DOWNLOADING FLASHROM" # ------------------- DONE ---------------------- @@ -66,6 +66,11 @@ git apply gitdiff # remove the copy (no longer needed) rm -rf gitdiff +# We don't need .git* (please submit all upstreamable changes directly to GRUB upstream) +# removing them, to reduce the size of the archive +rm -rf .git +rm -rf .gitignore + # we're done cd ../ diff --git a/macbook21_firstflash b/macbook21_firstflash new file mode 100755 index 0000000..1399d99 --- /dev/null +++ b/macbook21_firstflash @@ -0,0 +1,39 @@ +#!/bin/bash + +# flash script: uses flashrom to flash a new libreboot ROM image onto your machine +# +# Copyright (C) 2014 Francis Rowe +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +# USE ROOT OR SUDO WHEN EXECUTING THIS +# uses flashrom to flash the rom + +if (( $# != 1 )); then + echo "Usage: ./lenovobios_firstflash yourrom.rom" + echo "usage: ./lenovobios_firstflash path/to/yourrom.rom" + echo "You need to specify exactly 1 file" + exit +fi +if [ ! -f $1 ]; then + echo "File not found!" + exit +fi + +# flashrom doesn't recognize the machine unless you use that switch: laptop=force_I_want_a_brick +# after flashing libreboot and booting the machine, flashing normally will just work. + +./flashrom/flashrom -p internal:laptop=force_I_want_a_brick -w $1 +echo "IGNORE THE ERRORS. JUST MAKE SURE THAT IT SAYS 'VERIFIED' ABOVE (if not, goto #libreboot on freenode irc)" diff --git a/resources/grub/background/gnulove.jpg b/resources/grub/background/gnulove.jpg Binary files differindex c8bd2ed..6358271 100644 --- a/resources/grub/background/gnulove.jpg +++ b/resources/grub/background/gnulove.jpg diff --git a/resources/grub/keymap/itqwerty.gkb b/resources/grub/keymap/itqwerty.gkb Binary files differnew file mode 100644 index 0000000..f247cd1 --- /dev/null +++ b/resources/grub/keymap/itqwerty.gkb diff --git a/resources/grub/keymap/original/itqwerty b/resources/grub/keymap/original/itqwerty new file mode 100644 index 0000000..6c53aac --- /dev/null +++ b/resources/grub/keymap/original/itqwerty @@ -0,0 +1,130 @@ +keymaps 0-127 +keycode 1 = Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Escape Escape Escape Escape Escape Escape Escape Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape Meta_Escape +keycode 2 = U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+0031 U+0021 U+00b9 U+00a1 VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_one Meta_exclam Meta_one Meta_exclam VoidSymbol VoidSymbol VoidSymbol VoidSymbol +keycode 3 = U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute U+0032 U+0022 U+00b2 dead_doubleacute nul nul nul dead_doubleacute Meta_two Meta_quotedbl Meta_two dead_doubleacute Meta_nul Meta_nul Meta_nul dead_doubleacute +keycode 4 = U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde U+0033 U+00a3 U+00b3 dead_tilde Escape Escape Escape dead_tilde Meta_three Meta_three Meta_three dead_tilde Meta_Escape Meta_Escape Meta_Escape dead_tilde +keycode 5 = U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+0034 U+0024 U+00bc U+215b Control_backslash Control_backslash Control_backslash Control_backslash Meta_four Meta_dollar Meta_four Meta_dollar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash +keycode 6 = U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0035 U+0025 U+00bd U+215c Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_five Meta_percent Meta_five Meta_percent Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright +keycode 7 = U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum U+0036 U+0026 U+00ac U+215d Control_asciicircum Control_asciicircum Control_asciicircum Control_asciicircum Meta_six Meta_ampersand Meta_six Meta_ampersand Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum Meta_Control_asciicircum +keycode 8 = U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+0037 U+002f U+007b U+215e Control_underscore Control_underscore Control_underscore Control_underscore Meta_seven Meta_slash Meta_braceleft Meta_braceleft Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore +keycode 9 = U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape U+0038 U+0028 U+005b U+2122 Delete Delete Escape Escape Meta_eight Meta_parenleft Meta_bracketleft Meta_bracketleft Meta_Delete Meta_Delete Meta_Escape Meta_Escape +keycode 10 = U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+0039 U+0029 U+005d U+00b1 Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_nine Meta_parenright Meta_bracketright Meta_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright +keycode 11 = U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek U+0030 U+003d U+007d dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek Meta_zero Meta_equal Meta_braceright dead_ogonek dead_ogonek dead_ogonek dead_ogonek dead_ogonek +keycode 12 = U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul U+0027 U+003f U+0060 U+00bf Control_g Delete nul nul Meta_apostrophe Meta_question Meta_grave Meta_grave Meta_Control_g Meta_Delete Meta_nul Meta_nul +keycode 13 = +U+00ec U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +U+00ec U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +U+00ec U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +U+00ec U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +U+00cc U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +U+00cc U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +U+00cc U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +U+00cc U+005e U+007e dead_circumflex Control_asciicircum Control_asciicircum dead_circumflex dead_circumflex Meta_asciicircum Meta_asciicircum Meta_asciitilde dead_circumflex Meta_Control_asciicircum Meta_Control_asciicircum dead_circumflex dead_circumflex +keycode 14 = Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace Delete Delete Delete Delete BackSpace BackSpace BackSpace BackSpace Meta_Delete Meta_Delete Meta_Delete Meta_Delete Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +keycode 15 = Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Tab Tab Tab Tab Tab Tab Tab Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab Meta_Tab +keycode 16 = +U+0071 +U+0051 U+0040 +U+03a9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +U+0071 +U+0051 U+0040 +U+03a9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +U+0071 +U+0051 U+0040 +U+03a9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +U+0071 +U+0051 U+0040 +U+03a9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +U+0051 +U+0071 U+0040 +U+03c9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +U+0051 +U+0071 U+0040 +U+03c9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +U+0051 +U+0071 U+0040 +U+03c9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +U+0051 +U+0071 U+0040 +U+03c9 Control_q Control_q nul nul Meta_q Meta_Q Meta_at Meta_at Meta_Control_q Meta_Control_q Meta_nul Meta_nul +keycode 17 = +U+0077 +U+0057 +U+0142 +U+0141 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +U+0077 +U+0057 +U+0142 +U+0141 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +U+0077 +U+0057 +U+0142 +U+0141 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +U+0077 +U+0057 +U+0142 +U+0141 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +U+0057 +U+0077 +U+0141 +U+0142 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +U+0057 +U+0077 +U+0141 +U+0142 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +U+0057 +U+0077 +U+0141 +U+0142 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +U+0057 +U+0077 +U+0141 +U+0142 Control_w Control_w Control_w Control_w Meta_w Meta_W Meta_w Meta_W Meta_Control_w Meta_Control_w Meta_Control_w Meta_Control_w +keycode 18 = +U+0065 +U+0045 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +U+0065 +U+0045 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +U+0065 +U+0045 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +U+0065 +U+0045 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +U+0045 +U+0065 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +U+0045 +U+0065 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +U+0045 +U+0065 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +U+0045 +U+0065 U+20ac U+00a2 Control_e Control_e Control_e Control_e Meta_e Meta_E Meta_e Meta_E Meta_Control_e Meta_Control_e Meta_Control_e Meta_Control_e +keycode 19 = +U+0072 +U+0052 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +U+0072 +U+0052 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +U+0072 +U+0052 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +U+0072 +U+0052 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +U+0052 +U+0072 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +U+0052 +U+0072 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +U+0052 +U+0072 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +U+0052 +U+0072 U+00b6 U+00ae Control_r Control_r Control_r Control_r Meta_r Meta_R Meta_r Meta_R Meta_Control_r Meta_Control_r Meta_Control_r Meta_Control_r +keycode 20 = +U+0074 +U+0054 +U+0167 +U+0166 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +U+0074 +U+0054 +U+0167 +U+0166 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +U+0074 +U+0054 +U+0167 +U+0166 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +U+0074 +U+0054 +U+0167 +U+0166 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +U+0054 +U+0074 +U+0166 +U+0167 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +U+0054 +U+0074 +U+0166 +U+0167 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +U+0054 +U+0074 +U+0166 +U+0167 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +U+0054 +U+0074 +U+0166 +U+0167 Control_t Control_t Control_t Control_t Meta_t Meta_T Meta_t Meta_T Meta_Control_t Meta_Control_t Meta_Control_t Meta_Control_t +keycode 21 = +U+0079 +U+0059 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +U+0079 +U+0059 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +U+0079 +U+0059 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +U+0079 +U+0059 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +U+0059 +U+0079 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +U+0059 +U+0079 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +U+0059 +U+0079 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +U+0059 +U+0079 U+2190 U+00a5 Control_y Control_y Control_y Control_y Meta_y Meta_Y Meta_y Meta_Y Meta_Control_y Meta_Control_y Meta_Control_y Meta_Control_y +keycode 22 = +U+0075 +U+0055 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +U+0075 +U+0055 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +U+0075 +U+0055 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +U+0075 +U+0055 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +U+0055 +U+0075 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +U+0055 +U+0075 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +U+0055 +U+0075 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +U+0055 +U+0075 U+2193 U+2191 Control_u Control_u Control_u Control_u Meta_u Meta_U Meta_u Meta_U Meta_Control_u Meta_Control_u Meta_Control_u Meta_Control_u +keycode 23 = +U+0069 +U+0049 U+2192 +U+0131 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +U+0069 +U+0049 U+2192 +U+0131 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +U+0069 +U+0049 U+2192 +U+0131 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +U+0069 +U+0049 U+2192 +U+0131 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +U+0049 +U+0069 U+2192 +U+0049 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +U+0049 +U+0069 U+2192 +U+0049 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +U+0049 +U+0069 U+2192 +U+0049 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +U+0049 +U+0069 U+2192 +U+0049 Tab Tab Tab Tab Meta_i Meta_I Meta_i Meta_I Meta_Tab Meta_Tab Meta_Tab Meta_Tab +keycode 24 = +U+006f +U+004f +U+00f8 +U+00d8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +U+006f +U+004f +U+00f8 +U+00d8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +U+006f +U+004f +U+00f8 +U+00d8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +U+006f +U+004f +U+00f8 +U+00d8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +U+004f +U+006f +U+00d8 +U+00f8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +U+004f +U+006f +U+00d8 +U+00f8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +U+004f +U+006f +U+00d8 +U+00f8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +U+004f +U+006f +U+00d8 +U+00f8 Control_o Control_o Control_o Control_o Meta_o Meta_O Meta_o Meta_O Meta_Control_o Meta_Control_o Meta_Control_o Meta_Control_o +keycode 25 = +U+0070 +U+0050 +U+00fe +U+00de Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +U+0070 +U+0050 +U+00fe +U+00de Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +U+0070 +U+0050 +U+00fe +U+00de Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +U+0070 +U+0050 +U+00fe +U+00de Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +U+0050 +U+0070 +U+00de +U+00fe Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +U+0050 +U+0070 +U+00de +U+00fe Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +U+0050 +U+0070 +U+00de +U+00fe Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +U+0050 +U+0070 +U+00de +U+00fe Control_p Control_p Control_p Control_p Meta_p Meta_P Meta_p Meta_P Meta_Control_p Meta_Control_p Meta_Control_p Meta_Control_p +keycode 26 = +U+00e8 +U+00e9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +U+00e8 +U+00e9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +U+00e8 +U+00e9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +U+00e8 +U+00e9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +U+00c8 +U+00c9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +U+00c8 +U+00c9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +U+00c8 +U+00c9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +U+00c8 +U+00c9 U+005b U+007b Escape Escape Escape Escape Meta_bracketleft Meta_braceleft Meta_bracketleft Meta_braceleft Meta_Escape Meta_Escape Meta_Escape Meta_Escape +keycode 27 = U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright U+002b U+002a U+005d U+007d Control_bracketright Control_bracketright Control_bracketright Control_bracketright Meta_plus Meta_asterisk Meta_bracketright Meta_braceright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright Meta_Control_bracketright +keycode 28 = Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Return Return Return Return Control_m Control_m Control_m Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +keycode 29 = Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control +keycode 30 = +U+0061 +U+0041 +U+00e6 +U+00c6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +U+0061 +U+0041 +U+00e6 +U+00c6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +U+0061 +U+0041 +U+00e6 +U+00c6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +U+0061 +U+0041 +U+00e6 +U+00c6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +U+0041 +U+0061 +U+00c6 +U+00e6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +U+0041 +U+0061 +U+00c6 +U+00e6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +U+0041 +U+0061 +U+00c6 +U+00e6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +U+0041 +U+0061 +U+00c6 +U+00e6 Control_a Control_a Control_a Control_a Meta_a Meta_A Meta_a Meta_A Meta_Control_a Meta_Control_a Meta_Control_a Meta_Control_a +keycode 31 = +U+0073 +U+0053 +U+00df U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +U+0073 +U+0053 +U+00df U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +U+0073 +U+0053 +U+00df U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +U+0073 +U+0053 +U+00df U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +U+0053 +U+0073 +U+0053 U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +U+0053 +U+0073 +U+0053 U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +U+0053 +U+0073 +U+0053 U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +U+0053 +U+0073 +U+0053 U+00a7 Control_s Control_s Control_s Control_s Meta_s Meta_S Meta_s Meta_S Meta_Control_s Meta_Control_s Meta_Control_s Meta_Control_s +keycode 32 = +U+0064 +U+0044 +U+00f0 +U+00d0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +U+0064 +U+0044 +U+00f0 +U+00d0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +U+0064 +U+0044 +U+00f0 +U+00d0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +U+0064 +U+0044 +U+00f0 +U+00d0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +U+0044 +U+0064 +U+00d0 +U+00f0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +U+0044 +U+0064 +U+00d0 +U+00f0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +U+0044 +U+0064 +U+00d0 +U+00f0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +U+0044 +U+0064 +U+00d0 +U+00f0 Control_d Control_d Control_d Control_d Meta_d Meta_D Meta_d Meta_D Meta_Control_d Meta_Control_d Meta_Control_d Meta_Control_d +keycode 33 = +U+0066 +U+0046 +U+0111 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +U+0066 +U+0046 +U+0111 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +U+0066 +U+0046 +U+0111 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +U+0066 +U+0046 +U+0111 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +U+0046 +U+0066 +U+0110 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +U+0046 +U+0066 +U+0110 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +U+0046 +U+0066 +U+0110 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +U+0046 +U+0066 +U+0110 +U+00aa Control_f Control_f Control_f Control_f Meta_f Meta_F Meta_f Meta_F Meta_Control_f Meta_Control_f Meta_Control_f Meta_Control_f +keycode 34 = +U+0067 +U+0047 +U+014b +U+014a Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +U+0067 +U+0047 +U+014b +U+014a Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +U+0067 +U+0047 +U+014b +U+014a Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +U+0067 +U+0047 +U+014b +U+014a Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +U+0047 +U+0067 +U+014a +U+014b Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +U+0047 +U+0067 +U+014a +U+014b Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +U+0047 +U+0067 +U+014a +U+014b Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +U+0047 +U+0067 +U+014a +U+014b Control_g Control_g Control_g Control_g Meta_g Meta_G Meta_g Meta_G Meta_Control_g Meta_Control_g Meta_Control_g Meta_Control_g +keycode 35 = +U+0068 +U+0048 +U+0127 +U+0126 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +U+0068 +U+0048 +U+0127 +U+0126 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +U+0068 +U+0048 +U+0127 +U+0126 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +U+0068 +U+0048 +U+0127 +U+0126 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +U+0048 +U+0068 +U+0126 +U+0127 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +U+0048 +U+0068 +U+0126 +U+0127 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +U+0048 +U+0068 +U+0126 +U+0127 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +U+0048 +U+0068 +U+0126 +U+0127 BackSpace BackSpace BackSpace BackSpace Meta_h Meta_H Meta_h Meta_H Meta_BackSpace Meta_BackSpace Meta_BackSpace Meta_BackSpace +keycode 36 = +U+006a +U+004a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +U+006a +U+004a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +U+006a +U+004a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +U+006a +U+004a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +U+004a +U+006a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +U+004a +U+006a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +U+004a +U+006a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +U+004a +U+006a U+0309 U+031b Linefeed Linefeed Linefeed Linefeed Meta_j Meta_J Meta_j Meta_J Meta_Linefeed Meta_Linefeed Meta_Linefeed Meta_Linefeed +keycode 37 = +U+006b +U+004b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +U+006b +U+004b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +U+006b +U+004b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +U+006b +U+004b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +U+004b +U+006b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +U+004b +U+006b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +U+004b +U+006b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +U+004b +U+006b +U+0138 U+0026 Control_k Control_k Control_k Control_k Meta_k Meta_K Meta_k Meta_ampersand Meta_Control_k Meta_Control_k Meta_Control_k Meta_Control_k +keycode 38 = +U+006c +U+004c +U+0142 +U+0141 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +U+006c +U+004c +U+0142 +U+0141 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +U+006c +U+004c +U+0142 +U+0141 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +U+006c +U+004c +U+0142 +U+0141 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +U+004c +U+006c +U+0141 +U+0142 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +U+004c +U+006c +U+0141 +U+0142 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +U+004c +U+006c +U+0141 +U+0142 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +U+004c +U+006c +U+0141 +U+0142 Control_l Control_l Control_l Control_l Meta_l Meta_L Meta_l Meta_L Meta_Control_l Meta_Control_l Meta_Control_l Meta_Control_l +keycode 39 = +U+00f2 +U+00e7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +U+00f2 +U+00e7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +U+00f2 +U+00e7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +U+00f2 +U+00e7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +U+00d2 +U+00c7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +U+00d2 +U+00c7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +U+00d2 +U+00c7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +U+00d2 +U+00c7 U+0040 dead_cedilla nul dead_cedilla nul dead_cedilla Meta_at dead_cedilla Meta_at dead_cedilla Meta_nul dead_cedilla Meta_nul dead_cedilla +keycode 40 = +U+00e0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +U+00e0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +U+00e0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +U+00e0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +U+00c0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +U+00c0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +U+00c0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +U+00c0 U+00b0 U+0023 U+002a VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_numbersign Meta_asterisk Meta_numbersign Meta_asterisk VoidSymbol VoidSymbol VoidSymbol VoidSymbol +keycode 41 = U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash U+005c U+007c U+00ac U+00a6 Control_backslash Control_backslash Control_backslash Control_backslash Meta_backslash Meta_bar Meta_backslash Meta_bar Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash Meta_Control_backslash +keycode 42 = Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift +keycode 43 = +U+00f9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +U+00f9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +U+00f9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +U+00f9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +U+00d9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +U+00d9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +U+00d9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +U+00d9 U+00a7 dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve dead_grave dead_breve +keycode 44 = +U+007a +U+005a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +U+007a +U+005a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +U+007a +U+005a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +U+007a +U+005a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +U+005a +U+007a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +U+005a +U+007a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +U+005a +U+007a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +U+005a +U+007a U+00ab U+003c Control_z Control_z Control_z Control_z Meta_z Meta_Z Meta_z Meta_less Meta_Control_z Meta_Control_z Meta_Control_z Meta_Control_z +keycode 45 = +U+0078 +U+0058 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +U+0078 +U+0058 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +U+0078 +U+0058 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +U+0078 +U+0058 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +U+0058 +U+0078 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +U+0058 +U+0078 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +U+0058 +U+0078 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +U+0058 +U+0078 U+00bb U+003e Control_x Control_x Control_x Control_x Meta_x Meta_X Meta_x Meta_greater Meta_Control_x Meta_Control_x Meta_Control_x Meta_Control_x +keycode 46 = +U+0063 +U+0043 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +U+0063 +U+0043 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +U+0063 +U+0043 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +U+0063 +U+0043 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +U+0043 +U+0063 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +U+0043 +U+0063 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +U+0043 +U+0063 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +U+0043 +U+0063 U+00a2 U+00a9 Control_c Control_c Control_c Control_c Meta_c Meta_C Meta_c Meta_C Meta_Control_c Meta_Control_c Meta_Control_c Meta_Control_c +keycode 47 = +U+0076 +U+0056 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +U+0076 +U+0056 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +U+0076 +U+0056 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +U+0076 +U+0056 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +U+0056 +U+0076 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +U+0056 +U+0076 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +U+0056 +U+0076 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +U+0056 +U+0076 U+201c U+2018 Control_v Control_v Control_v Control_v Meta_v Meta_V Meta_v Meta_V Meta_Control_v Meta_Control_v Meta_Control_v Meta_Control_v +keycode 48 = +U+0062 +U+0042 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +U+0062 +U+0042 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +U+0062 +U+0042 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +U+0062 +U+0042 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +U+0042 +U+0062 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +U+0042 +U+0062 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +U+0042 +U+0062 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +U+0042 +U+0062 U+201d U+2019 Control_b Control_b Control_b Control_b Meta_b Meta_B Meta_b Meta_B Meta_Control_b Meta_Control_b Meta_Control_b Meta_Control_b +keycode 49 = +U+006e +U+004e +U+00f1 +U+00d1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +U+006e +U+004e +U+00f1 +U+00d1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +U+006e +U+004e +U+00f1 +U+00d1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +U+006e +U+004e +U+00f1 +U+00d1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +U+004e +U+006e +U+00d1 +U+00f1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +U+004e +U+006e +U+00d1 +U+00f1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +U+004e +U+006e +U+00d1 +U+00f1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +U+004e +U+006e +U+00d1 +U+00f1 Control_n Control_n Control_n Control_n Meta_n Meta_N Meta_n Meta_N Meta_Control_n Meta_Control_n Meta_Control_n Meta_Control_n +keycode 50 = +U+006d +U+004d +U+00b5 +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +U+006d +U+004d +U+00b5 +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +U+006d +U+004d +U+00b5 +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +U+006d +U+004d +U+00b5 +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +U+004d +U+006d +U+039c +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +U+004d +U+006d +U+039c +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +U+004d +U+006d +U+039c +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +U+004d +U+006d +U+039c +U+00ba Control_m Control_m Control_m Control_m Meta_m Meta_M Meta_m Meta_M Meta_Control_m Meta_Control_m Meta_Control_m Meta_Control_m +keycode 51 = U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute U+002c U+003b dead_acute U+00d7 dead_acute dead_acute dead_acute dead_acute Meta_comma Meta_semicolon dead_acute dead_acute dead_acute dead_acute dead_acute dead_acute +keycode 52 = U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis U+002e U+003a U+00b7 dead_diaeresis Compose Compose Compose dead_diaeresis Meta_period Meta_colon Meta_period dead_diaeresis Compose Compose Compose dead_diaeresis +keycode 53 = U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore U+002d U+005f U+005f U+00f7 Control_underscore Control_underscore Control_underscore Control_underscore Meta_minus Meta_underscore Meta_underscore Meta_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore Meta_Control_underscore +keycode 54 = Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift Shift +keycode 55 = KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply Hex_C KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply KP_Multiply +keycode 56 = Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt +keycode 57 = U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul U+0020 U+0020 U+0020 U+0020 nul nul nul nul Meta_space Meta_space Meta_space Meta_space Meta_nul Meta_nul Meta_nul Meta_nul +keycode 58 = CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock CtrlL_Lock +keycode 59 = F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 F1 F13 Console_13 Console_25 F25 F37 Console_13 Console_25 Console_1 Console_13 F1 F1 Console_1 Console_13 F1 F1 +keycode 60 = F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 F2 F14 Console_14 Console_26 F26 F38 Console_14 Console_26 Console_2 Console_14 F2 F2 Console_2 Console_14 F2 F2 +keycode 61 = F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 F3 F15 Console_15 Console_27 F27 F39 Console_15 Console_27 Console_3 Console_15 F3 F3 Console_3 Console_15 F3 F3 +keycode 62 = F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 F4 F16 Console_16 Console_28 F28 F40 Console_16 Console_28 Console_4 Console_16 F4 F4 Console_4 Console_16 F4 F4 +keycode 63 = F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 F5 F17 Console_17 Console_29 F29 F41 Console_17 Console_29 Console_5 Console_17 F5 F5 Console_5 Console_17 F5 F5 +keycode 64 = F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 F6 F18 Console_18 Console_30 F30 F42 Console_18 Console_30 Console_6 Console_18 F6 F6 Console_6 Console_18 F6 F6 +keycode 65 = F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 F7 F19 Console_19 Console_31 F31 F43 Console_19 Console_31 Console_7 Console_19 F7 F7 Console_7 Console_19 F7 F7 +keycode 66 = F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 F8 F20 Console_20 Console_32 F32 F44 Console_20 Console_32 Console_8 Console_20 F8 F8 Console_8 Console_20 F8 F8 +keycode 67 = F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 F9 F21 Console_21 Console_33 F33 F45 Console_21 Console_33 Console_9 Console_21 F9 F9 Console_9 Console_21 F9 F9 +keycode 68 = F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 F10 F22 Console_22 Console_34 F34 F46 Console_22 Console_34 Console_10 Console_22 F10 F10 Console_10 Console_22 F10 F10 +keycode 69 = Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Hex_A Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock Num_Lock +keycode 70 = Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Show_Memory Show_Registers Scroll_Lock Show_State Scroll_Lock Scroll_Lock Scroll_Lock Show_Registers Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock Scroll_Lock +keycode 71 = KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 Ascii_7 Hex_7 KP_7 KP_7 KP_7 KP_7 KP_7 KP_7 +keycode 72 = KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 Ascii_8 Hex_8 KP_8 KP_8 KP_8 KP_8 KP_8 KP_8 +keycode 73 = KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 Ascii_9 Hex_9 KP_9 KP_9 KP_9 KP_9 KP_9 KP_9 +keycode 74 = KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract Hex_D KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract KP_Subtract +keycode 75 = KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 Ascii_4 Hex_4 KP_4 KP_4 KP_4 KP_4 KP_4 KP_4 +keycode 76 = KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 Ascii_5 Hex_5 KP_5 KP_5 KP_5 KP_5 KP_5 KP_5 +keycode 77 = KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 Ascii_6 Hex_6 KP_6 KP_6 KP_6 KP_6 KP_6 KP_6 +keycode 78 = KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add Hex_E KP_Add KP_Add KP_Add KP_Add KP_Add KP_Add +keycode 79 = KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 Ascii_1 Hex_1 KP_1 KP_1 KP_1 KP_1 KP_1 KP_1 +keycode 80 = KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 Ascii_2 Hex_2 KP_2 KP_2 KP_2 KP_2 KP_2 KP_2 +keycode 81 = KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 Ascii_3 Hex_3 KP_3 KP_3 KP_3 KP_3 KP_3 KP_3 +keycode 82 = KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 Ascii_0 Hex_0 KP_0 KP_0 KP_0 KP_0 KP_0 KP_0 +keycode 83 = KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period KP_Period KP_Period KP_Period KP_Period Boot KP_Period Boot KP_Period +keycode 86 = U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol U+003c U+003e U+00ab U+00bb VoidSymbol VoidSymbol VoidSymbol VoidSymbol Meta_less Meta_greater Meta_less Meta_greater VoidSymbol VoidSymbol VoidSymbol VoidSymbol +keycode 87 = F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 F11 F23 Console_23 Console_35 F35 F47 Console_23 Console_35 Console_11 Console_23 F11 F11 Console_11 Console_23 F11 F11 +keycode 88 = F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 F12 F24 Console_24 Console_36 F36 F48 Console_24 Console_36 Console_12 Console_24 F12 F12 Console_12 Console_24 F12 F12 +keycode 102 = Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home Home +keycode 103 = Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up KeyboardSignal Up Up Up Up Up Up Up +keycode 104 = Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Scroll_Backward Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior Prior +keycode 105 = Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left Left Left Left Left Left Left Left Left Decr_Console Left Left Left Left Left Left Left +keycode 106 = Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right Right Right Right Right Right Right Right Right Incr_Console Right Right Right Right Right Right Right +keycode 107 = End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End End +keycode 108 = Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down +keycode 109 = Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next Next Scroll_Forward Next Next Next Next Next Next Next Next Next Next Next Next Next Next +keycode 110 = Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert Insert +keycode 111 = Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove Remove Remove Remove Remove Remove Remove Boot Remove Remove Remove Remove Remove Boot Remove Boot Remove +keycode 96 = KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter Hex_F KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter KP_Enter +keycode 97 = Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control +keycode 119 = Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause +keycode 99 = VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash VoidSymbol VoidSymbol Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash Control_backslash +keycode 98 = KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide Hex_B KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide KP_Divide +keycode 100 = AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr AltGr +keycode 125 = Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt +keycode 126 = Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt Alt +keycode 121 = KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period KP_Period +strings as usual +# The content of this file will be appended to the keyboard layout. +# For example if you uncomment the following lines Alt+j can be used +# to go to the next console and Alt+k can be used to go to the +# previous console: + +# alt keycode 36 = Incr_Console +# shiftl alt keycode 36 = Incr_Console +# shiftr alt keycode 36 = Incr_Console +# shiftr shiftl alt keycode 36 = Incr_Console +# ctrll alt keycode 36 = Incr_Console +# ctrll shiftl alt keycode 36 = Incr_Console +# ctrll shiftr alt keycode 36 = Incr_Console +# ctrll shiftr shiftl alt keycode 36 = Incr_Console + +# alt keycode 37 = Decr_Console +# shiftl alt keycode 37 = Decr_Console +# shiftr alt keycode 37 = Decr_Console +# shiftr shiftl alt keycode 37 = Decr_Console +# ctrll alt keycode 37 = Decr_Console +# ctrll shiftl alt keycode 37 = Decr_Console +# ctrll shiftr alt keycode 37 = Decr_Console +# ctrll shiftr shiftl alt keycode 37 = Decr_Console + diff --git a/resources/utilities/i945gpu/intel-regs.py b/resources/utilities/i945gpu/intel-regs.py new file mode 100755 index 0000000..f16a8d7 --- /dev/null +++ b/resources/utilities/i945gpu/intel-regs.py @@ -0,0 +1,93 @@ +#!/usr/bin/env python2 +# -*- coding: utf-8 -*- +# Copyright (C) 2014 Michał Masłowski <mtjm@mtjm.eu> +# +# Licensed under copyleft-next version 0.3.0. See +# https://gitorious.org/copyleft-next/copyleft-next/raw/master:Releases/copyleft-next-0.3.0 +# for more information. + +"""Get values of interesting i945 graphics parameters from a running system. + +This script might show the values for GPU registers specified in +devicetree.cb on coreboot mainboard ports using i945 native VGA init +from <http://review.coreboot.org/#/c/5320/>. + +Run as root. +""" + + +import mmap +import re +import struct +import subprocess + + +_MEMORY = re.compile(r"^\s+Memory\s+at\s+([0-9a-f]+)\s+\(32-bit, non-prefetchable\)\s+\[size=[0-9]+K\]$") + + +def get_pci_data(): + # lspci has a machine readable format, but it doesn't have the needed data. + for devid in "8086:27a2", "8086:27a6": + lspci = subprocess.Popen(("lspci", "-vn", "-d", devid), + stdout=subprocess.PIPE, + stderr=subprocess.PIPE) + for line in lspci.communicate()[0].split("\n"): + match = _MEMORY.match(line) + if match is not None: + yield int(match.group(1), 16) + break + +func0, func1 = list(get_pci_data()) + + +def read32(fo, base, offset): + memory = mmap.mmap(fo.fileno(), offset + 4, + mmap.MAP_SHARED, mmap.ACCESS_READ, + offset=base) + try: + memory.seek(offset) + val = memory.read(4) + return struct.unpack("=I", val)[0] + finally: + memory.close() + +# Some i915 register names. +PORT_HOTPLUG_EN = 0x61110 +BLC_PWM_CTL = 0x61254 +LVDS = 0x61180 + +# Bits in LVDS. +LVDS_CLOCK_B_POWERUP_ALL = 3 << 4 +LVDS_CLOCK_BOTH_POWERUP_ALL = 3 << 2 + +# Expansion of DPLL(1). +DPLL1 = ((0x06014) + (1)*((0x06018)-(0x06014))) + +# Bits there. +DPLL_INTEGRATED_CLOCK_VLV = (1<<13) +DPLL_INTEGRATED_CRI_CLK_VLV = (1<<14) + +if __name__ == "__main__": + with open("/dev/mem", "rb") as mem: + print "gpu_hotplug = 0x%08x" % read32(mem, func0, PORT_HOTPLUG_EN) + dpll = read32(mem, func0, DPLL1) + spread_spectrum = dpll & (DPLL_INTEGRATED_CLOCK_VLV \ + | DPLL_INTEGRATED_CRI_CLK_VLV) + if spread_spectrum != 0: + spread_spectrum = 1 + print "gpu_lvds_use_spread_spectrum_clock = %d" % spread_spectrum + lvds = read32(mem, func0, LVDS) + dual_channel = lvds & (LVDS_CLOCK_B_POWERUP_ALL \ + | LVDS_CLOCK_BOTH_POWERUP_ALL) + if dual_channel != 0: + dual_channel = 1 + print "gpu_lvds_is_dual_channel = %d" % dual_channel + backlight = read32(mem, func0, BLC_PWM_CTL) + print "gpu_backlight = 0x%08x" % backlight + # Using display clock from i945_get_display_clock_speed in + # drivers/gpu/drm/i915/intel_display.c. Result multiplied by + # two to match BIOS-reported PWM frequency on my X60t. + mod_freq = 2 * 400000000 / ((backlight >> 16) * 128.0) + print "backlight modulation frequency = %f Hz" % mod_freq + print "duty cycle = %d%%" % (100.0 * (backlight & 0xffff) + / (backlight >> 16)) |
