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From 5428b15fb1aef85b47fbbb117d943d2525a84692 Mon Sep 17 00:00:00 2001
From: Timothy Pearson <tpearson@raptorengineeringinc.com>
Date: Fri, 14 Aug 2015 02:50:44 -0500
Subject: [PATCH 116/139] southbridge/amd/sr5650: Use correct PCI configuration
block offset
Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
---
src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl
index a6ab114..1e0d5b0 100644
--- a/src/southbridge/amd/sr5650/acpi/sr5650.asl
+++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl
@@ -19,8 +19,8 @@
*/
Scope(\) {
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* PIC IRQ mapping registers, C00h-C01h */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
--
1.9.1
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