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From 92145a02934f4e8d3044f734b001af21bdf50962 Mon Sep 17 00:00:00 2001
From: Timothy Pearson <tpearson@raptorengineeringinc.com>
Date: Fri, 7 Aug 2015 19:04:49 -0500
Subject: [PATCH 097/143] amd/family_10h-family_15h: Fix poor performance on
Family 15h CPUs
Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
---
src/cpu/amd/family_10h-family_15h/defaults.h | 13 +++++--
src/cpu/amd/family_10h-family_15h/init_cpus.c | 45 +++++++++++++++++++++++--
2 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
index bff2efd..4868c5c 100644
--- a/src/cpu/amd/family_10h-family_15h/defaults.h
+++ b/src/cpu/amd/family_10h-family_15h/defaults.h
@@ -535,15 +535,15 @@ static const struct {
{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00800756, 0x00F3FFFF },
- { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00a11755, 0x00f3ffff },
-
{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00C37756, 0x00F3FFFF },
{ 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00000036, 0x000000FF },
+ { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL,
+ 0x00a11755, 0x00f3ffff },
+
/* Errata 281 Workaround */
{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
@@ -555,6 +555,13 @@ static const struct {
{ 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x8000052A, 0xD5FFFFFF },
+ /* Core Interface Buffer Count */
+ { 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
+ 0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3,
+ L3ToSriReqCBC = 0x4,
+ L3FreeListCBC = default,
+ CpuCmdBufCnt = 0x4 */
+
/* ACPI Power State Control Reg1 */
{ 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0xE6002200, 0xFFFFFFFF },
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index d770f38..67893ca1 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -847,8 +847,9 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
*/
static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
{
- u32 val;
- u32 linktype = 0;
+ uint32_t val;
+ uint32_t val2;
+ uint32_t linktype = 0;
/* Check connect, init and coherency */
val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18);
@@ -863,8 +864,13 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
if (linktype) {
/* Check gen3 */
val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08);
+ val = (val >> 8) & 0xf;
+ if (is_gt_rev_d()) {
+ val2 = pci_read_config32(NODE_PCI(node, 0), regoff + 0x1c);
+ val |= (val2 & 0x1) << 4;
+ }
- if (((val >> 8) & 0x0F) > 6)
+ if (val > 6)
linktype |= HTPHY_LINKTYPE_HT3;
else
linktype |= HTPHY_LINKTYPE_HT1;
@@ -1151,6 +1157,39 @@ static void cpuSetAMDPCI(u8 node)
pci_write_config32(NODE_PCI(node, 3), 0xd4, dword);
}
+ if (revision & AMD_FAM15_ALL) {
+ uint32_t f5x80;
+ uint8_t cu_enabled;
+ uint8_t compute_unit_count = 0;
+ uint8_t compute_unit_buffer_count;
+
+ /* Determine the number of active compute units on this node */
+ f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80);
+ cu_enabled = f5x80 & 0xf;
+ if (cu_enabled == 0x1)
+ compute_unit_count = 1;
+ if (cu_enabled == 0x3)
+ compute_unit_count = 2;
+ if (cu_enabled == 0x7)
+ compute_unit_count = 3;
+ if (cu_enabled == 0xf)
+ compute_unit_count = 4;
+
+ if (compute_unit_count == 1)
+ compute_unit_buffer_count = 0x1c;
+ else if (compute_unit_count == 2)
+ compute_unit_buffer_count = 0x18;
+ else if (compute_unit_count == 3)
+ compute_unit_buffer_count = 0x14;
+ else
+ compute_unit_buffer_count = 0x10;
+
+ dword = pci_read_config32(NODE_PCI(node, 3), 0x1a0);
+ dword &= ~(0x1f << 4); /* L3FreeListCBC = compute_unit_buffer_count */
+ dword |= (compute_unit_buffer_count << 4);
+ pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword);
+ }
+
printk(BIOS_DEBUG, " done\n");
}
--
1.7.9.5
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