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From 9761ddff5c8e47d7b5321a8c98383970b4fb8683 Mon Sep 17 00:00:00 2001
From: Timothy Pearson <tpearson@raptorengineeringinc.com>
Date: Mon, 7 Mar 2016 09:10:31 -0600
Subject: [PATCH 1/2] nb/amd/mct_ddr3: Restore previous DQS delay values on
failed loop
Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 19a7acb..1a3c7c1 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1522,6 +1522,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4);
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4);
} else {
+ /* Restore current settings of other (previously trained) lanes to the active array */
+ memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay));
+
/* Reprogram the Read DQS Timing Control register with the original settings */
write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
}
@@ -1571,6 +1574,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4);
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4);
} else {
+ /* Restore current settings of other (previously trained) lanes to the active array */
+ memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay));
+
/* Reprogram the Write DQS Timing Control register with the original settings */
write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg);
}
--
1.9.1
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