diff options
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0082-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0082-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0082-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch b/resources/libreboot/patch/kgpe-d16/0082-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch new file mode 100644 index 0000000..d7d15cc --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0082-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch @@ -0,0 +1,98 @@ +From 3d30e829f9630d588dee70215b67343c75996520 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <kb9vqf@pearsoncomputing.net> +Date: Sat, 27 Jun 2015 17:52:45 -0500 +Subject: [PATCH 082/146] northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot + failure + +--- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 28 +++++++++++++++++++------- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 8 +++++++- + 2 files changed, 28 insertions(+), 8 deletions(-) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +index 98a6952..6de8140 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +@@ -1622,6 +1622,11 @@ restartinit: + HTMemMapInit_D(pMCTstat, pDCTstatA); /* Map local memory into system address space.*/ + mctHookAfterHTMap(); + ++ if (!is_fam15h()) { ++ printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); ++ CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ ++ } ++ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n"); + mctHookAfterCPU(); /* Setup external northbridge(s) */ + +@@ -1645,6 +1650,11 @@ restartinit: + printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); + DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ + ++ if (!is_fam15h()) { ++ printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); ++ UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ ++ } ++ + if (!allow_config_restore) { + printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n"); + mct_OtherTiming(pMCTstat, pDCTstatA); +@@ -1665,11 +1675,13 @@ restartinit: + MCTMemClr_D(pMCTstat,pDCTstatA); + } + +- printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); +- CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ ++ if (is_fam15h()) { ++ printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); ++ CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ + +- printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); +- UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ ++ printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); ++ UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ ++ } + + printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { +@@ -6332,11 +6344,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, + DramMRS |= 1 << 1; + + dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); +- dword |= DramMRS; +- if (is_fam15h()) ++ if (is_fam15h()) { ++ dword |= DramMRS; + dword &= ~0x00800003; +- else ++ } else { + dword &= ~0x00fc2f8f; ++ dword |= DramMRS; ++ } + Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x84, dword); + } + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +index 039fcf8..1d41aa4 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +@@ -909,9 +909,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, + * Flush the receiver FIFO + * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO + */ +- ++ /* FIXME ++ * This does not seem to be needed, and has a tendency to lock up the ++ * boot process while attempting to write the test pattern. ++ */ ++#if 0 ++ SetUpperFSbase(TestAddr0); + WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1); + mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0); ++#endif + } + MaxDelay_CH[Channel] = CTLRMaxDelay; + } +-- +1.7.9.5 + |