diff options
Diffstat (limited to 'resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch deleted file mode 100644 index 285d836..0000000 --- a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch +++ /dev/null @@ -1,65 +0,0 @@ -From e1da6392d60e4735e8b972fd20e009c2686ab638 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <tpearson@raptorengineeringinc.com> -Date: Thu, 27 Aug 2015 13:19:34 -0500 -Subject: [PATCH 127/143] northbridge/amd/amdmct/mct_ddr3: Fix odd rank data - corruption due to incorrect DQS training - -Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178 -Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> ---- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 25 ++++++++++++++++-------- - 1 file changed, 17 insertions(+), 8 deletions(-) - -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c -index c520515..739a893 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c -@@ -1324,9 +1324,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, - Receiver = receiver_start; - - /* There are four receiver pairs, loosely associated with chipselects. -- * This is essentially looping over each DIMM. -+ * This is essentially looping over each rank within each DIMM. - */ -- for (; Receiver < receiver_end; Receiver += 2) { -+ for (; Receiver < receiver_end; Receiver++) { - dimm = (Receiver >> 1); - if ((Receiver & 0x1) == 0) { - /* Even rank of DIMM */ -@@ -1340,18 +1340,27 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, - continue; - } - -+#if DQS_TRAIN_DEBUG > 0 -+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: Training DQS read/write position for receiver %d (DIMM %d)\n", Receiver, dimm); -+#endif -+ - /* Initialize variables */ - for (lane = lane_start; lane < lane_end; lane++) { - passing_dqs_delay_found[lane] = 0; - } -- memset(dqs_results_array, 0, sizeof(dqs_results_array)); -+ if ((Receiver & 0x1) == 0) { -+ /* Even rank of DIMM */ -+ memset(dqs_results_array, 0, sizeof(dqs_results_array)); -+ -+ /* Read initial read / write DQS delays */ -+ read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg); -+ read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); - -- /* Read initial read / write DQS delays */ -- read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg); -- read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); -+ /* Read current settings of other (previously trained) lanes */ -+ read_dqs_write_data_timing_registers(initial_write_data_timing, dev, dct, dimm, index_reg); -+ } - -- /* Read current settings of other (previously trained) lanes */ -- read_dqs_write_data_timing_registers(initial_write_data_timing, dev, dct, dimm, index_reg); -+ /* Initialize iterators */ - memcpy(current_write_data_delay, initial_write_data_timing, sizeof(current_write_data_delay)); - - for (lane = lane_start; lane < lane_end; lane++) { --- -1.7.9.5 - |