diff options
Diffstat (limited to 'resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch | 200 |
1 files changed, 200 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch new file mode 100644 index 0000000..acdc33b --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch @@ -0,0 +1,200 @@ +From a7fcc0967128317b5c3dcdfffa7fb8e28210573f Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Sat, 21 May 2016 01:56:01 +1000 +Subject: [PATCH] nb/intel/x4x: Add DMI init + +Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8 +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + +diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc +index 34d9b0f..3520944 100644 +--- a/src/northbridge/intel/x4x/Makefile.inc ++++ b/src/northbridge/intel/x4x/Makefile.inc +@@ -20,6 +20,7 @@ + romstage-y += raminit.c + romstage-y += raminit_ddr2.c + romstage-y += ram_calc.c ++romstage-y += pcie.c + + ramstage-y += acpi.c + ramstage-y += ram_calc.c +diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c +new file mode 100644 +index 0000000..69a2741 +--- /dev/null ++++ b/src/northbridge/intel/x4x/pcie.c +@@ -0,0 +1,161 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <stdint.h> ++#include <stddef.h> ++#include <string.h> ++#include <arch/io.h> ++#include <device/pci_def.h> ++#include <device/pnp_def.h> ++#include <console/console.h> ++ ++#include "iomap.h" ++#include "x4x.h" ++ ++#define DEFAULT_RCBA 0xfed1c000 ++ ++static void init_egress(void) ++{ ++ EPBAR32(0x00) = 0x04010002; ++ EPBAR32(0x04) = 0x00000001; ++ EPBAR32(0x10) = 0x00000001; ++ EPBAR32(0x14) = 0x80000001; ++ EPBAR32(0x1c) = 0x00008001; ++ EPBAR32(0x40) = 0x00010005; ++ EPBAR32(0x44) = 0x00010301; ++ EPBAR32(0x50) = 0x01010001; ++ EPBAR32(0x58) = DEFAULT_DMIBAR; ++ EPBAR32(0x60) = 0x02010003; ++ EPBAR32(0x68) = 0x00008000; ++ EPBAR32(0x70) = 0x03000002; ++ EPBAR32(0x78) = 0x00030000; ++ ++ EPBAR32(0x20) = 0x81000080; ++} ++ ++static void init_dmi(void) ++{ ++ DMIBAR32(0x0000) = 0x04010002; ++ DMIBAR32(0x0004) = 0x00000001; ++ DMIBAR32(0x0010) = 0x00000001; ++ DMIBAR32(0x0014) = 0x80000001; ++ DMIBAR32(0x001c) = 0x00008001; ++ ++ DMIBAR32(0x0020) = 0x81000080; ++ ++ DMIBAR32(0x0028) = 0x00000001; ++ DMIBAR32(0x002c) = 0x86000000; ++ DMIBAR32(0x0040) = 0x08010005; ++ DMIBAR32(0x0044) = 0x01010202; ++ DMIBAR32(0x0050) = 0x00020001; ++ DMIBAR32(0x0058) = DEFAULT_RCBA; ++ DMIBAR32(0x0060) = 0x00010001; ++ DMIBAR32(0x0068) = DEFAULT_EPBAR; ++ DMIBAR32(0x0080) = 0x00010006; ++ DMIBAR32(0x0084) = 0x00012c41; ++ DMIBAR32(0x0088) = 0x00410000; ++ DMIBAR32(0x00f0) = 0x00012000; ++ DMIBAR32(0x00f4) = 0x33fe0037; ++ DMIBAR32(0x00fc) = 0xf000f004; ++ ++ DMIBAR32(0x01b0) = 0x00400000; ++ DMIBAR32(0x01b4) = 0x00008000; ++ DMIBAR32(0x01b8) = 0x000018f2; ++ DMIBAR32(0x01bc) = 0x00000018; ++ DMIBAR32(0x01cc) = 0x00060010; ++ DMIBAR32(0x01d4) = 0x00002000; ++ DMIBAR32(0x0200) = 0x00400f26; ++ DMIBAR32(0x0204) = 0x0001313f; ++ DMIBAR32(0x0208) = 0x00007cb0; ++ DMIBAR32(0x0210) = 0x00000101; ++ DMIBAR32(0x0214) = 0x0007000f; ++ DMIBAR32(0x0224) = 0x00030005; ++ DMIBAR32(0x0230) = 0x2800000e; ++ DMIBAR32(0x0234) = 0x4abcb5bc; ++ DMIBAR32(0x0250) = 0x00000007; ++ ++ DMIBAR32(0x0c00) = 0x0000003c; ++ DMIBAR32(0x0c04) = 0x16000000; ++ DMIBAR32(0x0c0c) = 0x00001fff; ++ DMIBAR32(0x0c10) = 0x0000b100; ++ DMIBAR32(0x0c24) = 0xffff0038; ++ DMIBAR32(0x0c28) = 0x0000000e; ++ DMIBAR32(0x0c2c) = 0x003c0008; ++ DMIBAR32(0x0c30) = 0x02000180; ++ DMIBAR32(0x0c34) = 0x10040071; ++ DMIBAR32(0x0d60) = 0x00000001; ++ DMIBAR32(0x0d6c) = 0x00000300; ++ DMIBAR32(0x0d74) = 0x00000020; ++ DMIBAR32(0x0d78) = 0x00220000; ++ DMIBAR32(0x0d7c) = 0x111f727c; ++ DMIBAR32(0x0d80) = 0x00001409; ++ DMIBAR32(0x0d88) = 0x000f1867; ++ DMIBAR32(0x0d8c) = 0x013000fc; ++ DMIBAR32(0x0da4) = 0x00009757; ++ DMIBAR32(0x0da8) = 0x00000078; ++ DMIBAR32(0x0e00) = 0x000d034e; ++ DMIBAR32(0x0e04) = 0x01880880; ++ DMIBAR32(0x0e08) = 0x01000060; ++ DMIBAR32(0x0e0c) = 0x00000080; ++ DMIBAR32(0x0e10) = 0xbe000000; ++ DMIBAR32(0x0e18) = 0x000000e3; ++ DMIBAR32(0x0e20) = 0x000d034e; ++ DMIBAR32(0x0e24) = 0x01880880; ++ DMIBAR32(0x0e28) = 0x01000060; ++ DMIBAR32(0x0e2c) = 0x00000080; ++ DMIBAR32(0x0e30) = 0xbe000000; ++ DMIBAR32(0x0e38) = 0x000000e3; ++ DMIBAR32(0x0e40) = 0x000d034e; ++ DMIBAR32(0x0e44) = 0x01880880; ++ DMIBAR32(0x0e48) = 0x01000060; ++ DMIBAR32(0x0e4c) = 0x00000080; ++ DMIBAR32(0x0e50) = 0xbe000000; ++ DMIBAR32(0x0e58) = 0x000000e3; ++ DMIBAR32(0x0e60) = 0x000d034e; ++ DMIBAR32(0x0e64) = 0x01880880; ++ DMIBAR32(0x0e68) = 0x01000060; ++ DMIBAR32(0x0e6c) = 0x00000080; ++ DMIBAR32(0x0e70) = 0xbe000000; ++ DMIBAR32(0x0e78) = 0x000000e3; ++ ++ DMIBAR32(0x0e14) = 0xce00381b; ++ DMIBAR32(0x0e34) = 0x4000781b; ++ DMIBAR32(0x0e54) = 0x5c00781b; ++ DMIBAR32(0x0e74) = 0x5400381b; ++ ++ DMIBAR32(0x0218) = 0x0b6202c1; ++ DMIBAR32(0x021c) = 0x02c202c2; ++ ++ DMIBAR32(0x0334) = 0x00b904b3; ++ DMIBAR32(0x0338) = 0x004e0000; ++ ++ DMIBAR32(0x0300) = 0x00a70f4c; ++ DMIBAR32(0x0304) = 0x00a90f54; ++ DMIBAR32(0x0308) = 0x00d103c4; ++ DMIBAR32(0x030c) = 0x003c0e10; ++ DMIBAR32(0x0310) = 0x003d0e11; ++ DMIBAR32(0x0314) = 0x00640000; ++ DMIBAR32(0x0318) = 0x00320c86; ++ DMIBAR32(0x031c) = 0x003a0ca6; ++ DMIBAR32(0x0324) = 0x00040010; ++ DMIBAR32(0x0328) = 0x00040000; ++} ++ ++void x4x_late_init(void) ++{ ++ init_egress(); ++ init_dmi(); ++} +diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h +index e1ef745..17810aa 100644 +--- a/src/northbridge/intel/x4x/x4x.h ++++ b/src/northbridge/intel/x4x/x4x.h +@@ -315,6 +315,7 @@ + + #ifndef __BOOTBLOCK__ + void x4x_early_init(void); ++void x4x_late_init(void); + u32 decode_igd_memory_size(u32 gms); + u32 decode_igd_gtt_size(u32 gsm); + u8 decode_pciebar(u32 *const base, u32 *const len); |