diff options
Diffstat (limited to 'resources/libreboot/patch/chromebook')
2 files changed, 173 insertions, 0 deletions
diff --git a/resources/libreboot/patch/chromebook/0001-armv7-Word-sized-half-word-sized-memory-operations-f.patch b/resources/libreboot/patch/chromebook/0001-armv7-Word-sized-half-word-sized-memory-operations-f.patch new file mode 100644 index 0000000..f89b160 --- /dev/null +++ b/resources/libreboot/patch/chromebook/0001-armv7-Word-sized-half-word-sized-memory-operations-f.patch @@ -0,0 +1,89 @@ +From 9746b7bf27d4a3c7c0de78b26ec9f217887f4e7d Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <contact@paulk.fr> +Date: Tue, 22 Sep 2015 22:16:33 +0200 +Subject: [PATCH 1/2] armv7: Word-sized/half-word-sized memory operations for + 32/16 bit read/write + +Some registers only allow word-sized or half-word-sized operations and will +cause a data fault when accessed with byte-sized operations. +However, the compiler may or may not break such an operation into smaller +(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for +32 bit read/write and half-word-sized operations for 16 bit read/write. + +This is particularly the case on the rk3288 SRAM registers, where the watchdog +tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the +compiler, where a 32 bit read would be broken into byte-sized chunks, which +caused a data fault when accessing the watchdog tombstone register. + +The definitions for byte-sized memory operations are also adapted to stay +consistent with the rest. + +Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede +Signed-off-by: Paul Kocialkowski <contact@paulk.fr> +--- + src/arch/arm/include/armv7/arch/io.h | 21 +++++++++++++++------ + 1 file changed, 15 insertions(+), 6 deletions(-) + +diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h +index 9d06003..94cb131 100644 +--- a/src/arch/arm/include/armv7/arch/io.h ++++ b/src/arch/arm/include/armv7/arch/io.h +@@ -29,40 +29,49 @@ + + static inline uint8_t read8(const void *addr) + { ++ uint8_t val; ++ + dmb(); +- return *(volatile uint8_t *)addr; ++ asm volatile ("ldrb %0, [%1]" : "=r" (val) : "r" (addr) : "memory"); ++ return val; + } + + static inline uint16_t read16(const void *addr) + { ++ uint16_t val; ++ + dmb(); +- return *(volatile uint16_t *)addr; ++ asm volatile ("ldrh %0, [%1]" : "=r" (val) : "r" (addr) : "memory"); ++ return val; + } + + static inline uint32_t read32(const void *addr) + { ++ uint32_t val; ++ + dmb(); +- return *(volatile uint32_t *)addr; ++ asm volatile ("ldr %0, [%1]" : "=r" (val) : "r" (addr) : "memory"); ++ return val; + } + + static inline void write8(void *addr, uint8_t val) + { + dmb(); +- *(volatile uint8_t *)addr = val; ++ asm volatile ("strb %0, [%1]" : : "r" (val), "r" (addr) : "memory"); + dmb(); + } + + static inline void write16(void *addr, uint16_t val) + { + dmb(); +- *(volatile uint16_t *)addr = val; ++ asm volatile ("strh %0, [%1]" : : "r" (val), "r" (addr) : "memory"); + dmb(); + } + + static inline void write32(void *addr, uint32_t val) + { + dmb(); +- *(volatile uint32_t *)addr = val; ++ asm volatile ("str %0, [%1]" : : "r" (val), "r" (addr) : "memory"); + dmb(); + } + +-- +1.9.1 + diff --git a/resources/libreboot/patch/chromebook/0002-chromeos-Allow-disabling-vboot-firmware-verification.patch b/resources/libreboot/patch/chromebook/0002-chromeos-Allow-disabling-vboot-firmware-verification.patch new file mode 100644 index 0000000..bed24b1 --- /dev/null +++ b/resources/libreboot/patch/chromebook/0002-chromeos-Allow-disabling-vboot-firmware-verification.patch @@ -0,0 +1,84 @@ +From d0e6324693214c51e707928e26571ecc9ab8ee03 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <contact@paulk.fr> +Date: Sun, 9 Aug 2015 10:23:38 +0200 +Subject: [PATCH 2/2] chromeos: Allow disabling vboot firmware verification + when ChromeOS is enabled + +Some ChromeOS bindings might be wanted without using vboot verification, for +instance to boot up depthcharge from the version of Coreboot installed in the +write-protected part of the SPI flash (without jumping to a RW firmware). + +Vboot firmware verification is still selected by default when ChromeOS is +enabled, but this allows more flexibility since vboot firmware verification is +no longer a hard requirement for ChromeOS (that this particular use case still +allows booting ChromeOS). + +In the future, it would make sense to have all the separate components that +CONFIG_CHROMEOS enables have their own config options, so that they can be +enabled separately. + +Change-Id: Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb +Signed-off-by: Paul Kocialkowski <contact@paulk.fr> +--- + src/lib/bootmode.c | 2 ++ + src/vendorcode/google/chromeos/Kconfig | 2 +- + src/vendorcode/google/chromeos/vboot2/Kconfig | 4 ++++ + 3 files changed, 7 insertions(+), 1 deletion(-) + +diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c +index f2ff72a..13c0130 100644 +--- a/src/lib/bootmode.c ++++ b/src/lib/bootmode.c +@@ -80,8 +80,10 @@ void gfx_set_init_done(int done) + int display_init_required(void) + { + /* For Chrome OS always honor vboot_skip_display_init(). */ ++#if CONFIG_VBOOT_VERIFY_FIRMWARE + if (IS_ENABLED(CONFIG_CHROMEOS)) + return !vboot_skip_display_init(); ++#endif + + /* By default always initialize display. */ + return 1; +diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig +index 8309d19..694e0d7 100644 +--- a/src/vendorcode/google/chromeos/Kconfig ++++ b/src/vendorcode/google/chromeos/Kconfig +@@ -31,7 +31,6 @@ config CHROMEOS + select BOOTMODE_STRAPS + select ELOG + select COLLECT_TIMESTAMPS +- select VBOOT_VERIFY_FIRMWARE + help + Enable ChromeOS specific features like the GPIO sub table in + the coreboot table. NOTE: Enabling this option on an unsupported +@@ -129,6 +128,7 @@ config VIRTUAL_DEV_SWITCH + + config VBOOT_VERIFY_FIRMWARE + bool "Verify firmware with vboot." ++ default y if CHROMEOS + default n + depends on HAVE_HARD_RESET + help +diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig +index 33c33a5..5bd8b54 100644 +--- a/src/vendorcode/google/chromeos/vboot2/Kconfig ++++ b/src/vendorcode/google/chromeos/vboot2/Kconfig +@@ -16,6 +16,8 @@ + ## Foundation, Inc. + ## + ++if VBOOT_VERIFY_FIRMWARE ++ + config VBOOT_STARTS_IN_BOOTBLOCK + bool "Vboot starts verifying in bootblock" + default n +@@ -133,3 +135,5 @@ config VBOOT_DYNAMIC_WORK_BUFFER + ram to allocate the vboot work buffer. That means vboot verification + is after memory init and requires main memory to back the work + buffer. ++ ++endif # VBOOT_VERIFY_FIRMWARE +-- +1.9.1 + |