kgpe-d6,kcma-d8,kfsn4-dre: use cb 67e11d1e4f5fa4ba7e864bb0487bf5a835fb2919

This revision is reported to work correctly.

9 files changed, 0 insertions, 222 deletions

diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
index 6427863..6427863 100644
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
deleted file mode 100644
index 905d73d..0000000
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 9761ddff5c8e47d7b5321a8c98383970b4fb8683 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 7 Mar 2016 09:10:31 -0600
-Subject: [PATCH 1/2] nb/amd/mct_ddr3: Restore previous DQS delay values on
- failed loop
-
-Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 19a7acb..1a3c7c1 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-@@ -1522,6 +1522,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4);
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4);
- 			} else {
-+				 /* Restore current settings of other (previously trained) lanes to the active array */
-+				memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay));
-+
- 				/* Reprogram the Read DQS Timing Control register with the original settings */
- 				write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
- 			}
-@@ -1571,6 +1574,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4);
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4);
- 			} else {
-+				/* Restore current settings of other (previously trained) lanes to the active array */
-+				memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay));
-+
- 				/* Reprogram the Write DQS Timing Control register with the original settings */
- 				write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg);
- 			}
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
deleted file mode 100644
index f866dda..0000000
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kcma-d8/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 3119f40c2e0abc36630a92fc5cee58b8d0f9087c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 7 Mar 2016 13:29:24 -0600
-Subject: [PATCH 2/2] nb/amd/mct_ddr3: Train correct receiver in
- TrainDQSRdWrPos_D_Fam15
-
-Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 1a3c7c1..ad81c3d 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-@@ -1340,14 +1340,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 
- 	Errors = 0;
- 	dual_rank = 0;
--	Receiver = mct_InitReceiver_D(pDCTstat, dct);
--	if (receiver_start > Receiver)
--		Receiver = receiver_start;
- 
- 	/* There are four receiver pairs, loosely associated with chipselects.
- 	 * This is essentially looping over each rank within each DIMM.
- 	 */
--	for (; Receiver < receiver_end; Receiver++) {
-+	for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) {
- 		dimm = (Receiver >> 1);
- 		if ((Receiver & 0x1) == 0) {
- 			/* Even rank of DIMM */
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
index 6427863..6427863 100644
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
deleted file mode 100644
index 905d73d..0000000
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 9761ddff5c8e47d7b5321a8c98383970b4fb8683 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 7 Mar 2016 09:10:31 -0600
-Subject: [PATCH 1/2] nb/amd/mct_ddr3: Restore previous DQS delay values on
- failed loop
-
-Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 19a7acb..1a3c7c1 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-@@ -1522,6 +1522,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4);
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4);
- 			} else {
-+				 /* Restore current settings of other (previously trained) lanes to the active array */
-+				memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay));
-+
- 				/* Reprogram the Read DQS Timing Control register with the original settings */
- 				write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
- 			}
-@@ -1571,6 +1574,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4);
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4);
- 			} else {
-+				/* Restore current settings of other (previously trained) lanes to the active array */
-+				memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay));
-+
- 				/* Reprogram the Write DQS Timing Control register with the original settings */
- 				write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg);
- 			}
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
deleted file mode 100644
index f866dda..0000000
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 3119f40c2e0abc36630a92fc5cee58b8d0f9087c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 7 Mar 2016 13:29:24 -0600
-Subject: [PATCH 2/2] nb/amd/mct_ddr3: Train correct receiver in
- TrainDQSRdWrPos_D_Fam15
-
-Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 1a3c7c1..ad81c3d 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-@@ -1340,14 +1340,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 
- 	Errors = 0;
- 	dual_rank = 0;
--	Receiver = mct_InitReceiver_D(pDCTstat, dct);
--	if (receiver_start > Receiver)
--		Receiver = receiver_start;
- 
- 	/* There are four receiver pairs, loosely associated with chipselects.
- 	 * This is essentially looping over each rank within each DIMM.
- 	 */
--	for (; Receiver < receiver_end; Receiver++) {
-+	for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) {
- 		dimm = (Receiver >> 1);
- 		if ((Receiver & 0x1) == 0) {
- 			/* Even rank of DIMM */
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
index 6427863..6427863 100644
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
deleted file mode 100644
index 905d73d..0000000
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 9761ddff5c8e47d7b5321a8c98383970b4fb8683 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 7 Mar 2016 09:10:31 -0600
-Subject: [PATCH 1/2] nb/amd/mct_ddr3: Restore previous DQS delay values on
- failed loop
-
-Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 19a7acb..1a3c7c1 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-@@ -1522,6 +1522,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4);
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4);
- 			} else {
-+				 /* Restore current settings of other (previously trained) lanes to the active array */
-+				memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay));
-+
- 				/* Reprogram the Read DQS Timing Control register with the original settings */
- 				write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
- 			}
-@@ -1571,6 +1574,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4);
- 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4);
- 			} else {
-+				/* Restore current settings of other (previously trained) lanes to the active array */
-+				memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay));
-+
- 				/* Reprogram the Write DQS Timing Control register with the original settings */
- 				write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg);
- 			}
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
deleted file mode 100644
index f866dda..0000000
--- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kgpe-d16/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 3119f40c2e0abc36630a92fc5cee58b8d0f9087c Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 7 Mar 2016 13:29:24 -0600
-Subject: [PATCH 2/2] nb/amd/mct_ddr3: Train correct receiver in
- TrainDQSRdWrPos_D_Fam15
-
-Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-index 1a3c7c1..ad81c3d 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
-@@ -1340,14 +1340,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
- 
- 	Errors = 0;
- 	dual_rank = 0;
--	Receiver = mct_InitReceiver_D(pDCTstat, dct);
--	if (receiver_start > Receiver)
--		Receiver = receiver_start;
- 
- 	/* There are four receiver pairs, loosely associated with chipselects.
- 	 * This is essentially looping over each rank within each DIMM.
- 	 */
--	for (; Receiver < receiver_end; Receiver++) {
-+	for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) {
- 		dimm = (Receiver >> 1);
- 		if ((Receiver & 0x1) == 0) {
- 			/* Even rank of DIMM */
--- 
-1.9.1
-