diff options
| author | Francis Rowe <info@gluglug.org.uk> | 2015-10-18 19:12:53 (EDT) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-10-18 21:32:36 (EDT) |
| commit | 0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch) | |
| tree | 4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | |
| parent | 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff) | |
| download | libreboot-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip libreboot-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz libreboot-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.bz2 | |
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed
Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch b/resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch new file mode 100644 index 0000000..0e10cc9 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch @@ -0,0 +1,30 @@ +From 5428b15fb1aef85b47fbbb117d943d2525a84692 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Fri, 14 Aug 2015 02:50:44 -0500 +Subject: [PATCH 116/139] southbridge/amd/sr5650: Use correct PCI configuration + block offset + +Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl +index a6ab114..1e0d5b0 100644 +--- a/src/southbridge/amd/sr5650/acpi/sr5650.asl ++++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl +@@ -19,8 +19,8 @@ + */ + + Scope(\) { +- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ +- Name(HPBA, 0xFED00000) /* Base address of HPET table */ ++ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ ++ Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) +-- +1.9.1 + |