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| author | Francis Rowe <info@gluglug.org.uk> | 2015-10-18 19:12:53 (EDT) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-10-18 21:32:36 (EDT) |
| commit | 0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch) | |
| tree | 4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch | |
| parent | 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff) | |
| download | libreboot-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip libreboot-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz libreboot-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.bz2 | |
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed
Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch b/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch deleted file mode 100644 index ed6ae69..0000000 --- a/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch +++ /dev/null @@ -1,55 +0,0 @@ -From f2495e7909302bd8cbc0633bde5a9ce60a6336c5 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <kb9vqf@pearsoncomputing.net> -Date: Thu, 13 Aug 2015 17:45:12 -0500 -Subject: [PATCH 114/146] southbridge/amd/sr5650: Hide clock configuration - device after setup is complete - ---- - src/southbridge/amd/sr5650/early_setup.c | 16 ++++++++-------- - src/southbridge/amd/sr5650/pcie.c | 3 +++ - 2 files changed, 11 insertions(+), 8 deletions(-) - -diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c -index e7cca06..cb666db 100644 ---- a/src/southbridge/amd/sr5650/early_setup.c -+++ b/src/southbridge/amd/sr5650/early_setup.c -@@ -414,14 +414,14 @@ static void sr5650_por_misc_index_init(device_t nb_dev) - set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310); - - /* NBCFG (NBMISCIND 0x0): NB_CNTL - -- * HIDE_NB_AGP_CAP ([0], default=1)HIDE -- * HIDE_P2P_AGP_CAP ([1], default=1)HIDE -- * HIDE_NB_GART_BAR ([2], default=1)HIDE -- * HIDE_MMCFG_BAR ([3], default=1)SHOW -- * AGPMODE30 ([4], default=0)DISABLE -- * AGP30ENCHANCED ([5], default=0)DISABLE -- * HIDE_AGP_CAP ([8], default=1)ENABLE */ -- set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6); -+ * HIDE_NB_AGP_CAP ([0], default=1)HIDE -+ * HIDE_P2P_AGP_CAP ([1], default=1)HIDE -+ * HIDE_NB_GART_BAR ([2], default=1)HIDE -+ * HIDE_MMCFG_BAR ([3], default=1)SHOW -+ * AGPMODE30 ([4], default=0)DISABLE -+ * AGP30ENCHANCED ([5], default=0)DISABLE -+ * HIDE_CLKCFG_HEADER ([8], default=0)SHOW */ -+ set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8); - - /* IOC_LAT_PERF_CNTR_CNTL */ - set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); -diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c -index 09ce217..360e9cb 100644 ---- a/src/southbridge/amd/sr5650/pcie.c -+++ b/src/southbridge/amd/sr5650/pcie.c -@@ -854,6 +854,9 @@ void sr56x0_lock_hwinitreg(void) - - /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */ - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); -+ -+ /* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */ -+ set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8); - } - - /***************************************** --- -1.7.9.5 - |