KGPE-D16: update patch set (also update coreboot and vboot)

Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed

Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.

1 files changed, 0 insertions, 70 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch b/resources/libreboot/patch/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch
deleted file mode 100644
index 014029d..0000000
--- a/resources/libreboot/patch/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 3a8253f5cd0093c33294f8c8399acaa60100b880 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Fri, 7 Aug 2015 19:06:09 -0500
-Subject: [PATCH 100/146] northbridge/amd/amdfam10: Fix poor performance on
- Family 15h CPUs
-
----
- src/northbridge/amd/amdfam10/nb_control.c  |    4 ++--
- src/northbridge/amd/amdfam10/northbridge.c |   21 +++++++++++++++++++++
- 2 files changed, 23 insertions(+), 2 deletions(-)
-
-diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c
-index f95b6f8..8e8dd57 100644
---- a/src/northbridge/amd/amdfam10/nb_control.c
-+++ b/src/northbridge/amd/amdfam10/nb_control.c
-@@ -60,10 +60,10 @@ static void nb_control_init(struct device *dev)
- 	pci_write_config32(dev, 0xe0, dword);
- 
- 	/* Configure northbridge P-states */
--	dword = pci_read_config32(dev, 0xe0);
-+	dword = pci_read_config32(dev, 0x170);
- 	dword &= ~(0x7 << 9);			/* NbPstateThreshold = compute_unit_count */
- 	dword |= (compute_unit_count & 0x7) << 9;
--	pci_write_config32(dev, 0xe0, dword);
-+	pci_write_config32(dev, 0x170, dword);
- 
- 	printk(BIOS_DEBUG, "done.\n");
- }
-diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
-index 2c8ee08..a60daf9 100644
---- a/src/northbridge/amd/amdfam10/northbridge.c
-+++ b/src/northbridge/amd/amdfam10/northbridge.c
-@@ -1755,6 +1755,8 @@ static void detect_and_enable_probe_filter(device_t dev)
- 
- 		disable_cache();
- 		asm("wbinvd");
-+
-+		/* Enable probe filter */
- 		for (i = 0; i < sysconf.nodes; i++) {
- 			device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
- 
-@@ -1771,6 +1773,25 @@ static void detect_and_enable_probe_filter(device_t dev)
- 			do {
- 			} while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19)));
- 		}
-+
-+		if (is_fam15h()) {
-+			printk(BIOS_DEBUG, "Enabling ATM mode\n");
-+
-+			/* Enable ATM mode */
-+			for (i = 0; i < sysconf.nodes; i++) {
-+				device_t f0x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
-+				device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
-+
-+				dword = pci_read_config32(f0x_dev, 0x68);
-+				dword |= (0x1 << 12);	/* ATMModeEn = 1 */
-+				pci_write_config32(f0x_dev, 0x68, dword);
-+
-+				dword = pci_read_config32(f3x_dev, 0x1b8);
-+				dword |= (0x1 << 27);	/* L3ATMModeEn = 1 */
-+				pci_write_config32(f3x_dev, 0x1b8, dword);
-+			}
-+		}
-+
- 		enable_cache();
- 
- 		/* Reenable L3 and DRAM scrubbers */
--- 
-1.7.9.5
-