KGPE-D16: update patch set (also update coreboot and vboot)

Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed

Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.

1 files changed, 0 insertions, 62 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch b/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch
deleted file mode 100644
index 842202e..0000000
--- a/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 6212e218fbd616d7ddeb74fffd883741ba40a6d6 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Sun, 2 Aug 2015 21:31:48 -0500
-Subject: [PATCH 095/146] cpu/amd/model_10xxx: Fix incorrect revision
- detection
-
----
- src/cpu/amd/model_10xxx/fidvid.c |   10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
-index fe1cfb4..1d55275 100644
---- a/src/cpu/amd/model_10xxx/fidvid.c
-+++ b/src/cpu/amd/model_10xxx/fidvid.c
-@@ -375,7 +375,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
- 	pci_write_config32(dev, 0xd8, dtemp);
- }
- 
--static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
-+static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) {
-         u8 link0isGen3 = 0;
-         u8 offset;
-         if (AMD_CpuFindCapability(node, 0, &offset)) {
-@@ -446,7 +446,7 @@ static u32 power_up_down(int node, u8 procPkg) {
-         return dword;
- }
- 
--static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
-+static void config_clk_power_ctrl_reg0(int node, uint64_t cpuRev, uint8_t procPkg) {
-        	device_t dev = NODE_PCI(node, 3);
- 
- 	/* Program fields in Clock Power/Control register0 (F3xD4) */
-@@ -471,7 +471,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
- 
- }
- 
--static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
-+static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
- 	/* check PVI/SVI */
- 	u32 dword = pci_read_config32(dev, 0xa0);
- 
-@@ -504,7 +504,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
- 	pci_write_config32(dev, 0xa0, dword);
- }
- 
--static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
-+static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) {
- 	/* Note the following settings are additional from the ported
- 	 * function setFidVidRegs()
- 	 */
-@@ -526,7 +526,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
- 	pci_write_config32(dev, 0xdc, dword);
- }
- 
--static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
-+static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
- 	if (is_fam15h()) {
- 		/* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */
- 		pci_write_config32(dev, 0x80, 0xe20be281);
--- 
-1.7.9.5
-