New board: ASUS KGPE-D16

coreboot build errors:

In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
 static inline enum cb_err get_option(void *dest, const char *name)
                           ^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
 enum cb_err get_option(void *dest, const char *name);

Ping tpearson about this.

Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.

1 files changed, 40 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch b/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch
new file mode 100644
index 0000000..c269358
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch
@@ -0,0 +1,40 @@
+From d78d6f37c04273b66bc0de4ea62deea5c033bf97 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+Date: Thu, 25 Jun 2015 18:37:45 -0500
+Subject: [PATCH 076/146] northbridge/amd/amdmct/mct_ddr3: Work around strange
+ phy training issue
+
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c |   16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+index 72c74e6..9c18d12 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+@@ -207,6 +207,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
+ 
+ 		pDCTData->WLCriticalGrossDelayPrevPass = cgd;
+ 
++		if (pDCTstat->Speed != pDCTstat->TargetFreq) {
++			/* FIXME
++			 * Using the Pass 1 training values causes major phy training problems on
++			 * all Family 15h processors I tested (Pass 1 values are randomly too high,
++			 * and Pass 2 cannot lock).
++			 * Figure out why this is and fix it, then remove the bypass code below...
++			 */
++			if (pass == FirstPass) {
++				for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
++					pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane];
++					pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane];
++				}
++				return 0;
++			}
++		}
++
+ 		/* Compensate for occasional noise/instability causing sporadic training failure */
+ 		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
+ 			uint8_t faulty_value_detected = 0;
+-- 
+1.7.9.5
+