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authorFrancis Rowe <info@gluglug.org.uk>2015-11-06 02:45:49 (EST)
committer Francis Rowe <info@gluglug.org.uk>2015-11-06 03:01:51 (EST)
commit60453ff2cbd1befe24959fba1d24f734406444e3 (patch)
tree74a6080455b2b00184fbc4a00503188032773986 /resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch
parent51f5487e7d2c8809bdc7690fe26948064257b34d (diff)
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Update coreboot to new version (use latest stable kgpe-d16 tree)
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch')
-rw-r--r--resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch32
1 files changed, 0 insertions, 32 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch b/resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch
deleted file mode 100644
index 822d763..0000000
--- a/resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 64ad6ee510824d3804a38a538f1822e5313eb3a3 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Fri, 12 Jun 2015 20:10:58 -0500
-Subject: [PATCH 059/139] mainboard/asus/kgpe-d16: Properly configure SR5690
- southbridge PIKE slot
-
-Change-Id: I2f1373905ffd6460ac3c7c21738e2e2a9aa2e463
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/mainboard/asus/kgpe-d16/devicetree.cb | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
-index 18e337e..ada268b 100644
---- a/src/mainboard/asus/kgpe-d16/devicetree.cb
-+++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
-@@ -43,9 +43,9 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
- end
- register "gpp1_configuration" = "0" # Configuration 16:0 default
- register "gpp2_configuration" = "1" # Configuration 8:8
-- #register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
-- register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
-- register "port_enable" = "0x3ffc" # Enable all ports except 0 and 1
-+ register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
-+ register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7
-+ register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured
- end
- chip southbridge/amd/sb700 # Secondary southbridge
- device pci 11.0 on end # SATA
---
-1.9.1
-