New board: ASUS KGPE-D16

coreboot build errors:

In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
 static inline enum cb_err get_option(void *dest, const char *name)
                           ^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
 enum cb_err get_option(void *dest, const char *name);

Ping tpearson about this.

Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.

1 files changed, 101 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0049-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch b/resources/libreboot/patch/kgpe-d16/0049-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch
new file mode 100644
index 0000000..eff8374
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0049-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch
@@ -0,0 +1,101 @@
+From 3632ae70a8596e983588296158045552a0fdf33e Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+Date: Mon, 8 Jun 2015 19:54:56 -0500
+Subject: [PATCH 049/146] northbridge/amd/amdmct: Skip DCT config write to
+ Flash if unchanged
+
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c   |    3 +++
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h   |    1 +
+ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c |   21 +++++++++++++++++++--
+ 3 files changed, 23 insertions(+), 2 deletions(-)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+index 1442340..6d8c23e 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+@@ -1358,6 +1358,7 @@ restartinit:
+ 
+ 		printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
+ 		restore_mct_information_from_nvram(0);
++		pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
+ 
+ 		printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
+ 		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
+@@ -2080,6 +2081,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
+ 
+ 		if (is_fam15h())
+ 			exit_training_mode_fam15(pMCTstat, pDCTstatA);
++
++		pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
+ 	}
+ 
+ 	/* FIXME - currently uses calculated value	TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+index 539ecc3..adf89b2 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+@@ -316,6 +316,7 @@ struct MCTStatStruc {
+ #define GSB_SpIntRemapHole	16	/* Special condition for Node Interleave and HW remapping*/
+ #define GSB_EnDIMMSpareNW	17	/* Indicates that DIMM Spare can be used without a warm reset */
+ 					/* NOTE: This is a local bit used by memory code */
++#define GSB_ConfigRestored	18	/* Training configuration was restored from NVRAM */
+ 
+ /*===============================================================================
+ 	Local DCT Status structure (a structure for each DCT)
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+index 24f78b2..4c0e58d 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+@@ -213,7 +213,7 @@ static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t d
+ 	return pci_read_config32(dev, reg);
+ }
+ 
+-static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data)
++static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored)
+ {
+ 	uint8_t node;
+ 	uint8_t dimm;
+@@ -236,6 +236,13 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data*
+ 	for (node = 0; node < MAX_NODES_SUPPORTED; node++)
+ 		for (channel = 0; channel < 2; channel++)
+ 			persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed;
++
++	if (restored) {
++		if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored))
++			*restored = 1;
++		else
++			*restored = 0;
++	}
+ }
+ 
+ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data)
+@@ -1034,6 +1041,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
+ int8_t save_mct_information_to_nvram(void)
+ {
+ 	uint8_t nvram;
++	uint8_t restored = 0;
+ 
+ 	if (acpi_is_wakeup_s3())
+ 		return 0;
+@@ -1055,7 +1063,16 @@ int8_t save_mct_information_to_nvram(void)
+ 	copy_mct_data_to_save_variable(persistent_data);
+ 
+ 	/* Save RAM SPD data at the same time */
+-	copy_cbmem_spd_data_to_save_variable(persistent_data);
++	copy_cbmem_spd_data_to_save_variable(persistent_data, &restored);
++
++	if (restored) {
++		/* Allow training bypass if DIMM configuration is unchanged on next boot */
++		nvram = 1;
++		set_option("allow_spd_nvram_cache_restore", &nvram);
++
++		printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n");
++		return 0;
++	}
+ 
+ 	/* Obtain CBFS file offset */
+ 	s3nv_offset = get_s3nv_file_offset();
+-- 
+1.7.9.5
+