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| author | Francis Rowe <info@gluglug.org.uk> | 2016-01-30 04:58:46 (EST) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2016-01-30 04:58:46 (EST) |
| commit | 75ab59d4e141d106970f397c31d52ba486117fc9 (patch) | |
| tree | 2c5ae2e910b590b7a8f7be16b38c431c28c23608 /resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0040-cpu-amd-fam10h-fam15h-Add-CMOS-option-to-disable-CPB.patch | |
| parent | a1357659b2a72c349091a0abd7a0276b4fd6946d (diff) | |
| download | libreboot-75ab59d4e141d106970f397c31d52ba486117fc9.zip libreboot-75ab59d4e141d106970f397c31d52ba486117fc9.tar.gz libreboot-75ab59d4e141d106970f397c31d52ba486117fc9.tar.bz2 | |
New board: ASUS KCMA-D8 desktop/workstation motherboard
Diffstat (limited to 'resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0040-cpu-amd-fam10h-fam15h-Add-CMOS-option-to-disable-CPB.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0040-cpu-amd-fam10h-fam15h-Add-CMOS-option-to-disable-CPB.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0040-cpu-amd-fam10h-fam15h-Add-CMOS-option-to-disable-CPB.patch b/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0040-cpu-amd-fam10h-fam15h-Add-CMOS-option-to-disable-CPB.patch new file mode 100644 index 0000000..0559642 --- /dev/null +++ b/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0040-cpu-amd-fam10h-fam15h-Add-CMOS-option-to-disable-CPB.patch @@ -0,0 +1,53 @@ +From 3efdfbd1def5dd2b3bd87ac9ff0bad83c2945eed Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Tue, 24 Nov 2015 14:12:07 -0600 +Subject: [PATCH 40/45] cpu/amd/fam10h-fam15h: Add CMOS option to disable CPB + (core boost) + +On certain systems and CPUs Core Performance Boost (CPB) may cause +sporadic system lockups. This issue is also somewhat known on the +various proprietary BIOSes, therefore it seems to be a hardware +incompatibility when present. + +Allow the user to disable CBP if needed. + +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c +index e2a1bf3..c1ff240 100644 +--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c ++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c +@@ -987,6 +987,7 @@ void cpuSetAMDMSR(uint8_t node_id) + u32 platform; + uint64_t revision; + uint8_t enable_c_states; ++ uint8_t enable_cpb; + + printk(BIOS_DEBUG, "cpuSetAMDMSR "); + +@@ -1078,6 +1079,19 @@ void cpuSetAMDMSR(uint8_t node_id) + enable_c_states = 0; + #endif + ++ if (revision & AMD_FAM15_ALL) { ++ enable_cpb = 1; ++ if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS) ++ enable_cpb = !!nvram; ++ ++ if (!enable_cpb) { ++ /* Disable Core Performance Boost */ ++ msr = rdmsr(0xc0010015); ++ msr.lo |= (0x1 << 25); /* CpbDis = 1 */ ++ wrmsr(0xc0010015, msr); ++ } ++ } ++ + printk(BIOS_DEBUG, " done\n"); + } + +-- +2.1.4 + |