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| author | Francis Rowe <info@gluglug.org.uk> | 2016-01-02 17:10:32 (EST) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2016-01-04 15:28:39 (EST) |
| commit | d1f408f3725aa02bc1d76c4c6aadb4697bd073c0 (patch) | |
| tree | 7eed036543ae1f8c57b56825880a722a8efbedf1 /resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch | |
| parent | 91aec7e72005dcda72d19f2d024a02d8c0f86590 (diff) | |
| download | libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.zip libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.tar.gz libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.tar.bz2 | |
Use different coreboot revisions and patches per board
The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.
At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.
Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.
For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.
Diffstat (limited to 'resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch new file mode 100644 index 0000000..85f519d --- /dev/null +++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch @@ -0,0 +1,37 @@ +From da95ad3fda51ddabb5b5799f459828008f841b4c Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Thu, 27 Aug 2015 13:18:53 -0500 +Subject: [PATCH 126/143] northbridge/amd/amdmct/mct_ddr3: Fix a minor RDIMM + CS select error + +Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +index 624a543..8fd2523 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +@@ -236,7 +236,7 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, + for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) { + if (pDCTstat->CSPresent & (1 << MrsChipSel)) { + val = Get_NB32_DCT(dev, dct, 0xa8); +- val &= ~(0xf << 8); ++ val &= ~(0xff << 8); + + switch (MrsChipSel) { + case 0: +@@ -283,7 +283,7 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, + /* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */ + val = Get_NB32_DCT(dev, dct, 0xa8); + val &= ~(0xff << 8); +- val |= (0x3 << (MrsChipSel & 0xfe)) << 8; ++ val |= (0x3 << (MrsChipSel & ~0x1)) << 8; + Set_NB32_DCT(dev, dct, 0xa8, val); + + /* Resend control word 10 */ +-- +1.7.9.5 + |