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| author | Francis Rowe <info@gluglug.org.uk> | 2016-03-08 01:00:09 (EST) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2016-03-08 02:32:32 (EST) |
| commit | dfa21bb8ee01eac21a2acee79011a634cb67e373 (patch) | |
| tree | 21cd4f855aa03db13abba91400ad3be212b11602 /resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | |
| parent | 2e5e505da125f9d90dd63c1cbcb08bf5316b21ae (diff) | |
| download | libreboot-dfa21bb8ee01eac21a2acee79011a634cb67e373.zip libreboot-dfa21bb8ee01eac21a2acee79011a634cb67e373.tar.gz libreboot-dfa21bb8ee01eac21a2acee79011a634cb67e373.tar.bz2 | |
Update coreboot (kgpe-d16,kcma-d8,kfsn4-dre,d510mo,ga-g41m-es2l)
Update to the latest coreboot and vboot versions at the time of writing:
coreboot 2a3434757ef425dbdfedf1fc69e1a033a6e7310d
vboot d187cd3fc792f8bcefbee4587c83eafbd08441fc
Diffstat (limited to 'resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch deleted file mode 100644 index 27fd1c2..0000000 --- a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f5d5d25583a6aee7f725a6de8cc0a51753502666 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <tpearson@raptorengineeringinc.com> -Date: Fri, 14 Aug 2015 02:50:44 -0500 -Subject: [PATCH 118/143] southbridge/amd/sr5650: Use correct PCI - configuration block offset - -Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc -Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> ---- - src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl -index a6ab114..1e0d5b0 100644 ---- a/src/southbridge/amd/sr5650/acpi/sr5650.asl -+++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl -@@ -19,8 +19,8 @@ - */ - - Scope(\) { -- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ -- Name(HPBA, 0xFED00000) /* Base address of HPET table */ -+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -+ Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) --- -1.7.9.5 - |