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| author | Francis Rowe <info@gluglug.org.uk> | 2016-01-02 17:10:32 (EST) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2016-01-04 15:28:39 (EST) |
| commit | d1f408f3725aa02bc1d76c4c6aadb4697bd073c0 (patch) | |
| tree | 7eed036543ae1f8c57b56825880a722a8efbedf1 /resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch | |
| parent | 91aec7e72005dcda72d19f2d024a02d8c0f86590 (diff) | |
| download | libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.zip libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.tar.gz libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.tar.bz2 | |
Use different coreboot revisions and patches per board
The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.
At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.
Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.
For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.
Diffstat (limited to 'resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch new file mode 100644 index 0000000..42cebaf --- /dev/null +++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch @@ -0,0 +1,57 @@ +From 2976a30c045a1c525095d8a954f26174fbdc532c Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Thu, 13 Aug 2015 17:45:12 -0500 +Subject: [PATCH 114/143] southbridge/amd/sr5650: Hide clock configuration + device after setup is complete + +Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/southbridge/amd/sr5650/early_setup.c | 16 ++++++++-------- + src/southbridge/amd/sr5650/pcie.c | 3 +++ + 2 files changed, 11 insertions(+), 8 deletions(-) + +diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c +index e7cca06..cb666db 100644 +--- a/src/southbridge/amd/sr5650/early_setup.c ++++ b/src/southbridge/amd/sr5650/early_setup.c +@@ -414,14 +414,14 @@ static void sr5650_por_misc_index_init(device_t nb_dev) + set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310); + + /* NBCFG (NBMISCIND 0x0): NB_CNTL - +- * HIDE_NB_AGP_CAP ([0], default=1)HIDE +- * HIDE_P2P_AGP_CAP ([1], default=1)HIDE +- * HIDE_NB_GART_BAR ([2], default=1)HIDE +- * HIDE_MMCFG_BAR ([3], default=1)SHOW +- * AGPMODE30 ([4], default=0)DISABLE +- * AGP30ENCHANCED ([5], default=0)DISABLE +- * HIDE_AGP_CAP ([8], default=1)ENABLE */ +- set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6); ++ * HIDE_NB_AGP_CAP ([0], default=1)HIDE ++ * HIDE_P2P_AGP_CAP ([1], default=1)HIDE ++ * HIDE_NB_GART_BAR ([2], default=1)HIDE ++ * HIDE_MMCFG_BAR ([3], default=1)SHOW ++ * AGPMODE30 ([4], default=0)DISABLE ++ * AGP30ENCHANCED ([5], default=0)DISABLE ++ * HIDE_CLKCFG_HEADER ([8], default=0)SHOW */ ++ set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8); + + /* IOC_LAT_PERF_CNTR_CNTL */ + set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); +diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c +index 09ce217..360e9cb 100644 +--- a/src/southbridge/amd/sr5650/pcie.c ++++ b/src/southbridge/amd/sr5650/pcie.c +@@ -854,6 +854,9 @@ void sr56x0_lock_hwinitreg(void) + + /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */ + set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); ++ ++ /* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */ ++ set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8); + } + + /***************************************** +-- +1.7.9.5 + |