Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 72 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch
new file mode 100644
index 0000000..cca5d53
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch
@@ -0,0 +1,72 @@
+From 718c44eb4a990acd5aedd7a57bacf43ebb7c76a6 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 7 Aug 2015 19:06:09 -0500
+Subject: [PATCH 100/143] northbridge/amd/amdfam10: Fix poor performance on
+ Family 15h CPUs
+
+Change-Id: I193749bc767b7c1139de7cd67622a7b03298009b
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdfam10/nb_control.c  |    4 ++--
+ src/northbridge/amd/amdfam10/northbridge.c |   21 +++++++++++++++++++++
+ 2 files changed, 23 insertions(+), 2 deletions(-)
+
+diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c
+index f95b6f8..8e8dd57 100644
+--- a/src/northbridge/amd/amdfam10/nb_control.c
++++ b/src/northbridge/amd/amdfam10/nb_control.c
+@@ -60,10 +60,10 @@ static void nb_control_init(struct device *dev)
+ 	pci_write_config32(dev, 0xe0, dword);
+ 
+ 	/* Configure northbridge P-states */
+-	dword = pci_read_config32(dev, 0xe0);
++	dword = pci_read_config32(dev, 0x170);
+ 	dword &= ~(0x7 << 9);			/* NbPstateThreshold = compute_unit_count */
+ 	dword |= (compute_unit_count & 0x7) << 9;
+-	pci_write_config32(dev, 0xe0, dword);
++	pci_write_config32(dev, 0x170, dword);
+ 
+ 	printk(BIOS_DEBUG, "done.\n");
+ }
+diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
+index 808cd3a..3a899c8 100644
+--- a/src/northbridge/amd/amdfam10/northbridge.c
++++ b/src/northbridge/amd/amdfam10/northbridge.c
+@@ -1759,6 +1759,8 @@ static void detect_and_enable_probe_filter(device_t dev)
+ 
+ 		disable_cache();
+ 		asm("wbinvd");
++
++		/* Enable probe filter */
+ 		for (i = 0; i < sysconf.nodes; i++) {
+ 			device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+ 
+@@ -1775,6 +1777,25 @@ static void detect_and_enable_probe_filter(device_t dev)
+ 			do {
+ 			} while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19)));
+ 		}
++
++		if (is_fam15h()) {
++			printk(BIOS_DEBUG, "Enabling ATM mode\n");
++
++			/* Enable ATM mode */
++			for (i = 0; i < sysconf.nodes; i++) {
++				device_t f0x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
++				device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
++
++				dword = pci_read_config32(f0x_dev, 0x68);
++				dword |= (0x1 << 12);	/* ATMModeEn = 1 */
++				pci_write_config32(f0x_dev, 0x68, dword);
++
++				dword = pci_read_config32(f3x_dev, 0x1b8);
++				dword |= (0x1 << 27);	/* L3ATMModeEn = 1 */
++				pci_write_config32(f3x_dev, 0x1b8, dword);
++			}
++		}
++
+ 		enable_cache();
+ 
+ 		/* Reenable L3 and DRAM scrubbers */
+-- 
+1.7.9.5
+