Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 58 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch
new file mode 100644
index 0000000..da17100
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch
@@ -0,0 +1,58 @@
+From e4cb65c6451563032f027e526250ac5e4bd614bb Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sat, 27 Jun 2015 17:52:18 -0500
+Subject: [PATCH 080/143] northbridge/amd/amdmct/mct_ddr3: Properly indicate
+ clobbered registers
+
+Change-Id: Icb2754143762bd64ee1df5674fa071de1c595eaf
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h |   11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h
+index f6aa755..cc8d971 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h
+@@ -123,6 +123,9 @@ static void proc_CLFLUSH(u32 addr_hi)
+ 
+ static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num)
+ {
++	uint32_t step = 16;
++	uint32_t count = line_num * 4;
++
+ 	__asm__ volatile (
+ 		/*prevent speculative execution of following instructions*/
+ 		/* FIXME: needed ? */
+@@ -135,7 +138,7 @@ static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num)
+ 		"loop 1b\n\t"
+ 		"mfence\n\t"
+ 
+-		 :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a)
++		 : "+a" (addr_lo), "+d" (step), "+c" (count), "+b" (buf_a) : :
+ 	);
+ 
+ }
+@@ -255,6 +258,10 @@ static void ReadMaxRdLat1CLTestPattern_D(u32 addr)
+ 
+ static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr)
+ {
++	uint32_t addr_phys = addr << 8;
++	uint32_t step = 16;
++	uint32_t count = 3 * 4;
++
+ 	SetUpperFSbase(addr);
+ 
+ 	__asm__ volatile (
+@@ -267,7 +274,7 @@ static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr)
+ 		"loop 1b\n\t"
+ 		"mfence\n\t"
+ 
+-		 :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf)
++		 : "+a" (addr_phys), "+d" (step), "+c" (count), "+b" (buf) : :
+ 	);
+ }
+ 
+-- 
+1.7.9.5
+