Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 120 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch
new file mode 100644
index 0000000..e233545
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch
@@ -0,0 +1,120 @@
+From 2d90214ad2153d723398d5c1175a7dc1769f86a4 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 26 Jun 2015 00:17:10 -0500
+Subject: [PATCH 076/143] northbridge/amd/amdmct/mct_ddr3: Add additional
+ debug trace statements
+
+Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |    8 ++++++++
+ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c |   16 ++++++++++++++++
+ 2 files changed, 24 insertions(+)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+index 999e4ae..6448eb4 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+@@ -5817,7 +5817,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
+ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
+ 					struct DCTStatStruc *pDCTstat, u8 dct)
+ {
++	printk(BIOS_DEBUG, "%s: Start\n", __func__);
++
+ 	mct_ProgramODT_D(pMCTstat, pDCTstat, dct);
++
++	printk(BIOS_DEBUG, "%s: Done\n", __func__);
+ }
+ 
+ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+@@ -5827,6 +5831,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+ 	u32 dword;
+ 	u32 dev = pDCTstat->dev_dct;
+ 
++	printk(BIOS_DEBUG, "%s: Start\n", __func__);
++
+ 	/* FIXME
+ 	 * Mainboards need to be able to specify the maximum number of DIMMs installable per channel
+ 	 * For now assume a maximum of 2 DIMMs per channel can be installed
+@@ -6141,6 +6147,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
+ 			Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
+ 		}
+ 	}
++
++	printk(BIOS_DEBUG, "%s: Done\n", __func__);
+ }
+ 
+ static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+index 51cbf16..380c5f2 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+@@ -192,9 +192,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct)
+ 	u32 dev = pDCTstat->dev_dct;
+ 	u32 val;
+ 
++	printk(BIOS_DEBUG, "%s: Start\n", __func__);
++
+ 	do {
+ 		val = Get_NB32_DCT(dev, dct, 0x98);
+ 	} while (!(val & (1 << DctAccessDone)));
++
++	printk(BIOS_DEBUG, "%s: Done\n", __func__);
+ }
+ 
+ static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct)
+@@ -239,6 +243,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
+ 	u32 dev = pDCTstat->dev_dct;
+ 	u32 val;
+ 
++	printk(BIOS_DEBUG, "%s: Start\n", __func__);
++
+ 	val = Get_NB32_DCT(dev, dct, 0x7c);
+ 	val &= ~0x00ffffff;
+ 	val |= EMRS;
+@@ -248,6 +254,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
+ 	do {
+ 		val = Get_NB32_DCT(dev, dct, 0x7c);
+ 	} while (val & (1 << SendMrsCmd));
++
++	printk(BIOS_DEBUG, "%s: Done\n", __func__);
+ }
+ 
+ static u32 mct_MR2(struct MCTStatStruc *pMCTstat,
+@@ -557,6 +565,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
+ 	u32 dev = pDCTstat->dev_dct;
+ 	u32 dword;
+ 
++	printk(BIOS_DEBUG, "%s: Start\n", __func__);
++
+ 	/*1.Program MrsAddress[10]=1
+ 	  2.Set SendZQCmd=1
+ 	 */
+@@ -573,6 +583,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
+ 
+ 	/* 4.Wait 512 MEMCLKs */
+ 	mct_Wait(300);
++
++	printk(BIOS_DEBUG, "%s: Done\n", __func__);
+ }
+ 
+ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
+@@ -582,6 +594,8 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
+ 	u32 dword;
+ 	u32 dev = pDCTstat->dev_dct;
+ 
++	printk(BIOS_DEBUG, "%s: Start\n", __func__);
++
+ 	if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
+ 		/* 3.Program F2x[1,0]7C[EnDramInit]=1 */
+ 		dword = Get_NB32_DCT(dev, dct, 0x7c);
+@@ -663,4 +677,6 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
+ 		Set_NB32_DCT(dev, dct, 0x7C, dword);
+ 		mct_DCTAccessDone(pDCTstat, dct);
+ 	}
++
++	printk(BIOS_DEBUG, "%s: Done\n", __func__);
+ }
+-- 
+1.7.9.5
+