Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 42 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch
new file mode 100644
index 0000000..ed90d9f
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch
@@ -0,0 +1,42 @@
+From 557954beb8c452750f9ffdd176896b2afb764f27 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Thu, 25 Jun 2015 18:37:45 -0500
+Subject: [PATCH 075/143] northbridge/amd/amdmct/mct_ddr3: Work around strange
+ phy training issue
+
+Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c |   16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+index 403c87c..85b8378 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+@@ -207,6 +207,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
+ 
+ 		pDCTData->WLCriticalGrossDelayPrevPass = cgd;
+ 
++		if (pDCTstat->Speed != pDCTstat->TargetFreq) {
++			/* FIXME
++			 * Using the Pass 1 training values causes major phy training problems on
++			 * all Family 15h processors I tested (Pass 1 values are randomly too high,
++			 * and Pass 2 cannot lock).
++			 * Figure out why this is and fix it, then remove the bypass code below...
++			 */
++			if (pass == FirstPass) {
++				for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
++					pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane];
++					pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane];
++				}
++				return 0;
++			}
++		}
++
+ 		/* Compensate for occasional noise/instability causing sporadic training failure */
+ 		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
+ 			uint8_t faulty_value_detected = 0;
+-- 
+1.7.9.5
+