Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 142 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0065-southbridge-amd-sb700-Do-drive-detection-even-in-AHC.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0065-southbridge-amd-sb700-Do-drive-detection-even-in-AHC.patch
new file mode 100644
index 0000000..84404e5
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0065-southbridge-amd-sb700-Do-drive-detection-even-in-AHC.patch
@@ -0,0 +1,142 @@
+From 9f702a6ac2a4106d3e1f88a27f61052ad4b99925 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sat, 20 Jun 2015 21:31:15 -0500
+Subject: [PATCH 065/143] southbridge/amd/sb700: Do drive detection even in
+ AHCI mode
+
+SeaBIOS AHCI drive detection randomly fails for drives present
+on the secondary channel of each AHCI SATA BAR.  Forcing native
+drive detection in AHCI mode resolves this issue.
+
+Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/southbridge/amd/sb700/sata.c |   99 ++++++++++++++++++++------------------
+ 1 file changed, 53 insertions(+), 46 deletions(-)
+
+diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
+index b09ae73..24f78dd 100644
+--- a/src/southbridge/amd/sb700/sata.c
++++ b/src/southbridge/amd/sb700/sata.c
+@@ -301,65 +301,72 @@ static void sata_init(struct device *dev)
+ 	if (port_count > max_port_count)
+ 		port_count = max_port_count;
+ 
+-	if (!sata_ahci_mode) {
+-		/* RPR7.7 SATA drive detection. */
+-		/* Use BAR5+0x128,BAR0 for Primary Slave */
+-		/* Use BAR5+0x1A8,BAR0 for Primary Slave */
+-		/* Use BAR5+0x228,BAR2 for Secondary Master */
+-		/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
+-		/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */
+-		/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
+-		for (i = 0; i < port_count; i++) {
++	/* RPR7.7 SATA drive detection. */
++	/* Use BAR5+0x128,BAR0 for Primary Slave */
++	/* Use BAR5+0x1A8,BAR0 for Primary Slave */
++	/* Use BAR5+0x228,BAR2 for Secondary Master */
++	/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
++	/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */
++	/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
++	for (i = 0; i < port_count; i++) {
++		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
++		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
++		byte &= 0xF;
++		if (byte == 0x1) {
++			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
++			/* Try to do something about it. */
++			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
++
++			/* Read in Port-N Serial ATA Control Register */
++			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
++
++			/* Set Reset Bit and 1.5g bit */
++			byte |= 0x11;
++			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
++
++			/* Wait 1ms */
++			mdelay(1);
++
++			/* Clear Reset Bit */
++			byte &= ~0x01;
++			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
++
++			/* Wait 1ms */
++			mdelay(1);
++
++			/* Reread status */
+ 			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+ 			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+ 			byte &= 0xF;
+-			if (byte == 0x1) {
+-				/* If the drive status is 0x1 then we see it but we aren't talking to it. */
+-				/* Try to do something about it. */
+-				printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
+-
+-				/* Read in Port-N Serial ATA Control Register */
+-				byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+-
+-				/* Set Reset Bit and 1.5g bit */
+-				byte |= 0x11;
+-				write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+-
+-				/* Wait 1ms */
+-				mdelay(1);
+-
+-				/* Clear Reset Bit */
+-				byte &= ~0x01;
+-				write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+-
+-				/* Wait 1ms */
+-				mdelay(1);
++		}
+ 
+-				/* Reread status */
+-				byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+-				printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+-				byte &= 0xF;
++		if (byte == 0x3) {
++			for (j = 0; j < 10; j++) {
++				if (i < 4)
++					current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2;
++				else
++					current_bar = ide_bar0;
++				if (!sata_drive_detect(i, current_bar))
++					break;
+ 			}
+-
+-			if (byte == 0x3) {
+-				for (j = 0; j < 10; j++) {
+-					if (i < 4)
+-						current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2;
+-					else
+-						current_bar = ide_bar0;
+-					if (!sata_drive_detect(i, current_bar))
+-						break;
+-				}
++			if (sata_ahci_mode)
++				printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n",
++						i,
++						(j == 10) ? "not " : "",
++						(j == 10) ? j : j + 1);
++			else
+ 				printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
+ 						(i / 2) ? "Secondary" : "Primary",
+ 						(i % 2 ) ? "Slave" : "Master",
+ 						(j == 10) ? "not " : "",
+ 						(j == 10) ? j : j + 1);
+-			} else {
++		} else {
++			if (sata_ahci_mode)
++				printk(BIOS_DEBUG, "No AHCI SATA drive on Slot%i\n", i);
++			else
+ 				printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
+ 						(i / 2) ? "Secondary" : "Primary",
+ 						(i % 2 ) ? "Slave" : "Master", i);
+-			}
+ 		}
+ 	}
+ 
+-- 
+1.7.9.5
+