Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 71 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0059-southbridge-amd-sr5650-Add-optional-delay-after-link.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0059-southbridge-amd-sr5650-Add-optional-delay-after-link.patch
new file mode 100644
index 0000000..e24676d
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0059-southbridge-amd-sr5650-Add-optional-delay-after-link.patch
@@ -0,0 +1,71 @@
+From 4e2f99afb90497195aae6491ecf9d931e77dc90d Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 12 Jun 2015 20:08:29 -0500
+Subject: [PATCH 059/143] southbridge/amd/sr5650: Add optional delay after
+ link training
+
+Certain devices (such as the LSI SAS 2008 controller) do not
+respond to PCI probes immediately after link training.  If it
+is known that such a device is likely to be installed allow the
+mainboard to insert an appropriate delay.
+
+Change-Id: Ibcd9426628cacd6f88e6e3fcbc2b3eb7e3a92081
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/southbridge/amd/sr5650/chip.h   |    4 ++++
+ src/southbridge/amd/sr5650/sr5650.c |    3 +++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h
+index 8a68998..d23c614 100644
+--- a/src/southbridge/amd/sr5650/chip.h
++++ b/src/southbridge/amd/sr5650/chip.h
+@@ -2,6 +2,7 @@
+  * This file is part of the coreboot project.
+  *
+  * Copyright (C) 2010 Advanced Micro Devices, Inc.
++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -27,6 +28,9 @@ struct southbridge_amd_sr5650_config
+ 	u8 gpp2_configuration;		/* The configuration of General Purpose Port. */
+ 	u8 gpp3a_configuration;		/* The configuration of General Purpose Port. */
+ 	u16 port_enable;		/* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */
++	uint32_t pcie_settling_time;	/* How long to wait after link training for PCI-e devices to
++					 * initialize before probing PCI-e busses (in microseconds).
++					 */
+ };
+ 
+ #endif /* SR5650_CHIP_H */
+diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
+index 75383de..6db1eb1 100644
+--- a/src/southbridge/amd/sr5650/sr5650.c
++++ b/src/southbridge/amd/sr5650/sr5650.c
+@@ -345,6 +345,7 @@ void sr5650_enable(device_t dev)
+ {
+ 	device_t nb_dev = 0, sb_dev = 0;
+ 	int dev_ind;
++	struct southbridge_amd_sr5650_config *cfg;
+ 
+ 	printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
+ 	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+@@ -352,6 +353,7 @@ void sr5650_enable(device_t dev)
+ 		die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n");
+ 		/* NOT REACHED */
+ 	}
++	cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
+ 
+ 	/* sb_dev (dev 8) is a bridge that links to southbridge. */
+ 	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+@@ -432,6 +434,7 @@ void sr5650_enable(device_t dev)
+ 	/* Lock HWInit Register after the last device was done */
+ 	if (dev_ind == 13) {
+ 		sr56x0_lock_hwinitreg();
++		udelay(cfg->pcie_settling_time);
+ 	}
+ }
+ 
+-- 
+1.7.9.5
+