Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 102 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0055-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0055-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch
new file mode 100644
index 0000000..b41d65e
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0055-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch
@@ -0,0 +1,102 @@
+From 0609ebe6ead8e3024e9ceeba7b46817ff6fc47a8 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Thu, 11 Jun 2015 16:14:15 -0500
+Subject: [PATCH 055/143] src/northbridge/amd/amdmct: Add option to override
+ bad SPD checksum
+
+Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/mainboard/asus/kgpe-d16/cmos.default     |    1 +
+ src/mainboard/asus/kgpe-d16/cmos.layout      |    6 +++++-
+ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |    5 +++--
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c |    8 ++++++++
+ 4 files changed, 17 insertions(+), 3 deletions(-)
+
+diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
+index a52b7fa..73f2a38 100644
+--- a/src/mainboard/asus/kgpe-d16/cmos.default
++++ b/src/mainboard/asus/kgpe-d16/cmos.default
+@@ -8,6 +8,7 @@ nmi = Disable
+ hypertransport_speed_limit = Auto
+ max_mem_clock = DDR3-1600
+ minimum_memory_voltage = 1.5V
++dimm_spd_checksum = Enforce
+ ECC_memory = Enable
+ ECC_redirection = Enable
+ ecc_scrub_rate = 1.28us
+diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout
+index 307bddc..068eaf4 100644
+--- a/src/mainboard/asus/kgpe-d16/cmos.layout
++++ b/src/mainboard/asus/kgpe-d16/cmos.layout
+@@ -47,7 +47,8 @@ entries
+ 466          1       e       1        cpu_cc6_state
+ 467          1       e       1        sata_ahci_mode
+ 468          4       h       0        maximum_p_state_limit
+-473          1       r       0        allow_spd_nvram_cache_restore
++472          2       e       13       dimm_spd_checksum
++474          1       r       0        allow_spd_nvram_cache_restore
+ 477          1       e       1        ieee1394
+ 728        256       h       0        user_data
+ 984         16       h       0        check_sum
+@@ -142,6 +143,9 @@ enumerations
+ 12    1     1.35V
+ 12    2     1.25V
+ 12    3     1.15V
++13    0     Enforce
++13    1     Ignore
++13    2     Override
+ 
+ checksums
+ 
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+index 4d7e5aa..f4859d0 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+@@ -1449,7 +1449,7 @@ restartinit:
+ 			}
+ 		}
+ 		if (NodesWmem == 0) {
+-			printk(BIOS_DEBUG, "No Nodes?!\n");
++			printk(BIOS_ALERT, "Unable to detect valid memory on any nodes.  Halting!\n");
+ 			goto fatalexit;
+ 		}
+ 
+@@ -3884,13 +3884,14 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
+ 					read_spd_bytes(pMCTstat, pDCTstat, i);
+ 					crc_status = crcCheck(pDCTstat, i);
+ 				}
+-				if (crc_status) { /* CRC is OK */
++				if ((crc_status) || (SPDCtrl == 2)) { /* CRC is OK */
+ 					byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE];
+ 					if (byte == JED_DDR3SDRAM) {
+ 						/*Dimm is 'Present'*/
+ 						pDCTstat->DIMMValid |= 1 << i;
+ 					}
+ 				} else {
++					printk(BIOS_WARNING, "Node %d DIMM %d: SPD checksum invalid\n", pDCTstat->Node_ID, i);
+ 					pDCTstat->DIMMSPDCSE = 1 << i;
+ 					if (SPDCtrl == 0) {
+ 						pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum;
+diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+index 5ca8eac..3053d58 100644
+--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
++++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+@@ -150,6 +150,14 @@ static u16 mctGet_NVbits(u8 index)
+ 	case NV_SPDCHK_RESTRT:
+ 		val = 0;	/* Exit current node initialization if any DIMM has SPD checksum error */
+ 		//val = 1;	/* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
++		//val = 2;	/* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */
++
++		if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS)
++			val = nvram & 0x3;
++
++		if (val > 2)
++			val = 2;
++
+ 		break;
+ 	case NV_DQSTrainCTL:
+ 		//val = 0;	/*Skip dqs training */
+-- 
+1.7.9.5
+