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| author | Francis Rowe <info@gluglug.org.uk> | 2016-01-02 17:10:32 (EST) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2016-01-04 15:28:39 (EST) |
| commit | d1f408f3725aa02bc1d76c4c6aadb4697bd073c0 (patch) | |
| tree | 7eed036543ae1f8c57b56825880a722a8efbedf1 /resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch | |
| parent | 91aec7e72005dcda72d19f2d024a02d8c0f86590 (diff) | |
| download | libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.zip libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.tar.gz libreboot-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.tar.bz2 | |
Use different coreboot revisions and patches per board
The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.
At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.
Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.
For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.
Diffstat (limited to 'resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch')
| -rw-r--r-- | resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch new file mode 100644 index 0000000..f11eca2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch @@ -0,0 +1,70 @@ +From 9517e40030e0b2a648df74095d705ed85a6b7f09 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Fri, 5 Jun 2015 21:14:23 -0500 +Subject: [PATCH 046/143] mainboard/asus/kgpe-d16: Enable CC6 + +Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 10 +++++++++- + 3 files changed, 12 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default +index 3e2ea3a..bfd2020 100644 +--- a/src/mainboard/asus/kgpe-d16/cmos.default ++++ b/src/mainboard/asus/kgpe-d16/cmos.default +@@ -14,6 +14,7 @@ ecc_scrub_rate = 1.28us + interleave_chip_selects = Enable + interleave_nodes = Disable + interleave_memory_channels = Enable ++cpu_cc6_state = Enable + ieee1394 = Enable + power_on_after_fail = On + boot_option = Fallback +diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout +index 7944631..630219e 100644 +--- a/src/mainboard/asus/kgpe-d16/cmos.layout ++++ b/src/mainboard/asus/kgpe-d16/cmos.layout +@@ -43,7 +43,8 @@ entries + 458 4 e 11 hypertransport_speed_limit + 462 2 e 12 minimum_memory_voltage + 464 1 e 2 compute_unit_siblings +-465 1 r 0 allow_spd_nvram_cache_restore ++465 1 e 1 cpu_cc6_state ++466 1 r 0 allow_spd_nvram_cache_restore + 477 1 e 1 ieee1394 + 728 256 h 0 user_data + 984 16 h 0 check_sum +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +index fa1873a..83c7b02 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +@@ -625,7 +625,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste + write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x124, data->f1x124); + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x10c, data->f2x10c); + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x114, data->f2x114); +- write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); ++ if (is_fam15h()) ++ /* Do not set LockDramCfg or CC6SaveEn at this time */ ++ write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118 & ~(0x3 << 18)); ++ else ++ write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c); + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0); + write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44); +@@ -1017,6 +1021,10 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste + + /* ECC scrub rate control */ + pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x58, data->f3x58); ++ ++ if (is_fam15h()) ++ /* Set LockDramCfg and CC6SaveEn */ ++ write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); + } + } + } +-- +1.7.9.5 + |