Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 59 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0038-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0038-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch
new file mode 100644
index 0000000..5300db1
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0038-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch
@@ -0,0 +1,59 @@
+From ed27521eaee0dd334c658fb68d0c8ebaa6a126cc Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Mon, 1 Jun 2015 23:58:59 -0500
+Subject: [PATCH 038/143] cpu/amd/car: Add romstage BSP stack overrun
+ detection
+
+Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/car/cache_as_ram.inc    |    6 +++++-
+ src/cpu/amd/car/post_cache_as_ram.c |    8 ++++++++
+ 2 files changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
+index 6542906..4ccde3f 100644
+--- a/src/cpu/amd/car/cache_as_ram.inc
++++ b/src/cpu/amd/car/cache_as_ram.inc
+@@ -24,7 +24,7 @@
+ #include <cpu/amd/mtrr.h>
+ 
+ #define CacheSize		CONFIG_DCACHE_RAM_SIZE
+-#define CacheBase		(0xd0000 - CacheSize)
++#define CacheBase		CONFIG_DCACHE_RAM_BASE
+ #define CacheSizeBSPStack	CONFIG_DCACHE_BSP_STACK_SIZE
+ #define CacheSizeBSPSlush	CONFIG_DCACHE_BSP_STACK_SLUSH
+ 
+@@ -473,6 +473,10 @@ fam10_end_part1:
+ 	movl	$(CacheBase + CacheSize), %eax
+ 	movl	%eax, %esp
+ 
++	/* Poison the lower stack boundary */
++	movl	$((CacheBase + CacheSize) - CacheSizeBSPStack), %eax
++	movl	$0xdeadbeef, (%eax)
++
+ 	post_code(0xa3)
+ 
+ 	jmp	CAR_FAM10_ap_out
+diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
+index 257b41a..787bedd 100644
+--- a/src/cpu/amd/car/post_cache_as_ram.c
++++ b/src/cpu/amd/car/post_cache_as_ram.c
+@@ -110,6 +110,14 @@ void post_cache_as_ram(void)
+ 	void *resume_backup_memory = NULL;
+ 	uint32_t family = amd_fam1x_cpu_family();
+ 
++	/* Verify that the BSP didn't overrun the lower stack
++	 * boundary during romstage execution
++	 */
++	volatile uint32_t *lower_stack_boundary;
++	lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_STACK_SIZE);
++	if ((*lower_stack_boundary) != 0xdeadbeef)
++		printk(BIOS_WARNING, "BSP overran lower stack boundary.  Undefined behaviour may result!\n");
++
+ 	struct romstage_handoff *handoff;
+ 	handoff = romstage_handoff_find_or_add();
+ 	if (handoff != NULL)
+-- 
+1.7.9.5
+