Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 108 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0016-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0016-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch
new file mode 100644
index 0000000..bd6a820
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0016-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch
@@ -0,0 +1,108 @@
+From 51e23836f586c79d63ca402bad738bd7a4149572 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sat, 5 Sep 2015 18:46:54 -0500
+Subject: [PATCH 016/143] cpu/amd/model_10xxx: Clean up debugging statements
+
+Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/model_10xxx/fidvid.c |   42 ++++++++++++++++++--------------------
+ 1 file changed, 20 insertions(+), 22 deletions(-)
+
+diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
+index 36bdf36..5b1c581 100644
+--- a/src/cpu/amd/model_10xxx/fidvid.c
++++ b/src/cpu/amd/model_10xxx/fidvid.c
+@@ -460,35 +460,35 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
+ 
+ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
+ 	/* check PVI/SVI */
+-	u32 dword = pci_read_config32(dev, 0xA0);
++	u32 dword = pci_read_config32(dev, 0xa0);
+ 
+-        /* BKDG r31116 2010-04-22  2.4.1.7 step b F3xA0[VSSlamVidMod] */
+-        /* PllLockTime and PsiVidEn set in ruleset in defaults.h */
++	/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xA0[VSSlamVidMod] */
++	/* PllLockTime and PsiVidEn set in ruleset in defaults.h */
+ 	if (dword & PVI_MODE) {	/* PVI */
+ 		/* set slamVidMode to 0 for PVI */
+ 		dword &= VID_SLAM_OFF ;
+ 	} else {	/* SVI */
+ 		/* set slamVidMode to 1 for SVI */
+ 		dword |= VID_SLAM_ON;
+-        }
++	}
+         /* set the rest of A0 since we're at it... */
+ 
+-        if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
+-	     dword |= NB_PSTATE_FORCE_ON;
++	if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
++		dword |= NB_PSTATE_FORCE_ON;
+ 	} // else should we clear it ?
+ 
+ 
+         if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
+-	  dword |= BP_INS_TRI_EN_ON ;
++		dword |= BP_INS_TRI_EN_ON ;
+ 	}
+ 
+ 	   /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
+         #if CONFIG_SVI_HIGH_FREQ
+-	   if (cpuRev & AMD_FAM10_C3) {
+-	     dword |= SVI_HIGH_FREQ_ON;
+-           }
+-        #endif
+-	pci_write_config32(dev, 0xA0, dword);
++	if (cpuRev & AMD_FAM10_C3) {
++		dword |= SVI_HIGH_FREQ_ON;
++	}
++	#endif
++	pci_write_config32(dev, 0xa0, dword);
+ }
+ 
+ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
+@@ -581,7 +581,7 @@ static void prep_fid_change(void)
+ 	nodes = get_nodes();
+ 
+ 	for (i = 0; i < nodes; i++) {
+-		printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
++		printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i);
+ 		dev = NODE_PCI(i, 3);
+                 u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
+ 	        u8 procPkg =  mctGetProcessorPackageType();
+@@ -591,25 +591,23 @@ static void prep_fid_change(void)
+ 		/* Figure out the value for VsSlamTime and program it */
+ 		recalculateVsSlamTimeSettingOnCorePre(dev);
+ 
+-                config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
++		config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
+ 
+                 config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
+ 		config_nb_syn_ptr_adj(dev,cpuRev);
+ 
+-                config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
++		config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
+ 
+ 		dword = pci_read_config32(dev, 0x80);
+-		printk(BIOS_DEBUG, "  F3x80: %08x \n", dword);
++		printk(BIOS_DEBUG, "  F3x80: %08x\n", dword);
+ 		dword = pci_read_config32(dev, 0x84);
+-		printk(BIOS_DEBUG, "  F3x84: %08x \n", dword);
++		printk(BIOS_DEBUG, "  F3x84: %08x\n", dword);
+ 		dword = pci_read_config32(dev, 0xD4);
+-		printk(BIOS_DEBUG, "  F3xD4: %08x \n", dword);
++		printk(BIOS_DEBUG, "  F3xD4: %08x\n", dword);
+ 		dword = pci_read_config32(dev, 0xD8);
+-		printk(BIOS_DEBUG, "  F3xD8: %08x \n", dword);
++		printk(BIOS_DEBUG, "  F3xD8: %08x\n", dword);
+ 		dword = pci_read_config32(dev, 0xDC);
+-		printk(BIOS_DEBUG, "  F3xDC: %08x \n", dword);
+-
+-
++		printk(BIOS_DEBUG, "  F3xDC: %08x\n", dword);
+ 	}
+ }
+ 
+-- 
+1.7.9.5
+