Use different coreboot revisions and patches per board

The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.

At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.

Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.

For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.

1 files changed, 95 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0011-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0011-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch
new file mode 100644
index 0000000..df89fbc
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0011-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch
@@ -0,0 +1,95 @@
+From 55eeaf44d331c7f42a7b03f22364d6a5a6febb47 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Tue, 8 Sep 2015 16:08:45 -0500
+Subject: [PATCH 011/143] northbridge/amd/amdmct/mct_ddr3: Fix curly brace
+ style violations
+
+Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c |   37 +++++++------------------
+ 1 file changed, 10 insertions(+), 27 deletions(-)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+index 67d705c..397fd77 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+@@ -818,28 +818,19 @@ void setWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm, u8 targetAddr)
+ 
+ 		tempB = 0;
+ 		offsetAddr = (u8)(3 * dimm);
+-		if (ByteLane < 2)
+-		{
++		if (ByteLane < 2) {
+ 			tempB = (u8)(16 * ByteLane);
+ 			addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01;
+-		}
+-		else if (ByteLane <4)
+-		{
++		} else if (ByteLane <4) {
+ 			tempB = (u8)(16 * ByteLane);
+ 			addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01 + 1;
+-		}
+-		else if (ByteLane <6)
+-		{
++		} else if (ByteLane <6) {
+ 			tempB = (u8)(16 * ByteLane);
+ 			addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_45;
+-		}
+-		else if (ByteLane <8)
+-		{
++		} else if (ByteLane <8) {
+ 			tempB = (u8)(16 * ByteLane);
+ 			addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_45 + 1;
+-		}
+-		else
+-		{
++		} else {
+ 			tempB = 0;
+ 			addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01 + 2;
+ 		}
+@@ -883,19 +874,14 @@ void getWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm)
+ 	u32 addr, fine, gross;
+ 	tempB = 0;
+ 	index = (u8)(MAX_BYTE_LANES*dimm);
+-	if (ByteLane < 4)
+-	{
++	if (ByteLane < 4) {
+ 		tempB = (u8)(8 * ByteLane);
+ 		addr = DRAM_CONT_ADD_PHASE_REC_CTRL_LOW;
+-	}
+-	else if (ByteLane < 8)
+-	{
++	} else if (ByteLane < 8) {
+ 		tempB1 = (u8)(ByteLane - 4);
+ 		tempB = (u8)(8 * tempB1);
+ 		addr = DRAM_CONT_ADD_PHASE_REC_CTRL_HIGH;
+-	}
+-	else
+-	{
++	} else {
+ 		tempB = 0;
+ 		addr = DRAM_CONT_ADD_ECC_PHASE_REC_CTRL;
+ 	}
+@@ -911,16 +897,13 @@ void getWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm)
+ 	/* Adjust seed gross delay overflow (greater than 3):
+ 	 * - Adjust the trained gross delay to the original seed gross delay.
+ 	 */
+-	if(pDCTData->WLGrossDelay[index+ByteLane] >= 3)
+-	{
++	if (pDCTData->WLGrossDelay[index+ByteLane] >= 3) {
+ 		gross += pDCTData->WLGrossDelay[index+ByteLane];
+ 		if(pDCTData->WLGrossDelay[index+ByteLane] & 1)
+ 			gross -= 1;
+ 		else
+ 			gross -= 2;
+-	}
+-	else if((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3))
+-	{
++	} else if ((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) {
+ 		/* If seed gross delay is 0 but PRE result gross delay is 3, it is negative.
+ 		 * We will then round the negative number to 0.
+ 		 */
+-- 
+1.7.9.5
+