Coreboot, vboot and depthcharge updates to Coreboot 4.3 for CrOS devices

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

4 files changed, 217 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0001-util-xcompile-Detect-toolchains-with-bare-arm-prefix.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0001-util-xcompile-Detect-toolchains-with-bare-arm-prefix.patch
new file mode 100644
index 0000000..1e71ecf
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0001-util-xcompile-Detect-toolchains-with-bare-arm-prefix.patch
@@ -0,0 +1,26 @@
+From 1a378294fa9afdc4d6d3b0e580ba78d33a62d044 Mon Sep 17 00:00:00 2001
+From: Paul Kocialkowski <contact@paulk.fr>
+Date: Tue, 19 Apr 2016 12:02:14 +0200
+Subject: [PATCH 1/4] util: xcompile: Detect toolchains with bare arm prefix
+
+Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
+---
+ util/xcompile/xcompile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
+index b0199eb..1765183 100755
+--- a/util/xcompile/xcompile
++++ b/util/xcompile/xcompile
+@@ -290,7 +290,7 @@ SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86 power8"
+ arch_config_arm() {
+ 	TARCH="arm"
+ 	TBFDARCHS="littlearm"
+-	TCLIST="armv7-a armv7a"
++	TCLIST="armv7-a armv7a arm"
+ 	TWIDTH="32"
+ 	TSUPP="arm armv4 armv7 armv7_m"
+ 	TABI="eabi"
+-- 
+2.8.0
+
diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0002-libpayload-use-32bit-access-when-accessing-4byte-wid.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0002-libpayload-use-32bit-access-when-accessing-4byte-wid.patch
new file mode 100644
index 0000000..b38cf56
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0002-libpayload-use-32bit-access-when-accessing-4byte-wid.patch
@@ -0,0 +1,48 @@
+From be5ba870e006e8e7fe0f1ace2952b540c3aec3d9 Mon Sep 17 00:00:00 2001
+From: Patrick Georgi <pgeorgi@chromium.org>
+Date: Mon, 8 Feb 2016 21:17:12 +0100
+Subject: [PATCH 2/4] libpayload: use 32bit access when accessing 4byte wide
+ uart registers
+
+This fixes serial on rk3288.
+
+Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f
+Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
+Reviewed-on: https://review.coreboot.org/13636
+Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
+Tested-by: build bot (Jenkins)
+---
+ payloads/libpayload/drivers/serial/8250.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c
+index 7fe9920..0386f23 100644
+--- a/payloads/libpayload/drivers/serial/8250.c
++++ b/payloads/libpayload/drivers/serial/8250.c
+@@ -46,7 +46,10 @@ static uint8_t serial_read_reg(int offset)
+ 		return inb(IOBASE + offset);
+ 	else
+ #endif
+-		return readb(MEMBASE + offset);
++		if (lib_sysinfo.serial->regwidth == 4)
++			return readl(MEMBASE + offset) & 0xff;
++		else
++			return readb(MEMBASE + offset);
+ }
+ 
+ static void serial_write_reg(uint8_t val, int offset)
+@@ -58,7 +61,10 @@ static void serial_write_reg(uint8_t val, int offset)
+ 		outb(val, IOBASE + offset);
+ 	else
+ #endif
+-		writeb(val, MEMBASE + offset);
++		if (lib_sysinfo.serial->regwidth == 4)
++			writel(val & 0xff, MEMBASE + offset);
++		else
++			writeb(val, MEMBASE + offset);
+ }
+ 
+ #if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED)
+-- 
+2.8.0
+
diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch
new file mode 100644
index 0000000..8a2d253
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch
@@ -0,0 +1,31 @@
+From 02bc24a863a9b580d5eb32b780296ff8a5c3d2c1 Mon Sep 17 00:00:00 2001
+From: Patrick Georgi <pgeorgi@chromium.org>
+Date: Mon, 8 Feb 2016 20:28:32 +0100
+Subject: [PATCH 3/4] rockchip/rk3288: UART uses 32bit wide registers
+
+Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b
+Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
+Reviewed-on: https://review.coreboot.org/13635
+Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
+Tested-by: build bot (Jenkins)
+Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
+---
+ src/soc/rockchip/rk3288/uart.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c
+index 9847734..8576dc1 100644
+--- a/src/soc/rockchip/rk3288/uart.c
++++ b/src/soc/rockchip/rk3288/uart.c
+@@ -155,7 +155,7 @@ void uart_fill_lb(void *data)
+ 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ 	serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+ 	serial.baud = default_baudrate();
+-	serial.regwidth = 1;
++	serial.regwidth = 4;
+ 	lb_add_serial(&serial, data);
+ 
+ 	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+-- 
+2.8.0
+
diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0004-chromeos-Allow-disabling-vboot-firmware-verification.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0004-chromeos-Allow-disabling-vboot-firmware-verification.patch
new file mode 100644
index 0000000..1139490
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0004-chromeos-Allow-disabling-vboot-firmware-verification.patch
@@ -0,0 +1,112 @@
+From 1122f7a00ad7b9cab11a548ed2ba24536bfc194e Mon Sep 17 00:00:00 2001
+From: Paul Kocialkowski <contact@paulk.fr>
+Date: Sun, 9 Aug 2015 10:23:38 +0200
+Subject: [PATCH 4/4] chromeos: Allow disabling vboot firmware verification
+ when ChromeOS is enabled
+
+Some ChromeOS bindings might be wanted without using vboot verification, for
+instance to boot up depthcharge from the version of Coreboot installed in the
+write-protected part of the SPI flash (without jumping to a RW firmware).
+
+Vboot firmware verification is still selected by default when ChromeOS is
+enabled, but this allows more flexibility since vboot firmware verification is
+no longer a hard requirement for ChromeOS (that this particular use case still
+allows booting ChromeOS).
+
+In the future, it would make sense to have all the separate components that
+CONFIG_CHROMEOS enables have their own config options, so that they can be
+enabled separately.
+
+Change-Id: Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb
+Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
+---
+ src/lib/bootmode.c                            | 2 ++
+ src/soc/rockchip/rk3288/Kconfig               | 2 +-
+ src/vendorcode/google/chromeos/Kconfig        | 4 +---
+ src/vendorcode/google/chromeos/vboot2/Kconfig | 4 ++++
+ 4 files changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
+index 15f7a5a..e4be29e 100644
+--- a/src/lib/bootmode.c
++++ b/src/lib/bootmode.c
+@@ -76,8 +76,10 @@ void gfx_set_init_done(int done)
+ int display_init_required(void)
+ {
+ 	/* For Chrome OS always honor vboot_skip_display_init(). */
++#if CONFIG_VBOOT_VERIFY_FIRMWARE
+ 	if (IS_ENABLED(CONFIG_CHROMEOS))
+ 		return !vboot_skip_display_init();
++#endif
+ 
+ 	/* By default always initialize display. */
+ 	return 1;
+diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
+index 65e6dc3..7947514 100644
+--- a/src/soc/rockchip/rk3288/Kconfig
++++ b/src/soc/rockchip/rk3288/Kconfig
+@@ -31,7 +31,7 @@ config SOC_ROCKCHIP_RK3288
+ 
+ if SOC_ROCKCHIP_RK3288
+ 
+-config CHROMEOS
++config VBOOT_VERIFY_FIRMWARE
+ 	select VBOOT_STARTS_IN_BOOTBLOCK
+ 	select SEPARATE_VERSTAGE
+ 	select RETURN_FROM_VERSTAGE
+diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
+index d2a42a1..4068419 100644
+--- a/src/vendorcode/google/chromeos/Kconfig
++++ b/src/vendorcode/google/chromeos/Kconfig
+@@ -27,7 +27,6 @@ config CHROMEOS
+ 	select BOOTMODE_STRAPS
+ 	select ELOG if SPI_FLASH
+ 	select COLLECT_TIMESTAMPS
+-	select VBOOT_VERIFY_FIRMWARE
+ 	select MULTIPLE_CBFS_INSTANCES
+ 	help
+ 	  Enable ChromeOS specific features like the GPIO sub table in
+@@ -96,7 +95,6 @@ config CHROMEOS_RAMOOPS_RAM_SIZE
+ config EC_SOFTWARE_SYNC
+ 	bool "Enable EC software sync"
+ 	default n
+-	depends on VBOOT_VERIFY_FIRMWARE
+ 	help
+ 	  EC software sync is a mechanism where the AP helps the EC verify its
+ 	  firmware similar to how vboot verifies the main system firmware. This
+@@ -120,12 +118,12 @@ config VBOOT_OPROM_MATTERS
+ config VIRTUAL_DEV_SWITCH
+ 	bool "Virtual developer switch support"
+ 	default n
+-	depends on VBOOT_VERIFY_FIRMWARE
+ 	help
+ 	  Whether this platform has a virtual developer switch.
+ 
+ config VBOOT_VERIFY_FIRMWARE
+ 	bool "Verify firmware with vboot."
++	default y if CHROMEOS
+ 	default n
+ 	depends on HAVE_HARD_RESET
+ 	help
+diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig
+index 7580d8d..141b636 100644
+--- a/src/vendorcode/google/chromeos/vboot2/Kconfig
++++ b/src/vendorcode/google/chromeos/vboot2/Kconfig
+@@ -12,6 +12,8 @@
+ ## GNU General Public License for more details.
+ ##
+ 
++if VBOOT_VERIFY_FIRMWARE
++
+ config VBOOT_STARTS_IN_BOOTBLOCK
+ 	bool "Vboot starts verifying in bootblock"
+ 	default n
+@@ -78,3 +80,5 @@ config VBOOT_DYNAMIC_WORK_BUFFER
+ 	  ram to allocate the vboot work buffer. That means vboot verification
+ 	  is after memory init and requires main memory to back the work
+ 	  buffer.
++
++endif # VBOOT_VERIFY_FIRMWARE
+-- 
+2.8.0
+