diff options
| author | Francis Rowe <info@gluglug.org.uk> | 2015-06-15 15:15:36 (EDT) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-06-15 23:36:26 (EDT) |
| commit | bd95009839337576c1d7ac6d022228c4ec4248a5 (patch) | |
| tree | 29622510346a315c5cb0fd766ac883147f3b4b15 /resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch | |
| parent | 9f8eced929a99b2ad7b10d1b8d237779afdd98d5 (diff) | |
| download | libreboot-bd95009839337576c1d7ac6d022228c4ec4248a5.zip libreboot-bd95009839337576c1d7ac6d022228c4ec4248a5.tar.gz libreboot-bd95009839337576c1d7ac6d022228c4ec4248a5.tar.bz2 | |
Update coreboot-libre
Rebase all patches. Remove the ones that are no longer needed.
More CPU microcode updates were moved to coreboot's 3rdparty
repository, so there are less blobs for libreboot to delete
now (because the 3rdparty repository is not checked out in
libreboot).
Correct HDA verbs used for T400 (also R400, T500) (patch is in
coreboot, merged).
Diffstat (limited to 'resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch')
| -rw-r--r-- | resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch b/resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch new file mode 100644 index 0000000..d41363f --- /dev/null +++ b/resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch @@ -0,0 +1,49 @@ +From 3b67763d6029ce954cea0dbc02ff6814b7c02478 Mon Sep 17 00:00:00 2001 +From: Steve Shenton <sgsit@libreboot.org> +Date: Fri, 12 Dec 2014 12:42:01 +0000 +Subject: [PATCH 11/17] northbridge/gm45/raminit.c: enable GS45 + high-performance mode + +The datasheets for GS45 describe a high- and low-performance mode +for different CPUs. Coreboot currently disables GS45 altogether, +but forcing coreboot to treat high-performance GS45 as GM45 makes +the X200S and X200 Tablet boot if it has the right CPU type. + +Hardcode-enable GS45 high-performance mode in coreboot, passing it +off as GM45. This is known to work with all CPUs except the SU +(low performance) models. + +Change-Id: I57032bb6e1ebdaf4e2aa09548e73d253afb9b078 +Signed-off-by: Steve Shenton <sgsit@libreboot.org> +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/northbridge/intel/gm45/raminit.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index 9c4fecd..9f5aa06 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -108,8 +108,8 @@ void get_gmch_info(sysinfo_t *sysinfo) + printk(BIOS_SPEW, "GMCH: GS40\n"); + break; + case GMCH_GS45: +- printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); +- sysinfo->gs45_low_power_mode = 1; ++ printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n"); ++ sysinfo->gs45_low_power_mode = 0; + break; + case GMCH_PM45: + printk(BIOS_SPEW, "GMCH: PM45\n"); +@@ -1692,7 +1692,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) + { + const dimminfo_t *const dimms = sysinfo->dimms; + const timings_t *const timings = &sysinfo->selected_timings; +- const int sff = sysinfo->gfx_type == GMCH_GS45; ++ const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1); + + int ch; + u8 reg8; +-- +1.9.1 + |