diff options
| -rw-r--r-- | resources/libreboot/patch/0014-northbridge-intel-gm45-Automatically-enable-second-L.patch | 129 | ||||
| -rwxr-xr-x | resources/scripts/helpers/download/coreboot | 3 |
2 files changed, 132 insertions, 0 deletions
diff --git a/resources/libreboot/patch/0014-northbridge-intel-gm45-Automatically-enable-second-L.patch b/resources/libreboot/patch/0014-northbridge-intel-gm45-Automatically-enable-second-L.patch new file mode 100644 index 0000000..6dd05d9 --- /dev/null +++ b/resources/libreboot/patch/0014-northbridge-intel-gm45-Automatically-enable-second-L.patch @@ -0,0 +1,129 @@ +From 11cbc9cc777afcf7553e698dd326d4292c3312d4 Mon Sep 17 00:00:00 2001 +From: "P. J. McDermott" <pj@pehjota.net> +Date: Sun, 20 Sep 2015 08:50:38 -0400 +Subject: [PATCH] northbridge/intel/gm45: Automatically enable second LVDS + channel + +This is not a static board-specific option, so it should be detected +instead of specified in devicetree.cb. + +Signed-off-by: P. J. McDermott <pj@pehjota.net> +--- + src/mainboard/lenovo/t400/devicetree.cb | 1 - + src/mainboard/lenovo/x200/devicetree.cb | 1 - + src/northbridge/intel/gm45/gma.c | 26 +++++++++++++++++++------- + 3 files changed, 19 insertions(+), 9 deletions(-) + +diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb +index c3fffe8..cf6157c 100644 +--- a/src/mainboard/lenovo/t400/devicetree.cb ++++ b/src/mainboard/lenovo/t400/devicetree.cb +@@ -4,7 +4,6 @@ chip northbridge/intel/gm45 + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + register "gfx.use_spread_spectrum_clock" = "1" +- register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" + +diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb +index cb4a021..007141c 100644 +--- a/src/mainboard/lenovo/x200/devicetree.cb ++++ b/src/mainboard/lenovo/x200/devicetree.cb +@@ -4,7 +4,6 @@ chip northbridge/intel/gm45 + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + register "gfx.use_spread_spectrum_clock" = "1" +- register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index f29b9b1..a695800 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -112,6 +112,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + u32 hactive, vactive, right_border, bottom_border; + int hpolarity, vpolarity; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ int lvds_dual_channel; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; +@@ -172,7 +173,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + hfront_porch = edid.hso; + vfront_porch = edid.vso; + +- target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock ++ /* ++ * Detect whether second LVDS channel should be enabled. ++ * This currently assumes that any display larger than 1280x800 pixels ++ * needs both channels, which seems approximately true. ++ */ ++ if (hactive * vactive > 1280 * 800) { ++ lvds_dual_channel = 1; ++ } else { ++ lvds_dual_channel = 0; ++ } ++ ++ target_frequency = lvds_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + vga_sr_write(1, 1); +@@ -257,7 +269,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, +- info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); ++ lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", +@@ -274,7 +286,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + + write32(mmio + LVDS, + (hpolarity << 20) | (vpolarity << 21) +- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL ++ | (lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + mdelay(1); +@@ -285,7 +297,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 ++ | (lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) +@@ -293,7 +305,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 ++ | (lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) +@@ -304,7 +316,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + + write32(mmio + LVDS, + (hpolarity << 20) | (vpolarity << 21) +- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL ++ | (lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + +@@ -395,7 +407,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + write32(mmio + LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) +- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL ++ | (lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + +-- +2.1.4 + diff --git a/resources/scripts/helpers/download/coreboot b/resources/scripts/helpers/download/coreboot index 21d86de..295c7f1 100755 --- a/resources/scripts/helpers/download/coreboot +++ b/resources/scripts/helpers/download/coreboot @@ -135,6 +135,9 @@ printf "ec/lenovo/h8: re-factor handling of power_management_beeps\n" # git fetch http://review.coreboot.org/coreboot refs/changes/31/10531/8 && git cherry-pick FETCH_HEAD git am "../resources/libreboot/patch/0013-ec-lenovo-h8-re-factor-handling-of-power_management_.patch" +printf "northbridge/intel/gm45: Automatically enable second LVDS channel\n" +git am "../resources/libreboot/patch/0014-northbridge-intel-gm45-Automatically-enable-second-L.patch" + # Run coreboot-libre deblob scripts # ------------------------------------------------------------------------------ |