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From fa09be02971b05b8031ebc372ab778613d25da7f Mon Sep 17 00:00:00 2001
From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
Date: Tue, 11 Aug 2015 17:53:45 -0500
Subject: [PATCH 117/146] mainboard/asus/kgpe-d16: Add several nvram
configuration options
---
src/mainboard/asus/kgpe-d16/acpi_tables.c | 37 +++++++++++++++++++++++++++++
src/mainboard/asus/kgpe-d16/cmos.default | 3 ++-
src/mainboard/asus/kgpe-d16/cmos.layout | 7 +++---
src/mainboard/asus/kgpe-d16/devicetree.cb | 1 +
src/mainboard/asus/kgpe-d16/romstage.c | 2 ++
5 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c
index 4e98dfe..3f8650b 100644
--- a/src/mainboard/asus/kgpe-d16/acpi_tables.c
+++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c
@@ -73,3 +73,40 @@ unsigned long acpi_fill_madt(unsigned long current)
return current;
}
+
+unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
+{
+ uint8_t *p;
+
+ uint32_t apicid_sp5100;
+ uint32_t apicid_sr5650;
+
+ apicid_sp5100 = 0x20;
+ apicid_sr5650 = apicid_sp5100 + 1;
+
+ /* Describe NB IOAPIC */
+ p = (uint8_t *)current;
+ p[0] = 0x48; /* Entry type */
+ p[1] = 0; /* Device */
+ p[2] = 0; /* Bus */
+ p[3] = 0x0; /* Data */
+ p[4] = apicid_sr5650; /* IOAPIC ID */
+ p[5] = 0x1; /* Device 0 Function 1 */
+ p[6] = 0x0; /* Northbridge bus */
+ p[7] = 0x1; /* Variety */
+ current += 8;
+
+ /* Describe SB IOAPIC */
+ p = (uint8_t *)current;
+ p[0] = 0x48; /* Entry type */
+ p[1] = 0; /* Device */
+ p[2] = 0; /* Bus */
+ p[3] = 0xd7; /* Data */
+ p[4] = apicid_sp5100; /* IOAPIC ID */
+ p[5] = 0x14 << 3; /* Device 0x14 Function 0 */
+ p[6] = 0x0; /* Southbridge bus */
+ p[7] = 0x1; /* Variety */
+ current += 8;
+
+ return current;
+}
\ No newline at end of file
diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
index 0a898bd..83c1fe8 100644
--- a/src/mainboard/asus/kgpe-d16/cmos.default
+++ b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -3,7 +3,7 @@ debug_level = Spew
multi_core = Enable
slow_cpu = off
compute_unit_siblings = Enable
-iommu = Disable
+iommu = Enable
nmi = Disable
hypertransport_speed_limit = Auto
max_mem_clock = DDR3-1600
@@ -23,6 +23,7 @@ maximum_p_state_limit = 0xf
probe_filter = Auto
l3_cache_partitioning = Disable
ieee1394 = Enable
+gart = Disable
experimental_memory_speed_boost = Disable
power_on_after_fail = On
boot_option = Fallback
diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout
index 010d4db..310b7b1 100644
--- a/src/mainboard/asus/kgpe-d16/cmos.layout
+++ b/src/mainboard/asus/kgpe-d16/cmos.layout
@@ -51,9 +51,10 @@ entries
473 2 e 13 dimm_spd_checksum
475 1 e 14 probe_filter
476 1 e 1 l3_cache_partitioning
-477 1 e 1 experimental_memory_speed_boost
-478 1 r 0 allow_spd_nvram_cache_restore
-479 1 e 1 ieee1394
+477 1 e 1 ieee1394
+478 1 e 1 gart
+479 1 e 1 experimental_memory_speed_boost
+480 1 r 0 allow_spd_nvram_cache_restore
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
index 05b975b..8879c0e 100644
--- a/src/mainboard/asus/kgpe-d16/devicetree.cb
+++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
chip southbridge/amd/sr5650 # Primary southbridge
device pci 0.0 on end # HT Root Complex 0x9600
device pci 0.1 on end # CLKCONFIG
+ device pci 0.2 on end # IOMMU
device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0)
# Slot # PCI E 1 / PCI E 2
end
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 13fb485..c91fb1d 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -459,6 +459,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
die("After soft_reset_x - shouldn't see this message!!!\n");
}
+ sr5650_htinit_dect_and_enable_isochronous_link();
+
/* Set default DDR memory voltage
* This will be overridden later during RAM initialization
*/
--
1.7.9.5
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