From 115b09a63d1e5eb07d8c12a6c5369c1577b41f42 Mon Sep 17 00:00:00 2001 From: Steve Shenton Date: Fri, 7 Aug 2015 08:22:27 +0100 Subject: [PATCH 6/9] northbridge/gm45/raminit.c: enable GS45 high-performance mode The datasheets for GS45 describe a high- and low-performance mode for different CPUs. Coreboot currently disables GS45 altogether, but forcing coreboot to treat high-performance GS45 as GM45 makes the X200S and X200 Tablet boot if it has the right CPU type. Hardcode-enable GS45 high-performance mode in coreboot, passing it off as GM45. This is known to work with all CPUs except the SU (low performance) models. The low-performance models are unsupported anyway, requiring extensive work on the raminit. For now, this patch increases compatibility to a whole new chipset (GS45), depending on the CPU. Change-Id: I2719385e93c37d254ce38e0f5f486262160234e1 Signed-off-by: Steve Shenton Signed-off-by: Francis Rowe --- src/northbridge/intel/gm45/raminit.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 9c4fecd..1614b7c 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -108,8 +108,7 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n"); break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1692,7 +1691,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; + const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1); int ch; u8 reg8; -- 1.9.1