How to programme an SPI flash chip with the BeagleBone Black

This document exists as a guide for reading from or writing to an SPI flash chip with the BeagleBone Black, using the flashrom software. BeagleBone Black rev. C was used when creating this guide, but earlier revisions may also work.

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Hardware requirements

Shopping list (pictures of this hardware is shown later):

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Setting up the 3.3V DC PSU

ATX PSU pinouts are on wikipedia

On 20-pin ATX PSUs, you can use pin 1 or 2 (orange) for 3.3V, and any of the ground/earth sources (black cables). Short PS_ON# / Power on (green) to a ground (black. there is one right next to it) using a wire/paperclip/jumper then power on the PSU.

On newer 24-pin ATX PSUs, there is an additional 3.3V (orange) on pin 12.

You only need one 3.3V supply and one ground for the flash chip, after grounding PS_ON# to ground. Multiple 3.3V supplies means that you could theoretically power multiple flash chips at once with the same PSU.

The male end of a 0.1" or 2.54mm header cable is not thick enough to remain permanently connected to the ATX PSU on its own. When connecting header cables to the connector on the ATX PSU, use a female end attached to a thicker piece of wire (you could use a paper clip), or wedge the male end of the jumper cable into the sides of the hole in the connector, instead of going through the centre.

Here is an example set up:

Accessing the operating system on the BBB

The operating system on your BBB will probably have an SSH daemon running where the root account has no password. Use SSH to access the operating system and set a root password. By default, the OS on your BBB will most likely use DHCP, so it should already have an IP address.

You will also be using the OS on your BBB for programming an SPI flash chip.

Alternatives to SSH (in case SSH fails)

You can also use a serial FTDI debug board with GNU Screen, to access the serial console.
# screen /dev/ttyUSB0 115200
Here are some example photos:

You can also connect the USB cable from the BBB to another computer and a new network interface will appear, with its own IP address. This is directly accessible from SSH, or screen:
# screen /dev/ttyACM0 115200

You can also access the uboot console, using the serial method instead of SSH.

Setting up spidev on the BBB

Log on as root on the BBB, using either SSH or a serial console as defined in #bbb_access. Make sure that you have internet access on your BBB.

Follow the instructions at http://elinux.org/BeagleBone_Black_Enable_SPIDEV#SPI0 up to (and excluding) the point where it tells you to modify uEnv.txt

You need to update the software on the BBB first. If you have an element14 brand BBB (sold by Premier Farnell plc. stores like Farnell element14, Newark element14, and Embest), you may need to work around a bug in the LED aging init script before you can update your software. If you don't have a file named /etc/init.d/led_aging.sh, you can skip this step and update your software as described below. Otherwise, replace the contents of this file with: 

#!/bin/sh -e
### BEGIN INIT INFO
# Provides:          led_aging.sh
# Required-Start:    $local_fs
# Required-Stop:     $local_fs
# Default-Start:     2 3 4 5
# Default-Stop:      0 1 6
# Short-Description: Start LED aging
# Description:       Starts LED aging (whatever that is)
### END INIT INFO

x=$(/bin/ps -ef | /bin/grep "[l]ed_acc")
if [ ! -n "$x" -a -x /usr/bin/led_acc ]; then
    /usr/bin/led_acc &
fi

Run apt-get update and apt-get upgrade then reboot the BBB, before continuing.

Check that the firmware exists:
# ls /lib/firmware/BB-SPI0-01-00A0.*
Output: 

/lib/firmware/BB-SPI0-01-00A0.dtbo

Then:
# echo BB-SPI0-01 > /sys/devices/bone_capemgr.*/slots
# cat /sys/devices/bone_capemgr.*/slots
Output: 

 0: 54:PF--- 
 1: 55:PF--- 
 2: 56:PF--- 
 3: 57:PF--- 
 4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G
 5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI
 7: ff:P-O-L Override Board Name,00A0,Override Manuf,BB-SPI0-01

Verify that the spidev device now exists:
# ls -al /dev/spid*
Output: 

crw-rw---T 1 root spi 153, 0 Nov 19 21:07 /dev/spidev1.0

Now the BBB is ready to be used for flashing. Make this persist across reboots:
In /etc/default/capemgr add CAPE=BB-SPI0-01 at the end (or change the existing CAPE= entry to say that, if an entry already exists.

Get flashrom from the libreboot_util release archive, or build it from libreboot_src/git if you need to. An ARM binary (statically compiled) for flashrom exists in libreboot_util releases. Put the flashrom binary on your BBB.

You may also need ich9gen, if you will be flashing an ICH9-M laptop (such as the X200). Get it from libreboot_util, or build it from libreboot_src, and put the ARM binary for it on your BBB.

Finally, get the ROM image that you would like to flash and put that on your BBB.

Now test flashrom:
# ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512
Output: 

Calibrating delay loop... OK.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.

This means that it's working (the clip isn't connected to any flash chip, so the error is fine).

Connecting the Pomona 5250/5252

Use this image for reference when connecting the pomona to the BBB: http://beagleboard.org/Support/bone101#headers (D0 = MISO or connects to MISO).

The following shows how to connect clip to the BBB (on the P9 header), for SOIC-16 (clip: Pomona 5252): 

 NC              -       - 21
 1               -       - 17
 NC              -       - NC
 NC              -       - NC
 NC              -       - NC
 NC              -       - NC
 18              -       - 3.3V PSU RED
 22              -       - NC - this is pin 1 on the flash chip
This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack.

The following shows how to connect clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): 

 18              -       - 1
 22              -       - NC
 NC              -       - 21
 3.3V PSU RED    -       - 17 - this is pin 1 on the flash chip
This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack.

NC = no connection

DO NOT connect 3.3V PSU RED yet. ONLY connect this once the pomona is connected to the flash chip.

You also need to connect the BLACK wire from the 3.3V PSU to pin 2 on the BBB (P9 header). It is safe to install this now (that is, before you connect the pomona to the flash chip).

if you need to extend the 3.3v psu leads, just use the same colour M-F leads, but keep all other leads short (10cm or less)

You should now have something that looks like this:

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Notes about stability

http://flashrom.org/ISP has some useful information about how to make flashing more reliable. Currently, we use spispeed=512 but it is possible to make some mods so that higher speeds can be used without any instability.

tty0_ in the coreboot IRC channel had this to say: 

<stefanct> http://flashrom.org/ISP
<stefanct> i was even using 220 ohm today
<tty0_> fchmmr: I flash with 20MHz. But had to do a lot of stuff to make it work:
<n1cky> stefanct: got a picture?
<tty0_> I made "coax" with 0.1 mm core  and aluminum foley (from my kitchen), add 100 Ohm resistors (serial)
<tty0_> above the aluminum foley i've put heatshrink
<stefanct> i think that's a bit overkill :)
<tty0_> did this for: CS, CLK, D0, D1
<tty0_> i can flash with 50MHz
* roxfan has quit (Ping timeout: 246 seconds)
<tty0_> I planned to take pics and explain
<fchmmr> sgsit, 50MHz / 0.5MHz = 100 times faster than what we are used to.
<kmalkki> and flashrom does not tell you the correct actual SPI clock
<tty0_> yep
<kmalkki> (for spidev on BBB)
<fchmmr> tty0_, I'm adding these notes to the libreboot documentation.
<tty0_> 512 takes forever (compared with this)
<fchmmr> tty0_, more notes from you (and photos), probably a full guide, would be very useful for a lot of people.
<tty0_> kmalkki: yes
<stefanct< and on the bbb the maximum is in the device tree
<tty0_> stefanct: If you have to do it many times it it worth i believe. I had so much problems flashing my x200t without it
<stefanct< in my case it is 16MHz
<stefanct< tty0_: if it helps... sure
<kmalkki> tty0_: so what hardware did you claim 50MHz with?
<tty0_> BBB

<tty0_> http://i.imgur.com/qHGxKpj.jpg
<tty0_> BTW, i use twisted pair as core (in case i need to put capacitors)
<tty0_> One of my early x200t attempts: http://i.imgur.com/L0fVK3i.jpg

EHCI debugging

  1. Find USB port on the target that supports EHCI debug
  2. Initial setup of BBB to act as EHCI debug dongle
  3. Patch BBB's g_dbgp module (optional, but highly recommended)
  4. Configure libreboot with EHCI debug
    1. Selecting HCD Index and USB Debug port
  5. How to get the debug logs
  6. Eneble EHCI Debug on the target's kernel (optional, recommended)
  7. References

If your computer does not boot after installing libreboot, it is very useful to get debug logs from it, from the payload (grub) and/or the kernel (if gets to there). All of them stream debug logs on the available serial (RS-232) by default. However, most of todays laptops lack RS-232 port. The other option is to stream the logs to USB EHCI debug port.

This section explains step-by-step how to setup BBB as a “USB EHCI debug dongle” and configure libreboot and the linux kernel to stream logs to it (TODO: grub).

I will refer to three computers:

Find USB port on the target that supports EHCI debug

Not all USB controllers support EHCI debug (see: EHCI Debug Port ). Even more, if a USB controller supports EHCI debug, it is available only on a single port that might or might not be exposed externally.

  1. Plug the usb stick in the first available usb port
  2. Run the script, you will get output similar to following:
    3. The following PCI devices support a USB debug port (says lspci): 0000:00:1a.0 0000:00:1d.0
The following PCI devices support a USB debug port (says the kernel): 0000:00:1a.0 0000:00:1d.0
*PCI device 0000:00:1a.0, USB bus 3, USB physical port 1*
*PCI device 0000:00:1d.0, USB bus 4, USB physical port 2*
Currently connected high-speed devices:
/:  Bus 04.Port 1: Dev 1, Class=root_hub, Driver=ehci-pci/2p, 480M
	|__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/8p, 480M
		|__ Port 7: Dev 14, If 0, Class=Hub, Driver=hub/4p, 480M
			|__ Port 1: Dev 15, If 0, Class=Hub, Driver=hub/4p, 480M
			|__ Port 3: Dev 17, If 0, Class=Hub, Driver=hub/2p, 480M
			|__ Port 4: Dev 18, If 0, Class=Hub, Driver=hub/4p, 480M
/:  Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci-pci/2p, 480M
	|__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/6p, 480M
/:  *Bus 01*.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/4p, 480M
	|__ *Port 3: Dev 31, If 0, Class=Mass Storage, Driver=usb-storage, 480M*
  3. The buses the support debug are Bus 3 (0000:00:1a.0) on Port 1 and Bus 4 (0000:00:1d.0) on port 2. Your usb stick is plugged on Bus 1, Port 3
  4. Repeat the steps, plugging the USB stick in the next available port
  5. Go through all available ports and remember(write down) those for which bus/port of the usb stick matches one of the bus/port that support debug (bold).

Remember (write down) for each port (external plug) you found that supports debug: PCI device id, the bus id, the port number, and the physical location of the usb plug.

If you do not find a match, you can not get debug over EHCI. Sorry.

1 The guys from coreboot were talking about including the script in coreboot distribution (check the status).

Initial setup of BBB to act as EHCI debug dongle

BBB must be powered with a barrel power connector since the mini-B USB plug will be used for the EHCI debug stream. So you will need:

(On BBB) The linux kernel includes module (g_dbgp that enables one of the usb ports on a computer to behave as EHCI debug dongle. Make sure you have this module available on your BBB (Debian 7.8 that comes with BBB should have it), if not, you should compile it yourself (see next section): 

ls /lib/modules/3.8.13-bone70/kernel/drivers/usb/gadget/g_dbgp.ko

Unload all other g_* modules: 

# lsmod
# rmmod g_multi
...

Then load g_dbgp : 

# modprobe g_dbgp
# lsmod # should show that g_dbgp is loaded, and no other g_*

Plug the mini-B side of the USB cable in your BBB and the A side in your target. Then one of the usb devices on your target (with lsusb ) should be: 

Bus 001 Device 024: ID 0525:c0de Netchip Technology, Inc.

If you see the device on the target, you are good to continue to the next step.

Patch BBB’s g_dbgp module (optional, but highly recommended)

For the reasons why you need this, see: EHCI Gadget Debug.
Make sure that you have cross compiling environment for arm-linux-gnueabihf setup on your host. 

$ cd $work_dir
$ git clone https://github.com/beagleboard/kernel.git
$ cd kernel
$ git checkout $mav (see above)
$ ./patch.sh
$ wget http://arago-project.org/git/projects/?p=am33x-cm3.git\;a=blob_plain\;f=bin/am335x-pm-firmware.bin\;hb=HEAD -O kernel/firmware/am335x-pm-firmware.bin
$ cp configs/beaglebone kernel/arch/arm/configs/beaglebone_defconfig

git apply ../usbdebug-gadget/v3.8-debug-gadget/0001-usb-dbgp-gadget-Fix-re-connecting-after-USB-disconne.patch
git apply ../usbdebug-gadget/v3.8-debug-gadget/0002-usb-serial-gadget-no-TTY-hangup-on-USB-disconnect-WI.patch
;
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- beaglebone_defconfig -j4@

$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j4 (is it possoble to build only the gadget modules)
$ mkdir ../tmp && make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- INSTALL_MOD_PATH=../tmp modules_install

Configure libreboot with EHCI debug

Libreboot(coreboot) should be configured with debug turned on and to push debug messages to the EHCI debug port.
If you’ve downloaded the binary distribution, you can check if it is properly configured in the following way: 

./cbfstool/i686/cbfstool $img_path extract -n config -f ./my_config

CONFIG_USBDEBUG=y (Generic Drivers -> USB 2.0 EHCI debug dongle support)
CONFIG_USBDEBUG_IN_ROMSTAGE=y (Generic Drivers -> Enable early (pre-RAM) usbdebug)
CONFIG_USBDEBUG_HCD_INDEX=<HCD Index of usb controller - see below> (Generic Drivers -> Index for EHCI controller to use with usbdebug)
CONFIG_USBDEBUG_DEFAULT_PORT=<USB Debug port - see below> (Generic Drivers -> Default USB port to use as Debug Port)

The following three are behind radio button in the menu. Only the first one2 should be = y 

USBDEBUG_DONGLE_STD=y                       (Generic Drivers -> Type of dongle (Net20DC or compatible) -> Net20DC or compatible)
CONFIG_USBDEBUG_DONGLE_BEAGLEBONE=n         (Generic Drivers -> Type of dongle (Net20DC or compatible) -> BeagleBone)
CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK=n   (Generic Drivers -> Type of dongle (Net20DC or compatible) -> BeagleBone Black)

2 The g_dbgp module on BeagleBone Black (Rev. C) reports it self as Net20DC, the other options are for older BB(B) - ver1. This is documented here (also tested/verified).

Then:

CONFIG_CONSOLE_USB=y (Console -> USB dongle console output)

Also Debugging ---> Output verbose XYZ ) (FIXME somebody verify these): 

CONFIG_DEBUG_CBFS=y (Output verbose CBFS debug messages )
CONFIG_HAVE_DEBUG_RAM_SETUP=y (??? What/where is this)
CONFIG_DEBUG_RAM_SETUP=y (Output verbose RAM init debug messages)
CONFIG_DEBUG_SMI=y      (Output verbose SMI debug messages)
CONFIG_DEBUG_ACPI=y     (Output verbose ACPI debug messages )
CONFIG_DEBUG_USBDEBUG=y (Output verbose USB 2.0 EHCI debug dongle messages)

If some of the above mentioned configuration options are not as specified, you have to configure and compile libreboot yourself. Please refer to the doc(FIXME: link about compiling libreboot.

Selecting HCD Index and USB Debug port

This applies (and works) only if the USB controller that supports debug (found in the first section) is from Intel.
If the PCI ID of the port you found in the first section is 0000:00:1a.0 or 0000:00:1d.0 , you are ok. Otherwise you have to try without guarantee that will work.

If the externally exposed port is on a bus with PCI ID == 0000:00:1a.0 then for CONFIG_USBDEBUG_HCD_INDEX choose 2, otherwise choose 0 .

For CONFIG_USBDEBUG_DEFAULT_PORT choose the port from the first section that correspond to the PCI ID

Notes:
The above is based on the implementation of coreboot/src/southbridge/intel/common/usb_debug.c : pci_ehci_dbg_dev() .
This is enough as it applies for the supported GM45/G45 Thinkpads. coreboot support some other contollers too, but they are irellevent for libreboot (for now).

How to get the debug logs

stty -icrnl -inlcr -F /dev/ttyGS0
cat /dev/ttyGS0

Note that this is not permanent on BBB, if you reboot it, you have to rmmod g_* and modprobe g_dbgp

Eneble EHCI Debug on the target’s kernel (optional, recommended)

You have to know how to compile kernel for your target.

  1. Check if early debugging is already enabled: grep CONFIG_EARLY_PRINTK_DBGP /boot/config-<ver>
  2. If enabled, you do not have to compile the kernel (skip this step). Otherwise, prepare kernel source for your distribution and select (Kernel hacking -> Early printk via EHCI debug port). Compile and install the new kernel.
  3. Edit your grub configuration and add following to the kenel parameters2021: earlyprintk=dbgp,keep. Also, try: earlyprintk=dbgp<N>,keep where N is the debug port id if the first does not work.

References

10 EHCI Debug Port

11 coreboot EHCI debug gadget demonstration

12 EHCI Gadget Debug

13 Ehci-debug-gadget-patches.tar.gz

14 Compiling the BeagleBone Black Kernel

15 http://dumb-looks-free.blogspot.ca/2014/06/beaglebone-black-bbb-compile-kernel.html

16 http://dumb-looks-free.blogspot.fr/2014/06/beaglebone-black-bbb-kernal-headers.html

17 Building BBB Kernel

18 http://komposter.com.ua/documents/USB-2.0-Debug-Port%28John-Keys%29.pdf

19 Exploring USB at the Hardware/Software Interface

20 https://www.kernel.org/doc/Documentation/x86/earlyprintk.txt

21 https://wiki.ubuntu.com/Kernel/Debugging/USBearlyprintk

TODO:

  1. grub does not send messages to EHCI debug. Investigate.
  2. The section “Configure libreboot with EHCI debug” can be skipped/simplified if a common configuration works for all relevant targets is selected as defualt
  3. Patch and compule g_dbgp on BBB instead cross-compile
  4. Find a simple way to send debug messages from targets userland

Copyright © 2014, 2015 Francis Rowe <info@gluglug.org.uk>
Copyright © 2015 Patrick "P. J." McDermott <pj@pehjota.net>
Copyright © 2015 Pi Van Den Cirkel <opdecirkel@gmail.com>
This document is released under the Creative Commons Attribution-ShareAlike 4.0 International Public License and all future versions. A copy of the license can be found at ../license.txt.

This document is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See ../license.txt for more information.