From 26e0d10cf2f3865a16c5c2e6aff267575be795c4 Mon Sep 17 00:00:00 2001
From: Leah Woods <info@minifree.org>
Date: Fri, 13 May 2016 21:37:07 -0400
Subject: Add support for 4th C-STATE on ThinkPad X60 (courtesy of avph on IRC)

---
(limited to 'resources/libreboot')

diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0003-c4.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0003-c4.patch
new file mode 100644
index 0000000..f0777e3
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0003-c4.patch
@@ -0,0 +1,77 @@
+From 498e5a8ae9c5384ca6648ace0180fe896976d28b Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Fri, 13 May 2016 00:07:36 +0200
+Subject: [PATCH] x60: restyle _CST table, add C4 state
+
+First of all requesting low power acpi c-states
+has two software interfaces:
+Using P_LVLx I/O reads or using equivalent MWAIT requersts.
+Since newer intel boards in coreboot use MWAIT, I tried to
+make the x60 c-states consistent with that.
+
+The C4 state is a lower power state that is only entered
+when both cores request it, else the core remains in C3.
+The power and latency are arbitrary but according to
+documentation the OS is supposed to handle this fine.
+
+In practice the x60 seems not to use noticable less power
+with c4 enabled.
+
+TEST= Build and boot platform. See if there is a state4
+in /sys/devices/system/cpu/cpu0/cpuidle/
+
+Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+---
+
+diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
+index 5ea4221..1db44f5 100644
+--- a/src/mainboard/lenovo/x60/mainboard.c
++++ b/src/mainboard/lenovo/x60/mainboard.c
+@@ -38,10 +38,43 @@
+ 
+ #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT
+ 
++#define MWAIT_RES(state, sub_state)                         \
++	{                                                   \
++	  .space_id = ACPI_ADDRESS_SPACE_FIXED,		    \
++	  .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,          \
++	  .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,          \
++	  {						    \
++		  .resv = 0,				    \
++	  },						    \
++	  .addrl = (((state) << 4) | (sub_state)),          \
++	  .addrh = 0,                                       \
++	}
++
+ static acpi_cstate_t cst_entries[] = {
+-	{ 1,  1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
+-	{ 2,  1,  500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
+-	{ 2, 17,  250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
++	{
++		.ctype = 1,
++		.latency = 1,
++		.power = 1000,
++		.resource = MWAIT_RES(0, 0),
++	},
++	{
++		.ctype = 2,
++		.latency = 1,
++		.power = 500,
++		.resource = MWAIT_RES(1, 0),
++	},
++	{
++		.ctype = 3,
++		.latency = 17,
++		.power = 250,
++		.resource = MWAIT_RES(2, 0),
++	},
++	{
++		.ctype = 3,
++		.latency = 34,
++		.power = 200,
++		.resource = MWAIT_RES(3, 0),
++	},
+ };
+ 
+ int get_cst_entries(acpi_cstate_t **entries)
--
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