From d1f408f3725aa02bc1d76c4c6aadb4697bd073c0 Mon Sep 17 00:00:00 2001 From: Francis Rowe Date: Sat, 02 Jan 2016 17:10:32 -0500 Subject: Use different coreboot revisions and patches per board The release archives will be bigger, but this is a necessary change that makes libreboot development easier. At present, there are boards maintained in libreboot by different people. By doing it this way, that becomes much easier. This is in contrast to the present situation, where a change to one board potentially affects all other boards, especially when updating to a new version of coreboot. Coreboot-libre scripts, download scripts, build scripts - everything. The entire build system has been modified to reflect this change of development. For reasons of consistency, cbfstool and nvramtool are no longer included in the util archives. --- (limited to 'resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch') diff --git a/resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch b/resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch deleted file mode 100644 index 5d2b74f..0000000 --- a/resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 5045c1b894492d4e818c41861d2c21e4eef242b4 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson -Date: Sat, 27 Jun 2015 17:52:45 -0500 -Subject: [PATCH 081/143] northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot - failure - -Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e -Signed-off-by: Timothy Pearson ---- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 28 +++++++++++++++++++------- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 8 +++++++- - 2 files changed, 28 insertions(+), 8 deletions(-) - -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index f3d5cb8..cfdfd43 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -@@ -1628,6 +1628,11 @@ restartinit: - HTMemMapInit_D(pMCTstat, pDCTstatA); /* Map local memory into system address space.*/ - mctHookAfterHTMap(); - -+ if (!is_fam15h()) { -+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); -+ CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ -+ } -+ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n"); - mctHookAfterCPU(); /* Setup external northbridge(s) */ - -@@ -1651,6 +1656,11 @@ restartinit: - printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); - DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ - -+ if (!is_fam15h()) { -+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); -+ UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ -+ } -+ - if (!allow_config_restore) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n"); - mct_OtherTiming(pMCTstat, pDCTstatA); -@@ -1671,11 +1681,13 @@ restartinit: - MCTMemClr_D(pMCTstat,pDCTstatA); - } - -- printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); -- CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ -+ if (is_fam15h()) { -+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); -+ CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ - -- printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); -- UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ -+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); -+ UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ -+ } - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { -@@ -6345,11 +6357,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, - DramMRS |= 1 << 1; - - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); -- dword |= DramMRS; -- if (is_fam15h()) -+ if (is_fam15h()) { -+ dword |= DramMRS; - dword &= ~0x00800003; -- else -+ } else { - dword &= ~0x00fc2f8f; -+ dword |= DramMRS; -+ } - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x84, dword); - } - -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c -index 011a94f..57641a1 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c -@@ -908,9 +908,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, - * Flush the receiver FIFO - * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO - */ -- -+ /* FIXME -+ * This does not seem to be needed, and has a tendency to lock up the -+ * boot process while attempting to write the test pattern. -+ */ -+#if 0 -+ SetUpperFSbase(TestAddr0); - WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1); - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0); -+#endif - } - MaxDelay_CH[Channel] = CTLRMaxDelay; - } --- -1.7.9.5 - -- cgit v0.9.1