From 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 Mon Sep 17 00:00:00 2001
From: Francis Rowe <info@gluglug.org.uk>
Date: Sat, 17 Oct 2015 11:10:53 -0400
Subject: New board: ASUS KGPE-D16

coreboot build errors:

In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
 static inline enum cb_err get_option(void *dest, const char *name)
                           ^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
 enum cb_err get_option(void *dest, const char *name);

Ping tpearson about this.

Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.
---
(limited to 'resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch')

diff --git a/resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch b/resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch
new file mode 100644
index 0000000..095f3e7
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch
@@ -0,0 +1,83 @@
+From d70984fcd30907e57adb6017e0c36b295b354be3 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+Date: Fri, 12 Jun 2015 19:43:38 -0500
+Subject: [PATCH 059/146] southbridge/amd/sr5650: Fix GPP3a link training in
+ higher width modes
+
+---
+ src/southbridge/amd/sr5650/pcie.c |   51 ++++++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 4 deletions(-)
+
+diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
+index d306b5a..79f2a5f 100644
+--- a/src/southbridge/amd/sr5650/pcie.c
++++ b/src/southbridge/amd/sr5650/pcie.c
+@@ -249,7 +249,7 @@ static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev)
+ 		reg |= 0xFF0BAA0;
+ 		break;
+ 	default:	/* shouldn't be here. */
+-		printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n");
++		printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check your devicetree.cb\n");
+ 		break;
+ 	}
+ 	nbmisc_write_index(nb_dev, 0x26, reg);
+@@ -722,10 +722,53 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+ 
+ 		/* check port enable */
+ 		if (cfg->port_enable & (1 << port)) {
+-			PcieReleasePortTraining(nb_dev, dev, port);
++			uint32_t hw_port = port;
++			switch (cfg->gpp3a_configuration) {
++			case 0x1: /* 4:2:0:0:0:0 */
++				if (hw_port == 9)
++					hw_port = 4 + 1;
++				break;
++			case 0x2: /* 4:1:1:0:0:0 */
++				if (hw_port == 9)
++					hw_port = 4 + 1;
++				else if (hw_port == 10)
++					hw_port = 4 + 2;
++				break;
++			case 0xc: /* 2:2:2:0:0:0 */
++				if (hw_port == 6)
++					hw_port = 4 + 1;
++				else if (hw_port == 9)
++					hw_port = 4 + 2;
++				break;
++			case 0xa: /* 2:2:1:1:0:0 */
++				if (hw_port == 6)
++					hw_port = 4 + 1;
++				else if (hw_port == 9)
++					hw_port = 4 + 2;
++				else if (hw_port == 10)
++					hw_port = 4 + 3;
++				break;
++			case 0x4: /* 2:1:1:1:1:0 */
++				if (hw_port == 6)
++					hw_port = 4 + 1;
++				else if (hw_port == 7)
++					hw_port = 4 + 2;
++				else if (hw_port == 9)
++					hw_port = 4 + 3;
++				else if (hw_port == 10)
++					hw_port = 4 + 4;
++				break;
++			case 0xb: /* 1:1:1:1:1:1 */
++				break;
++			default:  /* shouldn't be here. */
++				printk(BIOS_WARNING, "invalid gpp3a_configuration\n");
++				return;
++			}
++			PcieReleasePortTraining(nb_dev, dev, hw_port);
+ 			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
+-				u8 res = PcieTrainPort(nb_dev, dev, port);
+-				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
++				u8 res = PcieTrainPort(nb_dev, dev, hw_port);
++				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x hw_port=0x%x result=%d\n",
++					port, hw_port, res);
+ 				if (res) {
+ 					AtiPcieCfg.PortDetect |= 1 << port;
+ 				} else {
+-- 
+1.7.9.5
+
--
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