From 0622df6194dbb1b2120743c0fd1cc5e72c380128 Mon Sep 17 00:00:00 2001
From: Francis Rowe <info@gluglug.org.uk>
Date: Sun, 18 Oct 2015 19:12:53 -0400
Subject: KGPE-D16: update patch set (also update coreboot and vboot)

Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed

Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
---
(limited to 'resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch')

diff --git a/resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch b/resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch
new file mode 100644
index 0000000..6c11daf
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch
@@ -0,0 +1,37 @@
+From b0454d907b46b7d117a8778e18aa01c4258aeb1a Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Fri, 12 Jun 2015 19:43:06 -0500
+Subject: [PATCH 056/139] northbridge/amd/amdmct: Fix hang on boot due to
+ invalid array access
+
+Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+index 86a0b14..0a31aad 100644
+--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
++++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+@@ -344,7 +344,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
+ 	}
+ 
+ #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+-	for (i = 0; i < 15; i = i + 2) {
++	for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) {
+ 		if (pDCTstat->DIMMValid & (1 << i))
+ 			ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i];
+ 		if (pDCTstat->DIMMValid & (1 << (i + 1)))
+@@ -355,7 +355,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
+ 	for (i = 0; i < 2; i++) {
+ 		sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i];
+ 		highest_rank_count[i] = 0x0;
+-		for (dimm = 0; dimm < 8; dimm++) {
++		for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
+ 			if (pDCTData->DimmRanks[dimm] > highest_rank_count[i])
+ 				highest_rank_count[i] = pDCTData->DimmRanks[dimm];
+ 		}
+-- 
+1.9.1
+
--
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