From d1f408f3725aa02bc1d76c4c6aadb4697bd073c0 Mon Sep 17 00:00:00 2001 From: Francis Rowe Date: Sat, 02 Jan 2016 17:10:32 -0500 Subject: Use different coreboot revisions and patches per board The release archives will be bigger, but this is a necessary change that makes libreboot development easier. At present, there are boards maintained in libreboot by different people. By doing it this way, that becomes much easier. This is in contrast to the present situation, where a change to one board potentially affects all other boards, especially when updating to a new version of coreboot. Coreboot-libre scripts, download scripts, build scripts - everything. The entire build system has been modified to reflect this change of development. For reasons of consistency, cbfstool and nvramtool are no longer included in the util archives. --- (limited to 'resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0094-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch') diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0094-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0094-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch new file mode 100644 index 0000000..ac80918 --- /dev/null +++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0094-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch @@ -0,0 +1,110 @@ +From 518f3db1ecce1fe883074b133eb19e3575098f3a Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Sun, 2 Aug 2015 21:31:17 -0500 +Subject: [PATCH 094/143] cpu/amd/family_10h-family_15h: Set northbridge + throttle values + +Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102 +Signed-off-by: Timothy Pearson +--- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 21 +--------- + .../amd/family_10h-family_15h/model_10xxx_init.c | 44 ++++++++++++++++++++ + 2 files changed, 45 insertions(+), 20 deletions(-) + +diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c +index 7d303e0..d770f38 100644 +--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c ++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c +@@ -877,6 +877,7 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) + else + linktype |= HTPHY_LINKTYPE_UNGANGED; + } ++ + return linktype; + } + +@@ -971,26 +972,6 @@ void cpuSetAMDMSR(uint8_t node_id) + } + AMD_Errata298(); + +- if (revision & AMD_FAM15_ALL) { +- uint32_t f5x80; +- uint8_t enabled; +- uint8_t compute_unit_count = 0; +- f5x80 = pci_read_config32(NODE_PCI(node_id, 5), 0x80); +- enabled = f5x80 & 0xf; +- if (enabled == 0x1) +- compute_unit_count = 1; +- if (enabled == 0x3) +- compute_unit_count = 2; +- if (enabled == 0x7) +- compute_unit_count = 3; +- if (enabled == 0xf) +- compute_unit_count = 4; +- msr = rdmsr(BU_CFG2); +- msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ +- msr.lo |= (((compute_unit_count - 1) & 0x3) << 6); +- wrmsr(BU_CFG2, msr); +- } +- + /* Revision C0 and above */ + if (revision & AMD_OR_C0) { + uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); +diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +index 5c590b8..7319539 100644 +--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c ++++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +@@ -158,6 +158,50 @@ static void model_10xxx_init(device_t dev) + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + #endif + ++ /* Set bus unit configuration */ ++ if (is_fam15h()) { ++ uint32_t f5x80; ++ uint8_t enabled; ++ uint8_t compute_unit_count = 0; ++ f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80); ++ enabled = f5x80 & 0xf; ++ if (enabled == 0x1) ++ compute_unit_count = 1; ++ if (enabled == 0x3) ++ compute_unit_count = 2; ++ if (enabled == 0x7) ++ compute_unit_count = 3; ++ if (enabled == 0xf) ++ compute_unit_count = 4; ++ msr = rdmsr(BU_CFG2_MSR); ++ msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ ++ msr.lo |= (((compute_unit_count - 1) & 0x3) << 6); ++ wrmsr(BU_CFG2_MSR, msr); ++ } else { ++ uint32_t f0x60; ++ uint32_t f0x160; ++ uint8_t core_count = 0; ++ uint8_t node_count = 0; ++ f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60); ++ core_count = (f0x60 >> 16) & 0x1f; ++ node_count = ((f0x60 >> 4) & 0x7) + 1; ++ if (is_gt_rev_d()) { ++ f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160); ++ core_count |= ((f0x160 >> 16) & 0x7) << 5; ++ } ++ core_count++; ++ core_count /= node_count; ++ msr = rdmsr(BU_CFG2_MSR); ++ if (is_gt_rev_d()) { ++ msr.hi &= ~(0x3 << (36 - 32)); /* ThrottleNbInterface[3:2] */ ++ msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32)); ++ } ++ msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ ++ msr.lo |= (((core_count - 1) & 0x3) << 6); ++ msr.lo &= ~(0x1 << 24); /* WcPlusDis = 0 */ ++ wrmsr(BU_CFG2_MSR, msr); ++ } ++ + /* Disable Cf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); +-- +1.7.9.5 + -- cgit v0.9.1