From d1f408f3725aa02bc1d76c4c6aadb4697bd073c0 Mon Sep 17 00:00:00 2001 From: Francis Rowe Date: Sat, 02 Jan 2016 17:10:32 -0500 Subject: Use different coreboot revisions and patches per board The release archives will be bigger, but this is a necessary change that makes libreboot development easier. At present, there are boards maintained in libreboot by different people. By doing it this way, that becomes much easier. This is in contrast to the present situation, where a change to one board potentially affects all other boards, especially when updating to a new version of coreboot. Coreboot-libre scripts, download scripts, build scripts - everything. The entire build system has been modified to reflect this change of development. For reasons of consistency, cbfstool and nvramtool are no longer included in the util archives. --- (limited to 'resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0087-northbridge-amd-amdmct-Reduce-maximum-number-of-DDR3.patch') diff --git a/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0087-northbridge-amd-amdmct-Reduce-maximum-number-of-DDR3.patch b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0087-northbridge-amd-amdmct-Reduce-maximum-number-of-DDR3.patch new file mode 100644 index 0000000..08333f6 --- /dev/null +++ b/resources/libreboot/patch/coreboot/33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f/grub/kgpe-d16/0087-northbridge-amd-amdmct-Reduce-maximum-number-of-DDR3.patch @@ -0,0 +1,41 @@ +From e262fc3ee190bafb58adfab926cc24ff9cbd239c Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Tue, 20 Oct 2015 21:32:09 -0500 +Subject: [PATCH 087/143] northbridge/amd/amdmct: Reduce maximum number of + DDR3 DIMMs + +CAR space on certain platforms is nearly full. This prevents the +addition of necessary RAM initialization features such as x4 DIMM +support. As the DIMM SPD cache uses a sizeable amount of CAR RAM, +reducing it would free up a significant amount of CAR RAM. + +DDR3-based AMD platforms only support up to 3 physical DIMMs on +each channel (6 per node). Reduce the maximum number of DIMMs +on a node from 8 to 6 accordingly. + +Change-Id: I38def86da76fc622785318c825670209b2ac9017 +Signed-off-by: Timothy Pearson +--- + src/northbridge/amd/amdmct/wrappers/mcti.h | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h +index 2aba377..ef6e3dc 100644 +--- a/src/northbridge/amd/amdmct/wrappers/mcti.h ++++ b/src/northbridge/amd/amdmct/wrappers/mcti.h +@@ -51,7 +51,11 @@ UPDATE AS NEEDED + #endif + + #ifndef MAX_DIMMS_SUPPORTED +-#define MAX_DIMMS_SUPPORTED 8 ++#if IS_ENABLED(CONFIG_DIMM_DDR3) ++ #define MAX_DIMMS_SUPPORTED 6 ++#else ++ #define MAX_DIMMS_SUPPORTED 8 ++#endif + #endif + + #ifndef MAX_CS_SUPPORTED +-- +1.7.9.5 + -- cgit v0.9.1